JP2006294011A - Control program development support apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control program development support apparatus capable of providing a display by which it can be recognized at a glance, whether a memory currently being used in a certain program module is also being used in other program module. <P>SOLUTION: The control program development support apparatus, which analyzes a control program constituted of a plurality of program modules, includes an analysis means for reading the control program and analyze a duplication usage situation of a memory address being used among the program modules, and an analysis result display means for displaying an analyzed result by the analysis means. Duplication usage situation of a memory address for each program module can be displayed to other program modules. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a control program development support apparatus suitable for developing a control program (user program) for a programmable controller (hereinafter referred to as PLC).

  2. Description of the Related Art A control program development support device (hereinafter referred to as a development support device) is known as a device that supports creation of a control program (user program) executed by a PLC. When creating a user program using this development support apparatus, existing programs are often used.

  Normally, a user program is composed of a plurality of program modules, and there is a memory address that is commonly referred to between different program modules. Thus, when there is a memory address that is commonly referred to between different program modules, care must be taken when diverting the program module. Failure to do so may cause an unexpected malfunction.

  A reference table called a cross reference is known as a method for searching where a certain memory address is used in a user program. Note that various known techniques are known for searching using a cross reference (see, for example, Patent Document 1).

An example of cross reference display is shown in FIG. In this example, it is indicated that the memory address “A200.11” is used in the program module having the section name “section 1” constituting the program having the program name “new program 1”. Further, as a use place in the program module, the program address is “0”, which indicates that it is used as an operand of “LD” after the instruction.
JP 2003-243269 A

  However, the conventional cross-reference display is the center of the memory address in which the name of the program module in which a certain memory address is used, the use location in the program module, etc. are displayed side by side on the same line with the memory address at the beginning of the line. Is displayed. Therefore, since it was not possible to understand at a glance whether or not a memory address used in a certain program module is also used in another program module, a problem of being unusable is pointed out. In addition, when diverting a PLC user program that uses a conventionally provided function for sharing data among multiple PLCs (referred to as a data link function), share the data with other PLCs. In spite of the need to pay attention to the memory address of the memory area, there is a problem that it is not displayed in the conventional cross-reference display.

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to determine at a glance whether a memory address used in a certain program module is also used in another program module. It is an object of the present invention to provide a control program development support apparatus that can provide a display that can be understood.

  The control program development support device according to the present invention is a control program development support device that analyzes a control program composed of a plurality of program modules, reads the control program, and uses the memory address that is being used between the program modules. Analysis means and analysis result display means for displaying the result of analysis by the analysis means, and it is possible to display the overlapping use status of the memory addresses used with other program modules for each program module.

  According to such a configuration, it is possible to display to the user so that it can be understood at a glance whether or not a memory address used in a certain program module is also used in another program module.

  In a preferred embodiment of the present invention, the analysis means analyzes whether or not the control program is composed of a plurality of PLC control programs, and the analysis result display means is an analysis means that controls the plurality of PLCs. If it is analyzed that the program is composed of programs, the program modules may be grouped by PLC to display the overlapping usage status of the used memory addresses.

  According to such a configuration, it is possible to display to the user so that it can be understood at a glance whether or not a memory address used in one PLC is also used in another PLC.

  In a preferred embodiment of the present invention, the analysis result display means, when the memory address used in the program module for each program module is also used in other program modules, the duplicate use is performed. The use status of the used memory address may be displayed in association with the program module name being used.

  According to such a configuration, it is possible to display to the user so that it can be understood at a glance whether a memory address used in a certain program module is used in any program module.

  In a preferred embodiment of the present invention, the analyzing means analyzes whether or not the program module constituting the control program has a hierarchical structure, and if it is analyzed that there is a hierarchical structure, the analyzing means stores the hierarchical structure and the used memory address. The duplicate use degree of the memory address used by the program module may be calculated based on the duplicate use status, and the analysis result display means may display the duplicate use degree calculated by the analysis means.

  According to such a configuration, it is possible to display to the user so that it can be understood at a glance whether or not a memory address used in a certain hierarchy is also used in another hierarchy.

  Note that the present invention viewed from another aspect can also be grasped as a computer program for realizing the functions of the above-described devices.

  According to the present invention, it is possible to provide a display to the user so that it can be understood at a glance whether or not a memory address used in a certain program module is also used in another program module.

  In the following, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  The control program development support apparatus of the present invention can be realized, for example, by installing predetermined application software on a personal computer. Here, since the hardware configuration of a personal computer is well known in various documents, detailed description thereof is omitted in this specification.

  FIG. 1 shows an explanatory diagram of the memory usage status among tasks / sections / plural PLCs. FIG. 1 shows an example in which a PLC user program is composed of a plurality of program units called “tasks”, and each task is composed of a plurality of program modules called “sections”. In this example, it can be seen that the program module has a hierarchical structure of user programs / tasks / sections. When only one user program exists in the PLC and a control system is constructed by a plurality of PLCs, it can be considered that there is a PLC / task / section hierarchical structure. Generally, a PLC user program is often divided into a plurality of programs (tasks and sections) depending on the control target and function. Also, these multiple programs (tasks, sections) often access the same memory. Furthermore, the data link function can share the memory between PLCs without a program by a parameter defining an area to be linked.

  This data link function will be described with reference to FIGS. FIG. 11 is a diagram for explaining the concept of the data link function. In this example, data sharing by a data link function between three nodes (nodes 1 to 3) is shown. Here, the node corresponds to a PLC. Data of 100 words is transmitted from the memory address DM0 of the node 1 to the nodes 2 and 3. Also, 100 words of data are transmitted from the DM 100 of the node 2 to the nodes 1 and 3. Further, 150 words of data are transmitted from the DM 200 of the node 3 to the nodes 1 and 2. The above is a description of transmission of each node to another node.

  Next, data reception at the node 1 will be described. In this example, the node 1 stores the data transmitted from the node 2 from the DM 100 and stores the data transmitted from the node 3 from the DM 200. Information about transmission data and reception data at each node is managed by a table called a data link table. FIG. 12 shows an example of the data link table. This example shows the data link table of node 1 in FIG. The node number column indicates the data link target node, the local node link start memory address indicates the transmission / reception start memory address of the local node (node 1 in this example), and the link data size indicates the transmission / reception data size. The other node link start memory address indicates the transmission start memory address of the other node. By referring to this data link table, node 1 transmits data for 100 words from DM0 to another node, and stores data received from node 2 (data for 100 words from DM100 of node 2) from DM100. It can be seen that the data received from the node 3 (the data for 150 words from the DM 200 of the node 3) may be stored from the DM 200. Thus, in the PLC user program, memory sharing is possible between a plurality of programs or between a plurality of PLCs.

  In the control program development support apparatus of the present invention, the link status of the memory between these multiple programs / plural PLCs can be accurately displayed to the user.

  FIG. 1 shows an example in which the same memory is used among a plurality of programs / plural PLCs. In this example, there are two PLCs consisting of PLC1 and PLC2.

  The user program of PLC 1 includes two tasks consisting of task 1 and task 2. Task 1 includes three sections including section 1, section 2, and section 3. Similarly, task 2 includes two sections consisting of section 4 and section 5.

  On the other hand, four areas indicated by (A), (B), (C), and (D) are provided in the memory of the PLC 1 as memory areas that can be accessed via instruction words constituting the user program. Yes. Of these, area (A) is an area that is accessed only from section 1 in task 1. Area (B) is an area that is commonly accessed from section 2 and section 3 in task 1. Area (C) is an area that is commonly accessed by section 3 in task 1 and section 4 in task 2. Further, the area (D) is accessed from the section 5 of the task 2 in the program of the PLC 1 and is also an area shared by the data area and the memory area (D) of the PLC 2.

  In other words, the memory of the PLC 1 includes a memory (A) used in a single section, a memory (B) used in a plurality of sections of a single task, and a memory (C) used in a section of a plurality of tasks. ), There is a memory (D) used between the plurality of PLCs.

  As described above, if a part of the program is diverted or modified from a complicated system in which a part of the PLC memory is shared by various program parts, an unexpected malfunction may occur.

  Therefore, when remodeling or diverting from such a complex system, it is necessary to analyze the usage status of each part in the memory and accurately grasp the sharing relationship.

  The above-mentioned conventional cross-reference function uses the memory address used in a single section, the memory address used in multiple sections of a single task, the memory address used in a section of multiple tasks, and between multiple PLCs. Although it is useful for analyzing and grasping the memory addresses used, etc., the memory sharing status (task / section) between each task / section, which is a unit for modification and diversion based on such memory separation (usage status) Cannot be analyzed.

  That is, a section that does not share memory with other sections (for example, section 1), a section that shares memory with other sections within the own task (for example, section 2), a section that shares memory with other tasks (for example, section 3 / The analysis of section 4) and a section sharing memory with other PLCs (for example, section 5) cannot be realized by the conventional cross-reference function.

  On the other hand, in the device of the present invention described below, it is possible to accurately analyze the memory sharing relationship and display it to the user in an easy-to-understand manner. In connection with the present invention, FIG. 2 shows a flowchart of the analysis processing of the memory usage status between tasks / sections incorporated in a personal computer.

  When the processing is started in the figure, first, in step 201, the memory usage situation for each section in the user program is analyzed. That is, according to the previous example shown in FIG. 1, the memory usage situation for each of the sections 1 to 5 in the PLC 1 is analyzed.

  In the subsequent step 202, the memory sharing status between other PLCs is analyzed based on a separately prepared data link table. That is, in the example of FIG. 1, it is analyzed that the area (D) in the memory of the PLC 1 and the area (D) in the memory of the PLC 2 are in a shared state. Details of the analysis of the memory sharing status between other PLCs based on this data link table will be described with reference to the example of FIG. In the example of FIG. 12, the memory addresses shared with other PLCs are found by reading the contents of the own node link start memory address column and the link data size column. In this example, memory addresses of 100 words (DM0 to 99) from the memory address DM0, 100 words from DM100 (DM100 to DM199), and 150 words from DM200 (DM200 to DM349) are shared with other PLCs. It turns out.

  The above process is repeated for all sections (section 1 to section 5) (step 203 NO). In the meantime, when the analysis processing is completed for all sections (section 1 to section 5) (YES in step 203), in step 204, a portion using the same memory is extracted between sections. That is, according to the example of FIG. 1, the sections related to the areas (B) and (C) are extracted.

  In the following step 205, section attributes are classified. In the example of FIG. 1, classification of which section or PLC corresponds to the section is performed.

  In the next step 206, a section unit memory usage list is created and displayed on the screen of the personal computer.

  Next, a specific user program is given as an example, and the analysis result and display mode when the processing shown in FIG. 2 is performed based on this will be described.

  Assume that a user program structure as shown in FIG. 3 exists. This user program represents the user program of the PLC 1 and shows an example in the case where there is no memory sharing with other PLCs. In the user program of the PLC 1, there are two tasks consisting of task 1 and task 2. Each of these tasks 1 and 2 has one section (section 1).

  The task 1 / section 1 of the PLC 1 uses a memory address represented by DM0 / DM1 / DM2. In addition, the task 2 / section 1 of the PLC 1 uses a memory address represented by DM10 / EM0 / WR10. In this example, “DM”, “EM”, and “WR” are character strings representing the types of memory areas. The numbers following “DM”, “EM”, and “WR” represent addresses within the memory area type. As described above, a memory address may be expressed by a combination of a character string representing the type of the memory area and a number representing the address in the type of the memory area.

  An explanatory diagram of data stored in the RAM of the personal computer is shown in FIG. The structure of the user program shown in FIG. 3 is stored as data in the RAM of the personal computer, as shown in FIG. As an example, in the data indicated by the pointer P, the RAM address 1 stores the memory address “DM0” and the data “1” for identifying the task 1 / section 1. In the example of FIG. 4, “1” and “2” correspond to data identifying task 1 / section 1 and task 2 / section 1, respectively.

  A flowchart of the processing of the analysis tool is shown in FIG. When processing is started on the premise of the data structure shown in FIG. 4, the task / section No. is initially set to “1” in step 501.

  In the subsequent step 502, the task / section No. RAM address is input to the pointer P. In the subsequent step 503, the value of the No counter Num is initialized to “1”.

  Thereafter, while updating the pointer P and the counter Num by 1, the memory address acquisition process until the memory address becomes 0 (step 504), the PLC task section No. and the count No. corresponding to the memory address. The Num extraction process (step 505) is repeatedly executed.

  Meanwhile, if the memory address is determined to be 0 (step 507 YES), the task / section No. is updated by 1 (step 508), and the above operations (steps 502 to 508) are repeated and registered. The process ends after the completion of the repetition of the number of task / section numbers (which is 2 in the example of FIG. 4) (YES in step 509).

When the processing shown in FIG. 5 is executed and the program is analyzed, the following data string is obtained.
PLC1 [1] [1] = DM0
PLC1 [1] [2] = DM1
PLC1 [1] [3] = DM2
PLC1 [2] [1] = DM10
PLC1 [2] [2] = DM0
PLC1 [2] [3] = WR10

  The format of these data is PLC1 [task / section No.] [number of registrations].

  Next, FIG. 6 shows a flowchart of a drawing process based on the obtained data. When the processing is started in the figure, in step 601, initialization processing (i = 1, j = 1) is first executed.

  In the subsequent step 602, drawing [i] [j] = PLC1 [i] [j] is processed. In the subsequent step 603, j = j + 1 is performed.

  In the subsequent step 604, a determination is made that PLC1 [i] [j] = 0. If the determination result is 0 (step 604 YES), the process proceeds to step 605, whereas if the determination result is not 0 (step 604 NO), the process returns to step 602.

  In step 605, j = 1 and i = i + 1 are performed. In the subsequent step 606, it is determined that PLC1 [i] [j] = 0. If the determination result is 0 (step 606 YES), the process ends. If not (0 in step 606), the process returns to step 602. Thereafter, the above operations are repeated.

  FIG. 7 shows an explanatory diagram of a display example of an analysis result obtained as an execution result of the drawing process shown in FIG. As is apparent from the figure, according to this display example, the memory used for each task / section number can be seen at a glance. In the example of FIG. 7, the task / section No column is displayed as a number, but the character strings “task 1 / section 1” corresponding to “1” and “task 2 / section 1” corresponding to “2” are displayed. You may do it. More specific embodiments of the present invention will be described below. An example of memory use in this case is shown in FIG.

  As shown in FIG. 8, in this example, there are two PLCs composed of PLC1 and PLC2. The user program of PLC 1 includes two tasks whose task names are control A and control B. The task of control A includes four sections whose section names are control A_1, control A_2, control A_3, and control A_4. The task of control B includes two sections whose section names are control B_1 and control B_2.

  On the other hand, the memory of the PLC 1 is provided with memory areas such as an input / output relay area, an internal auxiliary relay area, a holding relay area, a special auxiliary relay area, a data memory area, and an extended data memory.

  The input / output relay area is used by the control A_1 (section). The internal auxiliary relay area is shared by the control A_2 (section) and the control A_3 (section). The special auxiliary relay area is shared by the control A_4 (section) and the control B_1 (section). The extended data memory is used by the control B_2 (section).

  On the other hand, the PLC2 user program includes one task whose task name is control a, and one task whose section name is control a_1 is included in the task of control a.

  The extended data memory in the PLC 2 memory is used by the control a_1 (section). At the same time, the extended data memory of the PLC1 memory and the extended data memory of the PLC2 memory are shared by the data link function.

  In other words, the system shown in FIG. 8 has two PLCs consisting of PLC1 and PLC2, and the program of PLC1 has two tasks (control A, control B) and six sections (control A_1, control A_2, Control A_3, control A_4, control B_1, control B_2). The PLC2 program is composed of one task (control a) and one section (control a_1).

  FIG. 9 shows a display example of the analysis result obtained when the analysis processing according to the present invention is applied to the system configuration shown in FIG.

  As is clear from the figure, in this display example, the horizontally long rectangular area is divided into three columns in the left-right direction, and each column has “analysis section”, “link destination section”, “Number of links” is assigned.

  Further, each of these three columns is further divided into four columns in the left-right direction, and “PLC”, “task”, “section”, and “section attribute” are sequentially assigned to each column.

  On the other hand, the column assigned to the PLC and extending in the vertical direction is divided in the vertical direction for each PLC. Further, the vertical column assigned to a task is assigned to a task name included in each PLC. In addition, columns extending in the vertical direction assigned to sections are subdivided into individual section names for each task name, and columns extending in the vertical direction allocated to section attributes are described by section attributes corresponding to each section. Is done.

  Here, the section attribute “1” is a section that does not share memory with other sections, the section attribute “2” is a section that shares memory with other sections in the invoking task, and the section attribute “3” is another task. The section attribute “4” is a section having a memory share with another PLC.

  In this analysis result display example, for example, since section control A_2 has memory sharing with section control A_3 in its own task, the section attribute is “2” (memory sharing with other sections in its own task). It is displayed that the memory sharing is for the internal auxiliary relay 10CH.

  According to this embodiment, it is possible to display to the user so that it can be understood at a glance whether or not the memory used in one program module is also used in another program module.

  According to the present invention, it is possible to provide a display to the user so that it can be understood at a glance whether or not the memory used in a certain program module is also used in another program module.

It is explanatory drawing of the memory usage condition between task / section / plural PLC. It is a flowchart of the analysis process of the memory usage condition between tasks / sections. It is explanatory drawing which shows an example of the structure of a user program. It is explanatory drawing of the data preserve | saved in RAM of a personal computer. It is a flowchart of a process of an analysis tool. It is a flowchart of a drawing process. It is explanatory drawing of the example of a display of an analysis result. It is a figure which shows the example of memory use. It is a figure which shows the example of a display of an analysis result. It is a figure which shows the example of a cross reference display. It is a figure explaining the concept of a data link function. It is a figure which shows the example of a data link table.

Explanation of symbols

  A to D Memory area in memory

Claims (8)

In a control program development support device that analyzes a control program composed of a plurality of program modules,
An analysis means for reading out the control program and analyzing the overlapping usage status between the program modules of the memory addresses being used;
An analysis result display means for displaying the result analyzed by the analysis means,
A control program development support apparatus characterized in that, for each program module, it is possible to display an overlapping usage status of a memory address used with another program module. The analyzing means analyzes whether the control program is composed of a plurality of PLC control programs,
The analysis result display means, when the analysis means analyzes that the control program is composed of a plurality of PLC control programs, groups the program modules for each PLC and displays the usage status of the used memory address. The control program development support device according to claim 1.   If the analysis result display means is duplicated in other program modules among the memory addresses used in the program module for each program module, the analysis result display means will correspond to the duplicated program module name. The control program development support apparatus according to claim 1, wherein an overlapping use status of used memory addresses is displayed.   The analysis means analyzes whether or not the program module constituting the control program has a hierarchical structure, and if it is analyzed that there is a hierarchical structure, the analysis module determines the program module based on the overlapping usage status of the hierarchical structure and the used memory address. 2. The control program development support apparatus according to claim 1, wherein the degree of duplicate use of the used memory address is calculated, and the analysis result display means displays the degree of duplicate use calculated by the analysis means. Computer
An analysis means for reading a control program composed of a plurality of program modules, and analyzing the overlapping usage status between the program modules of the used memory address;
An analysis result display means for displaying the result analyzed by the analysis means,
A control program development support device capable of displaying the overlapping usage status of memory addresses used with other program modules for each program module;
Computer program to function as. The analyzing means analyzes whether the control program is composed of a plurality of PLC control programs,
The analysis result display means, when the analysis means analyzes that the control program is composed of a plurality of PLC control programs, groups the program modules for each PLC and displays the usage status of the used memory address. The computer program according to claim 5.   If the analysis result display means is duplicated in other program modules among the memory addresses used in the program module for each program module, the analysis result display means will correspond to the duplicated program module name. 6. The computer program according to claim 5, wherein an overlapping usage status of the used memory address is displayed.   The analysis means analyzes whether or not the program module constituting the control program has a hierarchical structure, and if it is analyzed that there is a hierarchical structure, the analysis module determines the program module based on the overlapping usage status of the hierarchical structure and the used memory address. 6. The computer program according to claim 5, wherein the duplicate use degree of the used memory address is calculated, and the analysis result display means displays the duplicate use degree calculated by the analysis means.

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