JP5019021B2 - Control program development support device - Google Patents

Description

  The present invention relates to a control program development support apparatus suitable for developing a control program (user program) for a programmable controller (hereinafter referred to as PLC).

  2. Description of the Related Art A control program development support device (hereinafter referred to as a development support device) is known as a device that supports creation of a control program (user program) executed by a PLC. When creating a user program using this development support apparatus, existing programs are often used.

  Usually, a user program is composed of a plurality of program modules, and may be configured to call another program module as a subroutine program within a certain program module. There is a memory address that is commonly referred to between such subroutine programs or between program modules that are not subroutine programs (subroutine calling side).

  Thus, when there is a memory address that is commonly referred to between different program modules, care must be taken when diverting the program module. Failure to do so may cause an unexpected malfunction.

  A reference table called a cross reference is known as a method for searching where a certain memory address is used in a user program. Note that various known techniques are known for searching using a cross reference (see, for example, Patent Document 1).

An example of cross reference display is shown in FIG. In this example, it is indicated that the memory address “A200.11” is used in the program module having the section name “section 1” constituting the program having the program name “new program 1”. Furthermore, as a use place in the program module, the program address is “0”, which indicates that it is used as an operand of the instruction word “LD”.
JP 2003-243269 A

  However, the conventional cross-reference display is based on the memory address center, in which the name of the program module in which a certain memory address is used, the location in the program module, etc. are displayed side by side on the same line with the memory address as the head of the line. It is displayed. Therefore, it was not possible to understand at a glance whether the memory used in a subroutine program is also used in other subroutine programs or the program module that calls the subroutine program. It has been pointed out.

  The present invention has been made by paying attention to the above-mentioned problems, and the object of the present invention is that a memory used in a certain program module is a program module that calls another subroutine program or subroutine program. It is an object of the present invention to provide a control program development support apparatus that can provide a display that can be understood at a glance whether or not it is used.

  A control program development support apparatus according to the present invention is a control program development support apparatus that analyzes a control program composed of a plurality of program modules and a plurality of subroutine programs. Analyzing means for analyzing the overlapping usage status between subroutine programs or between subroutine programs and program modules that call subroutine programs, and analysis result displaying means for displaying the results of analysis by the analyzing means, each subroutine program The present invention is characterized in that it is possible to display the overlapping usage status of memory addresses used with other subroutine programs and program modules that call subroutine programs.

  According to such a configuration, a display is provided to the user so that the user can understand at a glance whether the memory used in a certain program module is also used in another subroutine program or a program module that calls a subroutine program. can do.

  In a preferred embodiment of the present invention, the analyzing means extracts the size of the memory address to be used redundantly when analyzing the overlapping usage status of the used memory address, and the analysis result displaying means is extracted by the analyzing means. The size of the overlapping memory address may be displayed together with the subroutine program name.

  According to such a configuration, the user can accurately grasp how much memory capacity is overlapped with which subroutine program based on the display.

  The present invention viewed from another aspect can also be grasped as a computer program capable of realizing such a development support apparatus on a personal computer.

  According to the present invention, it is possible to provide a display to the user so that it can be understood at a glance whether a memory used in a certain program module is also used in another subroutine program or a program module that is not a subroutine program.

  Hereinafter, a preferred embodiment of a control program development support device according to the present invention will be described in detail with reference to the accompanying drawings.

  The control program development support apparatus of the present invention can be realized, for example, by installing predetermined application software on a personal computer. Here, since the hardware configuration of a personal computer is well known in various documents, detailed description thereof is omitted in this specification.

  An explanatory diagram of the memory use status in the subroutine is shown in FIG. The PLC program is composed of a plurality of program modules, and may be configured to read out another program module as a subroutine program within a certain program module. There is a memory address that is commonly referenced between such subroutine programs and between the subroutine program and the program module that calls the subroutine program.

  FIG. 1 shows an explanatory diagram of the memory usage status between subroutines. In FIG. 1, the PLC user program is composed of a plurality of program units called “tasks”, each task is composed of a plurality of program modules called “sections”, and each section is a subroutine called “subroutine”. An example including a program is shown.

  The PLC user program shown in FIG. 1 has three tasks whose task names are control A, control B, and control C. The control A task includes a section whose section name is control A_1, and the control A_1 includes a subroutine whose subroutine name is SUB1.

  A control B_1 (section) is included in the control B (task), and a SUB2 (subroutine) is further included in the control B_1 (section). A control C_1 (section) is included in the control C (task), and a SUB3 (subroutine) is further included in the control C_1 (section). In the PLC memory, memory areas such as an input / output relay area, an internal auxiliary relay area, a holding relay area, a special auxiliary relay area, a data memory area, and an extended data memory area are provided.

  Among them, the input / output relay area (A) is used by SUB1 (subroutine) in the control A (task). The holding relay area (B) is shared by SUB1 (subroutine) in control A (task) and SUB2 (subroutine) in control B (task). The data memory area (C) is shared by the control B_1 (section) in the control B (task) and the SUB2 (subroutine) included in the control B_1 (section). The extended data memory area (D) includes a SUB2 (subroutine) in the control B (task), a control C_1 (section) in the control C (task), and a SUB3 (subroutine) in the control C_1 (section). Shared by.

Based on this, the memory called from the subroutine can be classified as follows.
(1) Area used only within one subroutine (A)
(2) Area used in two or more subroutines (B)
(3) Area used in one subroutine and normal routine (C)
(4) Area used in two or more subroutines and normal routine (D)

  Next, FIG. 2 shows a flowchart showing an analysis process of the memory usage status between subroutines to be installed in a personal computer, for example, in order to realize the apparatus of the present invention.

  When the process is started in the figure, the process of analyzing the used memory list for each subroutine (step 201) is sequentially executed for all subroutines (NO in step 202).

  When the analysis processing of the used memory list for each subroutine (step 201) is completed for all subroutines (YES in step 202), a portion using the same memory is extracted between the subroutines (step 203), and based on this extraction result Then, a list is created, and the created list is displayed on the screen of the personal computer (step 204). When extracting the overlapping use of the memory address in step 203, the total size of the memory area specified by the overlapping memory address is obtained for each type of memory area, and the obtained size is processed in step 204. May be configured to display on the screen.

  Next, an explanatory diagram showing an example of the structure of the user program is shown in FIG. This user program includes two tasks including a task 1 and a task 2 in the PLC 1. Task 1 includes section 1 and section 1 includes one subroutine SUB1. This subroutine SUB1 uses three memory addresses represented by DM0, DM1, and DM2.

  The task 2 includes a section 1 and the section 1 includes a subroutine SUB2. This subroutine SUB2 uses three memory addresses represented by DM10, EM0, and WR10. In this example, “DM”, “EM”, and “WR” are character strings representing the types of memory areas. The numbers following “DM”, “EM”, and “WR” represent addresses within the memory area type. As described above, a memory address may be expressed by a combination of a character string representing the type of the memory area and a number representing the address in the type of the memory area.

  In other words, memory DM0 to DM2 are used in subroutine SUB1 in task 1 / section 1 of PLC1, and memory DM10 / EM0 / WR10 is used in subroutine SUB2 in task 2 / section 1 of PLC1. .

  When such a user program is created, an explanatory diagram of data stored in the RAM of the personal computer is shown in FIG. As shown in the figure, the program created by the user is stored in the RAM of the personal computer divided into a RAM address, a memory address, and a SUB number. Specifically, focusing on the position of the pointer P, RAM address 1 stores memory address “DM0” and data “1” for identifying SUB1. In the example of FIG. 4, “1” and “2” correspond to data for identifying SUB1 and SUB2, respectively.

  Next, FIG. 5 shows a flowchart of a memory list display process using subroutine units. The control program development support apparatus according to the present invention is realized by installing the program shown in this flowchart in a personal computer.

  When the processing is started in the figure, the subroutine number register (SUB_No) is set to the initial value “1”. In the subsequent step 502, the RAM address of the subroutine number register (SUB_No) is input to the pointer P. In the subsequent step 503, an initial value “1” is set in the counter (Num) (step 503).

  In the subsequent step 504, the memory address is acquired based on the subroutine number register (SUB_No) and the counter (Num) (step 504). In the following step 505, SUB [SUB_No] [NUM] is obtained based on the acquired memory address.

  In the subsequent step 506, the pointer P and the counter Num are updated by 1. In the following step 507, it is determined whether or not the acquired memory address is zero. If it is 0 (NO in step 507), the process returns to step 504 again to execute the same processing as above. On the other hand, if it is determined that the memory address is 0 (step 507 YES), the process proceeds to step 508 to update the subroutine number SUB_No by one.

  In the subsequent step 509, it is determined whether or not the above-described series of processing has been repeated for the number of subroutine numbers (SUB_No) registered in advance. Repeat the process. On the other hand, if the registered number of repetitions has been reached (YES in step 509), the execution of the program is terminated.

When the program shown in FIG. 5 is executed on the data shown in FIG. 4, the following data is generated as a result.
SUB [1] [1] = DM0
SUB [1] [2] = DM1
SUB [1] [3] = DM2
SUB [2] [1] = DM10
SUB [2] [2] = EM0
SUB [2] [3] = WR10
Here, the data format is PLC1 [SUB_No] [setting value].

  FIG. 6 shows a flowchart of the drawing process based on the data obtained above. When the processing is started in the figure, in step 601, initialization processing (i = 1, j = 1) is executed.

  In the subsequent step 602, drawing calculation processing (drawing [i] [j] = PLC1 [i] [j] is executed. In the subsequent step 603, pixel update processing (j = j + 1) is performed. In the subsequent step 604, it is determined whether or not the value of PLC1 [i] [j] is zero.

  If the determination result is 0, the process returns to step 602 and the above processing is repeated. On the other hand, if the determination result is 0 (YES in step 604), the process proceeds to step 605, and pixel update processing (j = 1, i = i + 1) is executed.

  In the subsequent step 606, it is determined whether or not PLC1 [i] [j] is zero. If the determination result is not 0 (NO in step 606), the process returns to step 602 and the same processing is executed. On the other hand, if the determination result is 0 (YES in step 606), the execution of the program ends.

  FIG. 7 shows an explanatory diagram of a display example of the analysis result obtained on the screen of the personal computer by such drawing processing. As shown in the figure, according to this display mode, the memory used in the subroutine can be known at a glance.

  Finally, the subroutine analysis process will be described with a more specific example.

  FIG. 8 is a diagram showing an example of the memory usage status in the subroutine, and FIG. 9 is a diagram showing a display example of the analysis result.

  The PLC program shown in FIG. 8 includes two tasks including control A (task) and control B (task). Control A (task) includes control A_1 (section), and control A_1 (section) includes SUB1 (subroutine).

  Similarly, a control B_1 (section) is included in the control B (task), and two subroutines consisting of SUB2 (subroutine) and SUB3 (subroutine) are included in the control B_1 (section). include.

  On the other hand, an input / output relay area, an internal auxiliary relay area, a holding relay area, a special auxiliary relay area, a data memory area, and an extended data memory area are provided in the PLC memory.

  Among them, the internal auxiliary relay area is shared by SUB1 (subroutine) existing in the control A (task) and SUB2 (subroutine) included in the control B (task).

  The data memory area in the memory is shared by the control B_1 (section) and SUB3 (subroutine) in the control B (task).

  In other words, the PLC program is composed of two tasks (control A and control B) and two sections (control A_1 and control B_1), and the same memory is shared by a plurality of subroutines as shown in the figure. It will be.

  When such a PLC program is analyzed, an analysis result display as shown in FIG. 9 is obtained. As is apparent from the figure, in this display example, a horizontally long rectangular area is drawn on the screen of the personal computer, and this area is divided into three columns in the left-right direction. Each divided area is assigned a subroutine, a linked subroutine, and the number of link points.

  The subroutine is further divided into three columns in the left-right direction, and the subroutine, task, and section are assigned in order from the left.

  The subroutine row is divided into upper and lower three stages, and SUB1, SUB2, and SUB3 are assigned in order.

  Similarly, the task column stores task types such as control A, control B, and control B in association with each subroutine.

  Furthermore, with regard to the column of sections, sections included in the control A and the control B, respectively, are allocated as a control A_1, a control B_1, and a control B_1.

  Similarly, the link destination subroutine column is also divided into three columns in the left-right direction, and subroutines, tasks, and sections are allocated in order from the left.

  Subroutine columns are further divided into three stages vertically, and the subroutines are assigned in the same manner as before, such as SUB2, SUB1, and none.

  The task column is divided into upper and lower three stages corresponding to each subroutine, and assigned in the order of control B, control A, and control B.

  Furthermore, the section row is also divided into upper and lower three stages, and sections in each task are assigned to each stage in order, such as control B_1, control A_1, and control B_1.

  Finally, the column of link points is divided into five columns in the left-right direction, and each column is assigned a memory area type such as an input / output relay, an internal auxiliary relay, a holding relay, a special auxiliary relay, or a data memory. The number of link points represents the size of the memory that is used repeatedly between subroutines for each type of memory area. For example, it can be seen from the first row of the data string in the display example that 10 internal auxiliary relays are used overlappingly between SUB1 and SUB2. Further, it can be seen from the third row that 20 points of data memory are used redundantly between SUB3 and control B_1 (section) of control B (task).

  According to such a display mode, the correlation between subroutines is displayed, and it becomes possible to accurately grasp the memory usage / sharing status between subroutines.

  Next, an example of a subroutine hierarchy structure is shown in FIG. It is customary to make subroutines where parts can be converted into parts or reused in the program. In addition, a plurality of subroutines in the program have a hierarchical structure depending on their usage status. A description will be given based on an example in which a subroutine (SUB.1 to SUB.10) is called from a plurality of sections (control 1 to control 5) and has a hierarchical structure of the subroutine. In the figure, an arrow (→) indicates that a subroutine is being called.

  As is clear from the figure, the control 1 in the hierarchy 0 is assigned to the SUB. 1 (A) and SUB. 2 (A) is called. Similarly, the control 2 in the hierarchy 0 is transferred to the SUB. 1 (A) and SUB. 2 (A) is called.

  Control 3 in layer 0 is assigned to SUB. Call 3 (A). Control 4 in layer 0 is assigned to SUB. Call 6 (C). Control 5 at layer 0 is assigned to SUB. Call 7 (C). SUB. 1 (A) is a SUB. 4 (B) and SUB. Call 5 (B). SUB. 3 (A) indicates that SUB. 6 (C) and SUB. Call 7 (C). SUB. 4 (B) indicates that SUB. Call 8 (B). SUB. 6 (C) is a SUB. Call 9 (B).

  A diagram showing the classification of the subroutine is shown in FIG. As shown in the figure, the hierarchical structure of the subroutine shown in FIG. 10 is classified as shown in the table of FIG.

  That is, the first classification is a subroutine that is called only from one or a plurality of normal programs, and corresponds to (A) in FIG.

  The second classification is a subroutine called only from one or a plurality of subroutines, and corresponds to (B) in FIG.

  The third category is a subroutine called from both a normal program and a subroutine, and corresponds to (C) in FIG.

  The fourth category is a subroutine that is not called at all, and corresponds to (D) in FIG.

  Finally, FIG. 12 shows a subroutine usage example, and FIG. 13 shows a subroutine analysis result display example. According to the present invention, as shown in FIG. 12, when a plurality of subroutines exist, the display as shown in FIG. 13 is obtained by analyzing them according to the present invention. According to such a display mode, it is possible to accurately grasp the hierarchy (calling status of subroutines).

  As described above, according to the present invention, there is provided a control program development support apparatus for analyzing a control program composed of a plurality of program modules and a plurality of subroutine programs. Analyzing means for analyzing overlapping usage status between programs or between subroutine programs and program modules that call subroutine programs, and analysis display means for displaying the results analyzed by the analyzing means, each subroutine program having another subroutine program It is possible to display the overlapping use status of the memory addresses used with the program module that calls the subroutine program.

  It goes without saying that other embodiments of the subroutine described in the above embodiments can also be applied to function blocks used in ladder diagrams describing PLC user programs.

  According to the present invention, it is possible to provide the user with a display that allows the user to understand at a glance whether the memory used in a certain program module is also used in another subroutine program or a program module that calls a subroutine program. .

It is explanatory drawing of the memory usage condition between subroutines. It is a flowchart which shows the analysis process of the memory usage condition between subroutines. It is explanatory drawing which shows an example of the structure of a user program. It is explanatory drawing of the data preserve | saved in RAM of a personal computer. It is a flowchart of the memory list display process of SUB unit use. It is a flowchart of a drawing process. It is explanatory drawing of the example of a display of an analysis result. It is a figure which shows an example of the memory usage condition in a subroutine. It is a figure which shows the example of a display of an analysis result. It is a figure which shows the example of a subroutine hierarchical structure. It is a figure which shows the classification | category of a subroutine. It is a figure which shows the example of a subroutine usage. It is a display of a subroutine analysis result. It is a figure which shows the example of a cross reference display.

Explanation of symbols

SUB subroutine (A) to (D) Memory area

Claims (6)

A control program development support device for analyzing a control program composed of a plurality of program modules,
It is configured to read other program modules as subroutine programs within a program module.
An analysis means for reading the control program and analyzing the overlapping usage status between the subroutine programs of the memory addresses being used or between the subroutine program and the program module that calls the subroutine program;
An analysis result display means for displaying the result analyzed by the analysis means,
The results displayed by the analysis result display means are displayed for each subroutine program, other subroutine programs that share a memory address with the subroutine program, a program module that calls the subroutine program, and memory used by those subroutine programs and program modules. It is possible to display the overlapping usage status for each type of address memory area .
A control program development support device. The analysis means, when analyzing the overlapping usage status of the used memory address, extracts the size of the memory address used redundantly,
2. The control program development support apparatus according to claim 1, wherein the analysis result display means displays the size of the overlapping use memory address extracted by the analysis means together with the subroutine program name.   2. The control program development support apparatus according to claim 1, wherein a calling relationship between the subroutine programs and between the subroutine program and a program module that calls the subroutine program is configured in a hierarchical structure. Computer
A program module that reads a control program composed of a plurality of program modules, reads other program modules as subroutine programs in the program module, and calls subroutine programs and subroutine programs between subroutine programs at the memory address being used. An analysis means to analyze the overlapping usage status between,
An analysis result display means for displaying the result analyzed by the analysis means,
The results displayed by the analysis result display means are displayed for each subroutine program, other subroutine programs that share a memory address with the subroutine program, a program module that calls the subroutine program, and memory used by those subroutine programs and program modules. A computer program that functions as a control program development support device capable of displaying the overlapping usage status for each type of address memory area . The analysis means, when analyzing the overlapping usage status of the used memory address, extracts the size of the memory address used redundantly,
5. The computer program according to claim 4 , wherein the analysis result display means displays the size of the overlapping use memory address extracted by the analysis means together with the subroutine program name.   5. The computer program according to claim 4, wherein a calling relationship between the subroutine programs and between the subroutine program and a program module that calls the subroutine program is configured in a hierarchical structure.

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