JP2006286027A - Compiler device and compiling method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compiler capable of creating a string of instructions by which a processor capable of parallel processing can be operated with low power consumption. <P>SOLUTION: Three instructions of a cycle of concern are rearranged to create six sequences of instructions (S61). For the slot of each of the instruction sequences, a humming distance between the bit patterns of operational codes between the instruction of concern and the instruction of the previous cycle is calculated (S64). This process is carried out for all the instructions of the three slots (S63-S65) and the sum of the humming distances is calculated (S66). The above processes are carried out for all of the six sequences of instructions (S62-S67). The sequence of instructions with which the sum of the six humming distances assumes a minimum value is selected and the instructions are rearranged so that the sequence corresponding to the minimum value is provided (S68). The above processes are repeated from the second cycle to the final cycle (S60-S69). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a compiler that converts a source program written in a high-level language such as a C / C ++ language into a machine language program, and more particularly to a compiler that can output a machine language program with low power consumption during program execution.

  In portable information processing apparatuses such as mobile phones and information portable terminals that have become popular in recent years, reduction of power consumption is required. Therefore, there is a need for a compiler that can generate machine language instructions that can operate with low power consumption while effectively extracting the high functions of a processor used in such an information processing apparatus.

  As a conventional compiler, there is an instruction sequence optimizing device that reduces the power consumption of a processor by changing the execution order of instructions (see, for example, Patent Document 1).

In this instruction sequence optimizing apparatus, the instruction arrangement is changed so as to reduce the Hamming distance between the bit patterns of the instructions without affecting the dependency relation of the instructions. Thereby, it is possible to optimize the instruction sequence that can reduce the power consumption of the processor.
JP-A-8-101777

  However, the conventional instruction sequence optimization device does not assume a processor capable of parallel processing. For this reason, there is a problem that even if the conventional optimization processing is directly applied to a processor capable of parallel processing, the optimization of the optimum instruction sequence cannot be obtained.

  Therefore, the present invention has been made in view of such a situation, and an object thereof is to provide a compiler capable of generating an instruction sequence that can operate a processor capable of parallel processing with low power consumption.

  In order to achieve the above object, a compiler apparatus according to the present invention includes a plurality of execution units that can process a source program in parallel, and a plurality of instruction issuance units that respectively issue instructions executed by the plurality of execution units. A compiler device for translating the machine program into a machine language program for a processor, the parser means for parsing the source program, the intermediate code conversion means for converting the analyzed source program into intermediate code, and the intermediate code Priority is given to an instruction having a reduced Hamming distance from an instruction placed at a position corresponding to the same instruction issuing unit in the immediately preceding instruction cycle without breaking the dependency relation of the corresponding instruction. Optimization means for optimizing the intermediate code by placing the instruction at each corresponding position, and optimization Characterized in that it comprises a code generating means for converting the machine instructions the intermediate code.

  As a result, it is possible to suppress changes in the bit pattern of instructions executed by each instruction issuing unit, so that bit changes in values held in the instruction register of the processor are small, and the processor can be operated with low power consumption. An instruction sequence is generated.

  In addition, a compiler apparatus according to the present invention provides a machine for a processor having a plurality of execution units that can process a source program in parallel and a plurality of instruction issue units that respectively issue instructions executed by the plurality of execution units. A compiler apparatus for translating into a word program, a parser means for parsing the source program, an intermediate code conversion means for converting the analyzed source program into an intermediate code, and an instruction dependency corresponding to the intermediate code The instruction that accesses the same register as the register of the instruction arranged at the position corresponding to the same instruction issuing unit in the immediately preceding instruction cycle is prioritized without damaging the instruction cycle. An optimization means for allocating the instruction at a location and optimizing the intermediate code; Characterized in that it comprises a code generating means for converting the intermediate code into machine language instructions.

  As a result, access to the same register continues, the change in the control signal for selecting the register is reduced, and an instruction sequence that can operate the processor with low power consumption is generated.

  Furthermore, a compiler apparatus according to the present invention provides a machine for a processor having a plurality of execution units that can process a source program in parallel and a plurality of instruction issue units that issue instructions executed by the plurality of execution units. A compiler apparatus for translating into a word program, wherein each of the plurality of instruction issuing units is preliminarily specified with an instruction that is preferentially issued, and is analyzed by parser means for parsing the source program The intermediate code conversion means for converting the source program into an intermediate code and the instruction issued preferentially in each of the plurality of instruction issue units without breaking the dependency relationship between the instructions corresponding to the intermediate code, The instruction is arranged at a position corresponding to each of the plurality of instruction issuing units, and the intermediate code is optimized. And means, characterized in that it comprises a code generating means for converting the machine instructions the intermediate code optimized.

  Thus, if an instruction that uses the same component of the processor is assigned as an instruction that is preferentially issued by the same instruction issuing unit, instructions that use the same component are continuously executed in the same instruction issuing unit. Therefore, an instruction string that can operate the processor with low power consumption is generated.

  Furthermore, a compiler apparatus according to the present invention is for a processor having a plurality of execution units that can process a source program in parallel and a plurality of instruction issue units that issue instructions executed by the plurality of execution units. A compiler device that translates into a machine language program, which corresponds to parser means for parsing the source program, intermediate code conversion means for converting the analyzed source program into intermediate code, and the plurality of instruction issuing units, respectively. And a section detecting means for detecting a section in which unplaced positions of the same number of instructions continue for more than a predetermined number of instruction cycles, and the unplaced position of the instructions immediately before the section. First instruction insertion means for inserting an instruction for stopping the operation of the corresponding instruction issuing unit Characterized by comprising a code generating means for converting the intermediate code to which the instruction is inserted into machine instructions.

  As a result, when instructions are not continuously arranged at the position corresponding to the instruction issuing unit, the supply of power to the instruction issuing unit can be stopped during that time, so that the processor operates with low power consumption. An instruction sequence that can be generated is generated.

  Furthermore, a compiler apparatus according to the present invention is for a processor having a plurality of execution units that can process a source program in parallel and a plurality of instruction issue units that issue instructions executed by the plurality of execution units. A compiler apparatus for translating into a machine language program, wherein the source program includes number specifying information that can specify the number of instruction issuing units used by the processor, and is analyzed by parser means for parsing the source program. In addition, the intermediate code converting means for converting the source program into the intermediate code and the instruction issuing unit of the number specified by the number specifying information are operated without breaking the dependency relationship between the instructions corresponding to the intermediate code. An optimization means for allocating instructions and optimizing the intermediate code; Characterized in that it comprises a code generating means for converting the intermediate code into machine language instructions.

  As a result, regarding the instruction at the location specified by the number specification information, an instruction issuing unit to which no instruction is supplied can be generated and power supply to the instruction issuing unit can be stopped. An instruction sequence that can be operated with power consumption is generated.

  Furthermore, a compiler apparatus according to the present invention is for a processor having a plurality of execution units that can process a source program in parallel and a plurality of instruction issue units that issue instructions executed by the plurality of execution units. A compiler device that translates into a machine language program, receiving means for receiving the number of instruction issuing units used by the processor, parser means for parsing the source program, and converting the analyzed source program into intermediate code The intermediate code converting means and the instructions corresponding to the intermediate code are arranged so as to operate only the number of instruction issuing units received by the receiving means without breaking the dependency relationship between the instructions. Optimization means for converting the intermediate code into machine language instructions Characterized in that it comprises a code generating means.

  As a result, only the number of instruction issuing units received by the receiving means can be operated and the supply of power to the other instruction issuing units can be stopped, so that there are instruction examples that can operate the processor with low power consumption. Generated.

  The present invention can be realized not only as such a compiler apparatus but also as a compiling method using steps included in such a program as a step, or a characteristic compiler program or It can also be realized as a computer-readable recording medium. Needless to say, such a program or data file can be widely distributed via a recording medium such as a CD-ROM (Compact Disk-Read Only Memory) or a transmission medium such as the Internet.

  As can be seen from the above description, according to the compiler apparatus of the present invention, an instruction sequence is generated in which the bit change of the value held in the instruction register of the processor is small and the processor can be operated with low power consumption.

  In addition, an access to the same register is continued, a change in a control signal for selecting the register is reduced, and an instruction sequence that can operate the processor with low power consumption is generated.

  Furthermore, since instructions that use the same component in the same slot can be continuously executed, an instruction sequence that can operate the processor with low power consumption is generated.

  Furthermore, since the power supply to the empty slot can be stopped, an instruction sequence that can operate the processor with low power consumption is generated.

  As described above, the compiler according to the present invention makes it possible to operate a processor capable of parallel processing with low power consumption. In particular, it is possible to generate a processor-oriented instruction sequence (machine language program) used in a device that requires operation with low power consumption, such as a portable information processing device such as a mobile phone or an information portable terminal, Its practical value is extremely high.

Hereinafter, embodiments of a compiler according to the present invention will be described in detail with reference to the drawings.
The compiler in this embodiment is a cross compiler that translates a source program written in a high-level language such as C / C ++ into a machine language program that can be executed by a specific processor (target), and reduces the power consumption of the processor. It has the feature that it can be.

[Processor]
First, an example of a processor that is a target of a compiler according to the present embodiment will be described with reference to FIGS.

  The processor that is the target of the compiler in this embodiment, for example, has higher parallelism of instructions that can be executed than a normal microcomputer, and adopts a pipeline system so that a plurality of instructions can be processed in parallel. .

FIG. 1 is a diagram showing a structure of an instruction that is decoded and executed by the processor according to the present embodiment.
1A to 1D, each instruction of the processor has a fixed length of 32 bits. The 0th bit of each instruction indicates parallel execution boundary information. When the parallel execution boundary information is “1”, there is a parallel execution boundary between the instruction and the succeeding instruction, and when the parallel execution boundary information is “0”, there is no parallel execution boundary. Become. A method of using the parallel execution boundary information will be described later.

  The operation is determined in the 31-bit portion obtained by removing the parallel execution boundary information from the instruction length of each instruction. Specifically, in the fields “Op1”, “Op2”, “Op3”, and “Op4”, an operation code indicating the type of operation is designated. In the register fields “Rs”, “Rs1”, and “Rs2”, the register number of the register that becomes the source operand is designated. In the register field “Rd”, the register number of the register serving as the destination operand is designated. In the field “Imm”, a constant operand for calculation is designated. In the field “Disp”, a displacement is specified.

  The first 2 bits (30th and 31st bits) of the opcode are used to specify the type of operation (operation group). Details thereof will be described later.

  The opcodes Op2 to Op4 are 16-bit data, while the opcode Op1 is 21-bit data. Therefore, for the sake of convenience, the first half (16th to 31st bits) of the opcode Op1 is called an opcode Op1-1, and the second half (11th to 15th bits) is called an opcode Op1-2.

  FIG. 2 is a block diagram showing a schematic configuration of the processor according to the present embodiment. The processor 30 includes an instruction memory 40 that stores a group of instructions (hereinafter referred to as “packets”) described in accordance with a VLIW (Very Long Instruction Word) system, an instruction supply issue unit 50, a decoding unit 60, and an execution unit 70. And a data memory 100. Details of each part will be described later.

  FIG. 3 is a diagram illustrating an example of a packet. One packet is a unit of instruction fetch and is defined to be composed of four instructions. As described above, one instruction is 32 bits long. Therefore, one packet is 128 (= 32 × 4) bits long.

  Referring again to FIG. 2, the instruction supply / issuance unit 50 is connected to the instruction memory 40, the decoding unit 60 and the execution unit 70, and is based on the value of the PC (program counter) supplied from the execution unit 70. A packet is received from 40 and up to three instructions are supplied in parallel to the decoding unit 60.

  The decoding unit 60 is connected to the instruction supply issuing unit 50 and the execution unit 70, decodes the instruction supplied from the instruction supply issuing unit 50, and supplies the decoded instruction to the execution unit 70.

  The execution unit 70 is connected to the instruction supply / issuance unit 50, the decryption unit 60, and the data memory 100. Based on the decryption result supplied from the decryption unit 60, the execution unit 70 accesses the data stored in the data memory 100 as necessary. Performs processing based on the instruction. Each time the process is executed, the execution unit 70 increments the PC value by one.

  The instruction supply / issuance unit 50 is connected to the instruction memory 40 and a later-described PC unit in the execution unit 70, accesses the address of the instruction memory 40 indicated by the program counter held in the PC unit, and receives packets from the instruction memory 40. An instruction fetch unit 52 for receiving, an instruction buffer 54 connected to the instruction fetch unit 52 and temporarily holding a packet, and an instruction register unit 56 connected to the instruction buffer 54 and holding up to three instructions included in the packet Including.

  The instruction fetch unit 52 and the instruction memory 40 are connected by an IA (Instruction Address) bus 42 and an ID (Instruction Data) bus 44. The IA bus 42 is 32 bits wide and the ID bus 44 is 128 bits wide. Address supply from the instruction fetch unit 52 to the instruction memory 40 is performed via the IA bus 42. Packets are supplied from the instruction memory 40 to the instruction fetch unit 52 through the ID bus 44.

  The instruction register unit 56 includes instruction registers 56a to 56c each connected to the instruction buffer 54 and holding one instruction.

  The decoding unit 60 is connected to an instruction issuance control unit 62 that controls the issuance of instructions held in the three instruction registers 56 a to 56 c in the instruction register unit 56, an instruction issuance control unit 62, and the instruction register unit 56. And a decoding unit 64 that decodes an instruction supplied from the instruction register unit 56 based on the control of the instruction issue control unit 62.

  The decode unit 64 includes instruction decoders 64a to 64c connected to the instruction registers 56a to 56c, respectively, which basically decode one instruction per cycle and output a control signal.

  The execution unit 70 is connected to the decoding unit 64, and controls an after-mentioned component in the execution unit 70 based on control signals output from the three instruction decoders 64 a to 64 c in the decoding unit 64. 72, a PC section 74 that holds the address of the packet to be executed next, a register file 76 composed of 32 32-bit registers R0 to R31, and a SIMD (Single Instruction Multiple Data) type operation, respectively. Similar to the arithmetic logic / comparison arithmetic units 78a to 78c and the arithmetic logic / comparison arithmetic units 78a to 78c, SIMD type instructions can be executed, and can be accumulated up to 65 bits so as not to degrade the bit precision. Multiply / multiply-accumulate units 80a and 80b for calculation.

  The execution unit 70 is further connected to a barrel shifters 82a to 82b for performing an arithmetic shift (shift of two's complement system) or a logical shift (unsigned shift), a divider 84, and the data memory 100, respectively. An operand access unit 88 for transferring data to and from the data memory 100, a 32-bit wide data bus 90 (L1 bus, R1 bus, L2 bus, R2 bus, L3 bus, R3 bus), and a 32-bit wide data bus Data bus 92 (D1 bus, D2 bus, D3 bus).

  The register file 76 includes 32 32-bit registers R0 to R31. Selection of a register in the register file 76 that outputs data to the L1 bus, R1 bus, L2 bus, R2 bus, L3 bus, and R3 bus is performed by the control signals CL1, CR1, Performed by CL2, CR2, CL3 and CR3, respectively. In addition, selection of a register to which data flowing through the D1 bus, D2 bus, and D3 bus is written is performed by control signals CD1, CD2, and CD3 supplied from the execution control unit 72 to the register file 76, respectively.

  Two input ports of the arithmetic logic / comparison unit 78a are connected to the L1 bus and the R1 bus, respectively, and their output ports are connected to the D1 bus. Two input ports of the arithmetic logic / comparison operation unit 78b are connected to the L2 bus and the R2 bus, respectively, and their output ports are connected to the D2 bus. Two input ports of the arithmetic logic / comparison unit 78c are connected to the L3 bus and the R3 bus, respectively, and their output ports are connected to the D3 bus.

  The four input ports of the multiplication / product-sum operation unit 80a are connected to the L1 bus, the R1 bus, the L2 bus, and the R2 bus, respectively, and the two output ports are connected to the D1 bus and the D2 bus, respectively. The four input ports of the multiplication / product-sum operation unit 80b are connected to the L2 bus, the R2 bus, the L3 bus, and the R3 bus, respectively, and the two output ports are connected to the D2 bus and the D3 bus, respectively.

  Two input ports of the barrel shifter 82a are connected to the L1 bus and the R1 bus, respectively, and their output ports are connected to the D1 bus. Two input ports of the barrel shifter 82b are connected to the L2 bus and the R2 bus, respectively, and their output ports are connected to the D2 bus. Two input ports of the barrel shifter 82c are connected to the L3 bus and the R3 bus, respectively, and their output ports are connected to the D3 bus.

  Two input ports of the divider 84 are connected to the L1 bus and the R1 bus, respectively, and their output ports are connected to the D1 bus.

  The operand access unit 88 and the data memory 100 are connected by an OA (Operand Address) bus 96 and an OD (OperandData) bus 94. The OA bus 96 and the OD bus 94 are each 32 bits wide. The operand access unit 88 designates the address of the data memory 100 via the OA bus 96 and reads / writes data at the address via the OD bus 94.

  Operand access unit 88 is connected to the D1 bus, D2 bus, D3 bus, L1 bus, and R1 bus, and exchanges data with any of the buses.

  Although the processor 30 can execute three instructions in parallel, as will be described later, in the pipeline operation, a set of pipeline processing including an instruction allocation stage, a decode stage, an execution stage, and a write stage that can be executed in parallel is performed. A set of circuits that can be executed is defined herein as a “slot”. Therefore, the processor 30 has three slots of the first to third slots. Assume that the instruction register 56a and instruction decoder 64a belong to the first slot, the instruction register 56b and instruction decoder 64b belongs to the second slot, and the instruction register 56c and instruction decoder 64c belongs to the third slot.

  Each slot is assigned an instruction called default logic, and instruction scheduling is performed so that the same instruction is executed as much as possible in the same slot. For example, an instruction relating to memory access (default logic) is assigned to the first slot, a default logic relating to multiplication is assigned to the second slot, and other default logic is assigned to the third slot. Note that the default logic has a one-to-one correspondence with the operation group described with reference to FIG. That is, instructions whose first 2 bits are “01”, “10”, and “11” are the default logic of the first slot, the second slot, and the third slot, respectively.

  The default logic of the first slot includes ld (load instruction), st (store instruction), and the like. The default logic of the second slot includes mul1, mul2 (multiplication instruction) and the like. The default logic of the third slot includes add1, add2 (addition instruction), sub1, sub2 (subtraction instruction), mov1, mov2 (transfer instruction between registers), and the like.

  FIG. 4 is a diagram for explaining parallel execution boundary information included in a packet. Assume that packets are stored in the instruction memory 40 in the order of packets 112 and 114. Among these, the parallel execution boundary information of the instruction 2 of the packet 112 and the instruction 5 of the packet 114 is “1”, and the parallel execution boundary information of the other instructions is “0”.

  The instruction fetch unit 52 reads the packets in the order of the packet 112 and the packet 114 based on the value of the program counter of the PC unit 74 and sequentially supplies the packets to the instruction buffer 54. In the execution unit 70, instructions up to the parallel execution boundary information “1” are executed in parallel.

  FIG. 5 is a diagram illustrating an example of an execution unit of instructions executed in parallel created based on parallel execution boundary information of packets. Referring to FIGS. 4 and 5, when packets 112 and 114 are separated by an instruction portion whose parallel execution boundary information is “1”, execution units 122 to 126 are generated. Therefore, instructions are supplied from the instruction buffer 54 to the instruction register unit 56 in the order of the execution units 122 to 126. The command issue control unit 62 performs control related to the supply of commands.

  The instruction decoders 64 a to 64 c decode the operation codes of the instructions held in the instruction registers 56 a to 56 c, respectively, and output control signals to the execution control unit 72. The execution control unit 72 performs various controls of the components of the execution unit 70 based on the analysis results of the instruction decoders 64a to 64c.

  For example, consider the instruction “add1 R3, R0”. The meaning of this instruction is to add the value of the register R3 and the value of the register R0 and write the result to the register R0. In this case, the execution control unit 72 performs the following control as an example. . The execution control unit 72 supplies the register file 76 with a control signal CL1 for outputting the value held in the register R3 to the L1 bus. In addition, the execution control unit 72 supplies the register file 76 with a control signal CR1 for outputting the value held in the register R0 to the R1 bus.

  Further, the execution control unit 72 supplies a control signal CD1 for writing the execution result obtained through the D1 bus to the register R0 to the register file 76. Furthermore, the execution control unit 72 controls the arithmetic logic / comparison operation unit 78a, receives the values of the registers R3 and R0 via the L1 bus and the L2 bus, adds them, and then adds the addition result to the register R0 via the D1 bus. Write to.

  FIG. 6 is a block diagram showing a schematic configuration of the arithmetic logic / comparison arithmetic units 78a to 78c. Referring to FIGS. 6 and 2, each of arithmetic logic / comparison operation units 78 a to 78 c includes an ALU (Arithmetic and Logical Unit) unit 132 connected to a register file 76 via a data bus 90, and an ALU unit 132. And connected to the register file 76 via the data bus 92 and connected to the saturation processing unit 134 for performing saturation, maximum / minimum value detection and absolute value generation processing, and the ALU unit 132 for detecting overflow and generating a condition flag. And a flag section 136 to be executed.

  FIG. 7 is a block diagram illustrating a schematic configuration of the barrel shifters 82a to 82c. 7 and 2, each of barrel shifters 82a to 82c is connected to accumulator unit 142 having accumulators M0 and M1 for holding 32-bit data, and to register file 76 via accumulator M0 and data bus 90. Connected to the register file 76 via the accumulator M1 and the data bus 90, and connected to the output of the selector 146 and the selector 148 that receives the values of the accumulator M1 and the register. Upper barrel shifter 150, lower barrel shifter 152 connected to the output of selector 148, and saturation processing unit 154 connected to the outputs of upper barrel shifter 150 and lower barrel shifter 152.

  The output of the saturation processing unit 154 is connected to the register file 76 via the accumulator unit 142 and the data bus 92.

  Each of the barrel shifters 82a to 82c performs an arithmetic shift of data (shift of two's complement system) or logical shift (unsigned shift) by operating a component. Normally, 32-bit or 64-bit data is input / output. For the data to be shifted stored in the register in the register file 76 or the accumulator in the accumulator unit 142, the shift amount is designated by another register or an immediate value. The data is arithmetically or logically shifted from the left 63 bits to the right 63 bits and output with an input bit length.

  Further, each of the barrel shifters 82a to 82c can shift data of 8, 16, 32, and 64 bits with respect to the SIMD type instruction. For example, a shift of 8-bit data can be processed in 4 parallel.

  Arithmetic shift is a shift of 2's complement system, and alignment of decimal point at the time of addition or subtraction, multiplication by power of 2 (2, 2 squared, 2 (-1) power, 2 (-2) Etc.) etc.

  FIG. 8 is a block diagram showing a schematic configuration of the divider 84. Referring to FIGS. 8 and 2, divider 84 is connected to register file 76 via accumulator unit 162 having accumulators M0 and M1 holding 32-bit data, and accumulator unit 162 and data buses 90 and 92. Divided division unit 164.

  Divider 84 sets the dividend to 64 bits and the divisor to 32 bits, and outputs the quotient and remainder each 32 bits. 34 cycles are required to find the quotient and the remainder. Both signed and unsigned data can be handled. However, the setting of the presence / absence of a sign is common to the dividend and the divisor. In addition, it has a function of outputting an overflow flag and a division by zero flag.

  FIG. 9 is a block diagram showing a schematic configuration of the multiplication / product-sum operation units 80a and 80b. Referring to FIGS. 9 and 2, each of multiplication / product-sum operation units 80a and 80b includes an accumulator unit 172 having accumulators M0 and M1 for holding 64-bit data, and a register file via data bus 90, respectively. 2-input 32-bit multipliers (MUL) 174a and 174b connected to 76.

  Each of multiplication / product-sum operation units 80a and 80b is further connected to an output and accumulator unit 172 of a multiplier 174b, and a 64-bit adder (Adder) 176a connected to the output and accumulator unit 172 of multiplier 174a. 64-bit adder 176b, 64-bit adder 176c connected to the outputs of 64-bit adder 176a and 64-bit adder 176b, selector 178 connected to the outputs of 64-bit adders 176b and 176c, And an output of the selector 178, an accumulator unit 172, and a saturation processing unit (Saturation) 180 connected to the register file 76 via the data bus 92.

Each of the multiplication / product-sum operation units 80a and 80b performs the following multiplication and product-sum operation.
32 × 32 bit signed multiplication, product sum, product difference operation 32 × 32 bit unsigned multiplication 16 × 16 bit 2-parallel signed multiplication, product sum, product difference operation 32 × 16 bit 2 parallel signed multiplication, product sum, product difference operation

  These operations are performed on data in integer and fixed-point format. Also, rounding and saturation are performed for these operations.

  FIG. 10 is a timing chart showing each pipeline operation when an instruction is executed by the processor 30. 2 and 10, in the instruction fetch stage, the instruction fetch unit 52 accesses the instruction memory 40 at the address specified by the program counter held in the PC unit 74 and transfers the packet to the instruction buffer 54. To do. In the instruction assignment stage, instructions held in the instruction buffer 54 are assigned to the instruction registers 56a to 56c. In the decode stage, the instructions assigned to the instruction registers 56a to 56c are decoded by the instruction decoders 64a to 64c, respectively, according to the control from the instruction issue control unit 62. In the execution stage, the execution control unit 72 operates the components of the execution unit 70 based on the decoding results from the instruction decoders 64a to 64c, and executes various calculations. In the write stage, the calculation result is stored in the data memory 100 or the register file 76. With these processes, up to three parallel pipeline processes can be executed.

  FIG. 11 is a diagram illustrating instructions executed by the processor 30, processing contents, and bit patterns thereof. The instruction “ld Rs, Rd” is the data memory 100 of the address of the value of the register (hereinafter referred to as “register Rs”; hereinafter the same) designated in the Rs field of the operation shown in FIG. Shows a process of loading the data stored in the register Rd. The bit pattern is as shown in FIG.

  In the bit pattern of FIG. 11, the first 2 bits (30th and 31st bits) are used to specify an operation group, and the 0th bit is used to specify parallel execution boundary information. The above-described operation in which the first two bits are “01” relates to memory access. An operation whose first 2 bits are “10” relates to multiplication. The operation having the first two bits of “11” relates to other operations.

  The instruction “st Rs, Rd” indicates a process of storing the value of the register Rs at the address specified by the register Rd of the data memory 100.

  The instruction “mul1 Rs, Rd” indicates a process of writing the product of the value of the register Rs and the value of the register Rd to the register Rd. The instruction “mul2 Rs1, Rs2, Rd” indicates a process of writing the product of the value of the register Rs1 and the value of the register Rs2 to the register Rd.

  The instruction “add1 Rs, Rd” indicates a process of writing the sum of the value of the register Rs and the value of the register Rd to the register Rd. The instruction “add2 Rs1, Rs2, Rd” indicates a process of writing the sum of the value of the register Rs1 and the value of the register Rs2 to the register Rd.

  The instruction “sub1 Rs, Rd” indicates a process of writing the difference between the value of the register Rs and the value of the register Rd into the register Rd. The instruction “sub2 Rs1, Rs2, Rd” indicates a process of writing the difference between the value of the register Rs1 and the value of the register Rs2 to the register Rd.

  The instruction “mov1 Rs, Rd” indicates a process of writing the value of the register Rs to the register Rd. The instruction “mov2 Imm, Rd” indicates a process of writing the value of the Imm field into the register Rd.

  The instruction “div Rs, Rd” indicates a process of writing a quotient obtained by dividing the value of the register Rs by the value of the register Rd into the register Rd. The instruction “mod Rs, Rd” indicates a process of writing a remainder obtained by dividing the value of the register Rs by the value of the register Rd into the register Rd.

[compiler]
Next, an example of a compiler according to the present embodiment targeting the above-described processor 30 will be described with reference to FIGS.

[Compiler overall configuration]
FIG. 12 is a functional block diagram showing a configuration of the compiler 200 according to the present embodiment. The compiler 200 is a cross compiler that converts a source program 202 described in a high-level language such as a C / C ++ language into a machine language program 204 using the processor 30 as a target processor, and is executed on a computer such as a personal computer. The program is implemented by a program to be executed, and roughly includes a parser unit 210, an intermediate code conversion unit 220, an optimization unit 230, and a code generation unit 240.

  The parser unit 210 is a preprocessing unit that extracts reserved words (keywords) and the like from a source program 202 (including an included header file) to be compiled, and performs lexical analysis. It has an analysis function.

  The intermediate code conversion unit 220 is a processing unit that is connected to the parser unit 210 and converts each statement of the source program 202 passed from the parser unit 210 into an intermediate code based on a certain rule. Here, the intermediate code is typically a code expressed in the form of a function call (for example, a code indicating “+ (int a, int b)”; “adding an integer b to an integer a” It is shown.)

  The optimization unit 230 is connected to the intermediate code conversion unit 220. With regard to the intermediate code output from the intermediate code conversion unit 220, the optimization unit 230 focuses on the operation code of the instruction, and the power consumption of the processor 30 is reduced without breaking the dependency between instructions. The instruction scheduling unit 232 that arranges instructions so as to be smaller, and the instruction scheduling unit 232 are connected to the instruction scheduling unit 232. Regarding the schedule result in the instruction scheduling unit 232, the power consumption of the processor 30 is reduced by focusing on the register field of the instruction. A register allocation unit 234 for allocating registers.

  The optimization unit 230 is further connected to the register allocation unit 234, and pays attention to the bit pattern of the instruction for the schedule result to which the register is allocated so that the power consumption of the processor 30 is reduced without breaking the instruction dependency. In addition, an instruction rescheduling unit 236 that performs instruction relocation, and a slot that is connected to the instruction rescheduling unit 236 and that is stopped for a predetermined cycle or more from the schedule result of the instruction rescheduling unit 236, A slot stop / return command generation unit 238 for inserting a command for stopping and returning the slot.

  The optimization unit 230 is further connected to the slot stop / return instruction generation unit 238, and sets a parallel execution boundary information setting unit 239 for setting parallel execution boundary information of the arranged instruction based on the schedule result, and an instruction scheduling unit 232, a register allocation unit 234, and an instruction rescheduling unit 236, and an in-cycle arrangement adjustment processing unit 237 that rearranges the schedule results so that the power consumption decreases for each cycle.

  Note that processing in the optimization unit 230 described later is performed in units of basic blocks. A basic block is a unit of a program that does not branch from the middle to the outside, such as a sequence of expressions or assignment statements, and does not branch from the middle to the middle.

  The code generation unit 240 is connected to the parallel execution boundary information setting unit 239 of the optimization unit 230, and refers to a conversion table or the like held internally for the intermediate code output from the parallel execution boundary information setting unit 239. Thus, the machine language program 204 is generated by replacing all intermediate codes with machine language instructions.

  Next, a characteristic operation of the compiler 200 configured as described above will be described with a specific example.

[Instruction scheduling section]
FIG. 13 is a flowchart showing the operation of the instruction scheduling unit 232. In the process of the instruction scheduling unit 232, the register scheduling is not performed, and the process is performed assuming that the number of registers is infinite. Therefore, in the following description, it is assumed that a register scheduled by the instruction scheduling unit 232 is prefixed with Vr such as Vr (Virtual Register) 0 and Vr1.

  The instruction scheduling unit 232 creates an instruction dependency graph based on the intermediate code generated by the intermediate code conversion unit 220 (step S2 (hereinafter, “step” is omitted)). The dependency graph is a graph showing a dependency relationship between instructions, and is a directed graph in which a node is allocated for each instruction and instructions having a dependency relationship are connected by an edge. The dependency graph is a well-known technique. Therefore, detailed description thereof will not be repeated here. For example, here, it is assumed that a dependency graph composed of three directed graphs as shown in FIG.

  The instruction scheduling unit 232 selects an executable instruction (node) from the dependency graph, and schedules the instruction in the first cycle so as to match the default logic of each slot (S4). For example, in the dependency graph of FIG. 14A, the nodes of the instructions of the nodes N1, N6, N7, N11, and N12 can be scheduled. Of these, the node N1 is an instruction related to memory access, and the node N11 is a multiplication instruction. And node N6 is a shift instruction. In this case, nodes N1, N11, and N6 are arranged in the first to third slots of the first cycle, respectively. A flag is attached to the arranged node, and the dependency graph is updated as shown in FIG. After instruction scheduling (S4) in the first cycle, an instruction scheduling result as shown in FIG. 15 is obtained.

  The instruction scheduling unit 232 generates a placement candidate instruction set with reference to the dependency graph (S8). That is, in the example of FIG. 14B, the instructions indicated by the nodes N2, N7, N8, and N12 are the arrangement candidate instruction set.

  The instruction scheduling unit 232 extracts one optimum instruction from the arrangement candidate instruction set according to an algorithm described later (S12).

  The instruction scheduling unit 232 determines whether or not the extracted optimum instruction can actually be arranged (S14). Judgment as to whether or not placement is possible is made based on whether or not the number of instructions in the target cycle assuming that the optimum instruction has been placed does not exceed the number of instructions placed in the previous cycle. As a result, a cycle in which the same number of instructions are arranged continues.

  If it is determined that placement is possible (YES in S14), the optimum instruction is provisionally placed and deleted from the placement candidate instruction set (S16). Thereafter, the instruction scheduling unit 232 determines whether or not further instructions can be arranged in the same manner as the above-described determination process (S14) (S18). If it is determined that placement is possible (YES in S18), the dependency graph is referred to, and if a new placement candidate instruction is generated, it is added to the placement candidate instruction set (S20). The instruction temporary arrangement process for the above target cycle is repeated until there are no arrangement candidate instructions (S10 to S22).

  If it is determined that the instruction cannot be arranged in the target cycle after the optimum instruction temporary arrangement process (S16) (NO in S18), the instruction temporary arrangement process (S10 to S22) is performed. Exit the loop.

  After the instruction temporary placement process (S10 to S22), the instruction scheduling unit 232 determines the temporarily placed instruction and ends the scheduling for the placement candidate instruction set (S24). Thereafter, for the arranged instruction, the arranged flag is attached to the corresponding node of the dependency graph, and the dependency graph is updated (S26).

  The instruction scheduling unit 232 determines whether or not the same number of instructions are continuously arranged for a predetermined cycle or more (S27). When it is determined that the same number of instructions are continuously arranged over a certain cycle (for example, when 2 instructions are continuously arranged for 20 cycles or more, or 1 instruction is continuously arranged for 10 cycles or more) (YES in S27), the instruction scheduling unit 232 sets the maximum number of instructions that can be arranged in one cycle (hereinafter referred to as “the maximum number of instructions that can be arranged”) to 3 (S28), and in the subsequent cycles, as much as possible. Three instructions are arranged in one cycle. The above processing is repeated until there are no unplaced instructions (S6 to S29).

  FIG. 16 is a flowchart showing the operation of the optimum instruction fetch process (S12) of FIG.

  The instruction scheduling unit 232 obtains the Hamming distance between the bit patterns of the opcode between each of the placement candidate instructions and each of the instructions placed in the cycle immediately before the target cycle (S42).

  For example, referring to FIG. 14B, nodes N2, N7, N8, and N12 can be arranged at the beginning of the scheduling of the second cycle. In the first cycle, nodes N1, N6 and N11 are arranged. For this reason, the Hamming distance between the bit patterns of the opcodes is obtained for all combinations between the nodes N1, N6 and N11 and the nodes N2, N7, N8 and N12.

  FIG. 17 is a diagram for explaining a method of calculating the Hamming distance between the bit patterns of the operation code. It is assumed that the instruction “ld Vr11, Vr12” has already been arranged in the Nth cycle, and the arrangement candidate instructions in the N + 1th cycle are “st Vr13, Vr14” and “add1 Vr13, Vr14”. Referring to FIG. 17A, the operation codes “ld” and “st” have different bit patterns of the 12, 16, 17, 24, and 25th bits. For this reason, the Hamming distance is 5. Similarly, referring to FIG. 17B, the operation codes “ld” and “add1” have different bit patterns of the 16, 17, 18, 20, 25, 26, 28, and 31 bits. For this reason, the Hamming distance is 8.

  FIG. 18 is a diagram for explaining a method of calculating a Hamming distance between operation codes having different bit lengths. It is assumed that the instruction “ld Vr11, Vr12” has already been arranged in the Nth cycle, and the arrangement candidate instructions in the N + 1th cycle are “mul2 Vr13, Vr14, Vr15” and “st Vr13, Vr14”. Referring to FIG. 18A, the hamming distance is calculated for the bit pattern of the overlapped portion of the operation code between the operation codes having different bit lengths such as the operation codes “ld” and “mul2”. Therefore, the Hamming distance is calculated based on the values from the 16th bit to the 31st bit of the operation code. The opcodes “ld” and “mul2” are different in the 16, 18, 19, 22, 23, 25, 26, 27, 28, 30 and 31st bits. For this reason, the Hamming distance is 11. Referring to FIG. 18 (b), the other arrangement candidate instructions “st Vr13, Vr14” are also from the 16th bit to the 31st bit of the opcode in order to ensure consistency with the example of FIG. 18 (a). The Hamming distance is calculated based on the value of. The opcodes “ld” and “st” differ in the 16th, 17th, 24th and 25th bits. For this reason, the Hamming distance is 4.

  Referring to FIG. 16 again, the instruction scheduling unit 232 identifies an arrangement candidate instruction having the minimum Hamming distance (S43). In the example of FIGS. 17 and 18, both the instructions “st Vr13, Vr14” are specified as the arrangement candidate instructions.

  The instruction scheduling unit 232 determines whether there are two or more placement candidate instructions having the minimum Hamming distance (S44). If there is one placement candidate instruction having the minimum Hamming distance (NO in S44), that instruction is determined as the optimum instruction (S56).

  If there are two or more placement candidate instructions having the minimum Hamming distance (YES in S44), whether or not any of these placement candidate instructions matches the default logic of an empty slot in which no instruction is placed. Is determined (S46).

  If there is no placement candidate instruction that matches the default logic (NO in S46), any one of two or more placement candidate instructions having the minimum Hamming distance is arbitrarily selected and set as the optimum instruction (S54).

  If there is a placement candidate instruction that matches the default logic and the number is one (YES in S46, NO in S48), the placement candidate instruction that matches the default logic is determined as the optimum instruction (S52).

  If there is an arrangement candidate instruction that matches the default logic and the number is two or more (YES in S46, YES in S48), any one of two or more arrangementable instructions that match the default logic is arbitrarily selected. The optimum instruction is selected (S50).

[In-cycle placement adjustment processing section]
FIG. 19 is a flowchart showing the operation of the in-cycle arrangement adjustment processing unit 237. The in-cycle arrangement adjustment processing unit 237 adjusts instruction arrangement in each cycle based on the schedule result in the instruction scheduling unit 232.

  The in-cycle arrangement adjustment processing unit 237 rearranges the three instructions in the target cycle from the second cycle to the last cycle of the schedule result, and creates six instruction sequences (S61). FIG. 20 is a diagram showing an example of the six instruction sequences created in this way.

  The in-cycle arrangement adjustment processing unit 237 executes processing (S62 to S67) for obtaining the sum of the Hamming distances for each of six instruction sequences to be described later. From among the sum of the hamming distances obtained for each of the six instruction sequences, an instruction sequence that takes the minimum sum of the Hamming distances is selected, and the instructions are rearranged so that they are arranged in sequence (S68). The above processing is repeated from the second cycle to the final cycle (S60 to S69).

  Next, processing for obtaining the sum of the Hamming distances for each of the six instruction sequences (S62 to S67) will be described. The in-cycle arrangement adjustment processing unit 237 obtains the Hamming distance between the bit patterns of the operation code of the instruction of interest and the instruction of the previous cycle for each slot of each instruction sequence (S64). The processing for obtaining the Hamming distance (S64) is performed for all the instructions in the three slots (S63 to S65), and the sum of the Hamming distances is obtained for each of the instructions in the three slots (S66). The above processing is performed for all six instruction sequences (S62 to S67).

  FIG. 21 is a diagram illustrating an example of arranged instructions. In the Nth cycle, “ld Vr10, Vr11”, “sub1 Vr12, Vr13”, and “add1 Vr14, Vr15” are arranged as instructions executed in the first slot, the second slot, and the third slot, respectively. Shall. In the (N + 1) th cycle, “st Vr16, Vr17”, “mul Vr18, Vr19” and “mod Vr20, Vr21” are arranged as instructions executed in the first slot, the second slot, and the third slot, respectively. Shall.

  FIG. 22 is a diagram for explaining the instruction arrangement creating process (S61). For example, six instruction sequences shown in FIGS. 22A to 22F are created from three instructions arranged in the (N + 1) th cycle shown in FIG.

  FIG. 23 is a diagram for explaining the operation code Hamming distance calculation processing (S64). For example, when the Hamming distance of the opcode is calculated for each slot between the Nth cycle instruction sequence shown in FIG. 21 and the N + 1th cycle instruction sequence shown in FIG. 22C, the first slot and the second slot are calculated. And the Hamming distances in the third slot are 10, 9 and 5, respectively.

  Therefore, the sum of the Hamming distances in the example of FIG. In the Hamming distance sum calculation process (S66), Hamming is performed between the instruction sequence at the Nth cycle shown in FIG. 21 and each of the six instruction sequences shown in FIGS. 22 (a) to (f). The sum of distances is determined to be 14, 16, 24, 22, 24, and 20, respectively. In the instruction arrangement selection process (S68), the instruction arrangement shown in FIG. 22A, which takes the sum of the minimum Hamming distances, is selected from the six instruction arrangements.

[Register allocation section]
FIG. 24 is a flowchart showing the operation of the register allocation unit 234. The register allocation unit 234 actually performs register allocation based on the schedule results in the instruction scheduling unit 232 and the in-cycle arrangement adjustment processing unit 237.

  The register allocation unit 234 extracts allocation targets (variables) from the source program 202, and obtains the life spans and priority levels of the allocation targets (S72). The life interval is an interval from when a variable is defined in the program until the reference ends. Accordingly, there may be a plurality of life intervals even for the same variable. The priority is determined by the life span length to be assigned and its reference frequency. Since the detailed description is not an essential matter of the present invention, it will be omitted.

  The register allocator 234 creates an interference graph from the allocation target (S74). The interference graph is a graph showing conditions to be allocated that cannot allocate the same register. Next, a method for creating an interference graph will be described.

  FIG. 25 is a diagram illustrating a life span of a variable to be assigned. Here, an example is shown in which three variables of variables I, J, and K are assigned.

  Variable I is defined in step T1 and is finally referenced in step T5. The variable I is defined at step T8 and finally referred to at step T10. Therefore, the variable I has two life spans. The variable I in the previous life interval is defined as the variable I1, and the variable in the later life interval is defined as the variable I2. Variable J is defined in step T2 and is finally referenced in step T4.

  The variable K is defined in step T3 and finally referred to in step T6. The variable K is defined in step T7 and is finally referred to in step T9. Therefore, like the variable I, the variable K has two life spans. The variable K in the previous life interval is defined as the variable K1, and the variable K in the later life interval is defined as the variable K2.

  In the variables I1, I2, J, K1, and K2, there are overlaps of life spans as shown below. That is, the life spans of the variables I1 and J have an overlap at steps T2 to T4. The life spans of variables J and K1 have overlap at steps T3 to T4. The life spans of variables I1 and K1 have overlap at steps T3 to T5. Variables I2 and K2 have overlap in steps T8-T9. In this way, variables with overlapping life intervals cannot be assigned to the same register. For this reason, the variable to be allocated is a node, and the variables in which the live ranges overlap are connected by an edge is an interference graph.

  FIG. 26 is a diagram illustrating an interference graph of variables created based on the example of FIG. Nodes I1, K1 and J are connected to each other by edges. For this reason, it can be seen that there are sections in which the survival periods overlap between the variables I1, K1, and J, and the same register cannot be assigned to these three variables. Similarly, nodes I2 and K2 are connected by an edge. For this reason, it can be seen that the same register cannot be assigned to the variables I2 and K2.

  However, there is no dependency between nodes that are not connected by an edge. For example, nodes J and K2 are not connected by an edge. For this reason, it can be seen that the variables J and K2 do not overlap the live ranges and can be assigned the same register.

  Referring to FIG. 24 again, the register allocation unit 234 selects an allocation target with the highest priority among allocation targets for which register allocation is not performed (S80). The instruction scheduling unit 232 determines whether or not a register having the same number as the register number in the same field can be allocated among the instructions executed immediately before the instruction that refers to the allocation target in the same slot as the allocation target. (S82). Judgment as to whether allocation is possible is performed by referring to the above-described interference graph.

  FIG. 27 is a diagram illustrating a result of instruction scheduling. For example, referring to FIG. 27A, it is assumed that the current allocation target is allocated to the source operand (register Vr5) of the (N + 1) th cycle of the first slot. The register Vr5 is a provisionally provided register as described above. Therefore, in the register allocation possibility determination process (S82) of FIG. 24, it is determined whether or not the register (here, register R0) used in the same field of the Nth cycle can be allocated. Become. FIG. 27B shows a bit pattern of an instruction when register R0 is assigned to Vr5. Thus, when the same register is accessed between successive cycles, power consumption can be reduced due to the characteristics of the register.

  If it is determined that the register with the same number can be allocated (YES in S82), the register allocation unit 234 allocates the register with the same number to the allocation target (S84). When it is determined that the register with the same number cannot be allocated (NO in S82), the register allocation unit 234 determines the register of the same slot in the preceding cycle among the register numbers (binary representation) of the register that can be allocated. A value that minimizes the Hamming distance between the register numbers in the same field is obtained (S86). FIG. 27C shows an example in which the register R1 having the register number (00001) that minimizes the Hamming distance from the register number (00000) of the register R0 is selected from the available registers.

  If there is only one register that can be allocated with the minimum Hamming distance (NO in S88), the register is allocated to the allocation target (S92). If there are two or more assignable registers with the minimum Hamming distance (YES in S88), any of the two or more assignable registers is arbitrarily selected and assigned to the assignment target (S90). The above processing is performed until there are no more allocation targets (S78 to S94).

  After the processing in the register allocation unit 234, the in-cycle arrangement adjustment processing unit 237 adjusts the arrangement of instructions in each cycle based on the schedule result in the register allocation unit 234. The processing executed by the in-cycle arrangement adjustment processing unit 237 is the same as that described with reference to FIGS. 19 and 20. Therefore, detailed description thereof will not be repeated here.

[Instruction rescheduling section]
FIG. 28 is a flowchart showing the operation of the instruction rescheduling unit 236. The instruction rescheduling unit 236 reschedules the schedule result of the instruction scheduled to be operable by the processor 30 by the processing executed by the instruction scheduling unit 232, the register allocation unit 234, and the in-cycle arrangement adjustment processing unit 237. Perform processing. That is, the instruction rescheduling unit 236 performs scheduling again on the instruction sequence whose actual register is determined by the register allocation unit 234.

  The instruction rescheduling unit 236 deletes redundant instructions from the schedule result (S112). For example, the instruction “mov1 R0, R0” is a redundant instruction because it is a process of writing the contents of the register R0 into the register R0. Further, when the instruction in the first slot of the same cycle is “mov2 4, R1” and the instruction in the second slot is “mov2 5, R1”, these are instructions that write 4 and 5 to the register R1 respectively. . In the present embodiment, it is assumed that the instruction in the slot with the larger number is preferentially executed. Therefore, the instruction “mov2 4, R1” in the first slot is a redundant instruction.

  When redundant instructions are deleted, the dependency of instructions may change. Therefore, the instruction rescheduling unit 236 reconstructs the dependency graph (S114). The instruction rescheduling unit 236 selects an executable instruction (node) from the dependency graph, and schedules the instruction in the first cycle so as to match the default logic of each slot (S115). A placed flag is attached to the node of the dependency graph corresponding to the instruction in the first cycle.

  The instruction rescheduling unit 236 refers to the dependency graph and generates a placement candidate instruction set (S118). The instruction rescheduling unit 236 extracts one optimum instruction from the arrangement candidate instruction set according to an algorithm described later (S122).

  The instruction rescheduling unit 236 determines whether or not the fetched optimum instruction can actually be arranged (S124). The determination as to whether or not the arrangement is possible is the same as the determination in S14 of FIG. Therefore, detailed description thereof will not be repeated here.

  If it is determined that placement is possible (YES in S124), the optimum instruction is temporarily placed and deleted from the placement candidate instruction set (S126). Thereafter, the instruction rescheduling unit 236 determines whether or not further instructions can be arranged in the same manner as the above-described arrangement possibility determination (S124) (S128). If it is determined that placement is possible (YES in S128), the dependency graph is referred to, and if a new placement candidate instruction is generated, it is added to the placement candidate instruction set (S130). The above processing is repeated until there is no arrangement candidate instruction (S120 to S132).

  If it is determined that the instruction cannot be arranged in the target cycle after the optimum instruction temporary arrangement process (S126) (NO in S128), the optimum instruction temporary arrangement process (S120 to S132). Exit the loop.

  After the optimal instruction temporary placement process (S120 to S132), the instruction rescheduling unit 236 determines the temporarily placed instruction and ends the scheduling for the placement candidate instruction set (S134). Thereafter, for the arranged instruction, the arranged flag is attached to the corresponding node of the dependency graph, and the dependency graph is updated (S136).

  The instruction rescheduling unit 236 determines whether or not the same number of instructions are continuously arranged for a predetermined cycle or more (S137). If it is determined that the same number of instructions are continuously arranged for a certain cycle or more (YES in S137), the instruction rescheduling unit 236 sets the maximum number of instructions that can be arranged to 3 (S138), and the subsequent cycles Then, as much as possible, three instructions are arranged in one cycle. The above processing is repeated until there are no unplaced instructions (S116 to S139).

  FIG. 29 is a flowchart showing the operation of the optimum instruction fetch process (S122) of FIG. The instruction rescheduling unit 236 obtains the number of fields having the same register number by comparing with the instruction executed in the same slot of the cycle immediately before the target cycle among the arrangement candidate instructions, and the number is the maximum. Is determined (S152).

  FIG. 30 is a diagram for explaining the arrangement candidate instruction specifying process (S152). Assume that “add1 R0, R2” is arranged as an instruction to be executed in the first slot of the Nth cycle, and “sub1” shown in FIG. 30A is an instruction that can be arranged in the first slot of the (N + 1) th cycle. Assume that there are R0, R1 "and" div R0, R2 "shown in FIG. As shown in FIG. 30A, when the instruction “sub1 R0, R1” is arranged at the arrangement position, the field having the same register number is only the field in which the register R0 (register number 00000) is arranged. It is. For this reason, the number of fields having the same register number is one. As shown in FIG. 30 (b), when the instruction “div R0, R2” is arranged at the arrangement position, two fields in which the register R0 (register number 00000) and the register R2 (00010) are arranged are respectively displayed. Have the same register number. For this reason, the number of fields having the same register number is two.

  If there is only one placement candidate instruction with the maximum number (NO in S154), the placement candidate instruction is determined as the optimum instruction (S174).

  If there is no placement candidate instruction with the maximum number or there are two or more placement candidate instructions (YES in S154), the instruction rescheduling unit 236 executes each placement candidate instruction in the same slot of the previous cycle. Compared with the instruction to be executed, the instruction having the minimum Hamming distance of the bit pattern of the instruction is obtained (S156).

  FIG. 31 is a diagram for explaining the arrangement candidate instruction specifying process (S156). Assume that “mul1 R3, R10” is arranged as an instruction to be executed in the first slot of the Nth cycle, and “add1” shown in FIG. 31A is shown as an instruction that can be arranged in the first slot of the (N + 1) th cycle. Assume that there are R2, R4 "and" sub2 R11, R0, R2 "shown in FIG. The bit pattern of each instruction is as shown in the figure. As shown in FIG. 31A, when the instruction “add1 R2, R4” is arranged at the arrangement position, the Hamming distance to the instruction “mul1 R3, R10” is 10. As shown in FIG. 31B, when the instruction “sub2 R11, R0, R2” is arranged at the arrangement position, the Hamming distance to the instruction “mul1 R3, R10” is 8. Therefore, “sub2 R11, R0, R2” is specified as the arrangement candidate instruction.

  If there is one placement candidate instruction having the minimum Hamming distance (NO in S158), the placement candidate instruction is set as the optimum instruction (S172).

  If there are two or more placement candidate instructions having the minimum Hamming distance (YES in S158), a placement candidate instruction that matches the default logic of the slot in which the placement candidate instruction is executed out of the two or more placement candidate instructions. Is identified (S160).

  FIG. 32 is a diagram for explaining the arrangement candidate instruction specifying process (S160). Assume that “st R1, R13” is arranged as an instruction to be executed in the first slot of the Nth cycle, and “ld” shown in FIG. 32A is given as an instruction that can be arranged in the first slot of the (N + 1) th cycle. Assume that there are “R30, R18” and “sub1 R8, R2” shown in FIG. The bit pattern of each instruction is as shown in the figure. The default logic of the first slot is a command related to memory access as described above. This can be distinguished from the fact that the first two bits of the instruction are “01”. Since the first 2 bits of the instruction “ld R30, R18” are “01”, it matches the default logic of the first slot, but the first 2 bits of the instruction “sub1 R8, R2” is “11”. It does not match the default logic of 1 slot. For this reason, “ld R30, R18” is specified as the placement candidate instruction.

  If there is no placement candidate instruction that matches the default logic (NO in S162), one of the placement candidate instructions having the minimum Hamming distance is arbitrarily selected and set as the optimum instruction (S170).

  If there is a placement candidate instruction that matches the default logic and the number is one (YES in S162, NO in S164), the placement candidate instruction that matches the default logic is determined as the optimum instruction (S168).

  If there is a placement candidate instruction that matches the default logic and the number is two or more (YES in S162, YES in S164), any one of the placement candidate instructions that matches the default logic is arbitrarily selected, The optimum instruction is selected (S166).

  After the processing in the instruction rescheduling unit 236, the in-cycle arrangement adjustment processing unit 237 adjusts the arrangement of instructions in each cycle based on the schedule result in the instruction rescheduling unit 236. The processing executed by the in-cycle arrangement adjustment processing unit 237 is the same as that described with reference to FIGS. 19 and 20. Therefore, detailed description thereof will not be repeated here.

  The operation of the instruction rescheduling unit 236 has been described above. However, the number of slots used in one cycle may be limited according to the compile option or pragma described in the source program. A pragma is a description that gives optimization guidelines for a compiler without changing the meaning of a program. For example, as shown in Example 1, “-para” is provided as an option when compiling a source program written in C language, and the number of slots is defined by the subsequent numbers. In Example 1, the source program “foo.c” is compiled by the C compiler, but two instructions are necessarily arranged in each cycle of the schedule result.

  Further, as shown in Example 2, the number of slots used for each function described in the source program may be defined by a pragma. In Example 2, the number of slots used when executing the function func is defined as one. For this reason, in the schedule result, only one instruction is necessarily arranged in each cycle for executing the function func.

(Example 1)
cc-para 2 foo. c
(Example 2)
#Pragma para = 1 func
int func (void) {
・ ・ ・ ・ ・ ・
}

  When options and pragmas are set at the same time, the smaller value may be given priority. For example, when the function func and its pragma shown in Example 2 are specified in the source program “foo.c” shown in Example 1, two-slot parallel processing is executed in principle, but the function func In the cycle in which the process is executed, the schedule result is created so that the process is executed in only one slot.

  Further, options and pragmas may be considered not only in the instruction rescheduling unit 236 but also in the operation of the instruction scheduling unit 232 or the register allocation unit 234.

[Slot stop / return instruction generator]
FIG. 33 is a flowchart showing the operation of the slot stop / return command generation unit 238. The slot stop / return instruction generation unit 238 detects a section in which only one specific slot is continuously used for a predetermined cycle (for example, four cycles) or more from the schedule result in the instruction rescheduling unit 236 (S182). The slot stop / return instruction generation unit 238 inserts an instruction to stop the remaining two slots at the empty slot position one cycle before the above section (S184). If there is no empty slot position to insert an instruction one cycle before, one cycle is added and the instruction is inserted.

  Next, the slot stop / return command generation unit 238 inserts a command for returning the two slots stopped at the empty slot position after one cycle of the section (S186). If there is no empty slot position to insert an instruction after the cycle, one cycle is added and the above instruction is added.

  FIG. 34 is a diagram illustrating an example of a schedule result in which instructions are arranged. In the 9th cycle from the 10th cycle to the 18th cycle, only the first slot is continuously used. Therefore, an instruction (“set1 1”) for operating only the first slot and stopping the remaining two slots is written in the empty slot of the ninth cycle. In addition, an instruction (“clear1 1”) for restoring the remaining two slots is written in the empty slot of the 19th cycle. FIG. 35 is a diagram showing an example of a schedule result in which an instruction is written in the processing (S182 to S186) when only one specific slot in FIG. 33 is continuously used.

  Referring to FIG. 33 again, slot stop / return instruction generation unit 238 detects a section in which only two specific slots are continuously used for a predetermined cycle (for example, four cycles) or more from the schedule result (S188). The slot stop / return instruction generation unit 238 inserts an instruction to stop the remaining one slot at the empty slot position one cycle before the above section (S190). If there is no empty slot position to insert an instruction one cycle before, one cycle is added and the instruction is inserted.

  Next, the slot stop / return instruction generation unit 238 inserts an instruction for returning one slot that has been stopped at an empty slot position after one cycle of the section (S192). If there is no empty slot position to insert an instruction after the cycle, one cycle is added and the above instruction is added.

  In the schedule result of FIG. 35, only the first and second slots are used in the fifth cycle from the fourth cycle to the eighth cycle, and the third slot is not used. Therefore, it is necessary to write an instruction for stopping the third slot (“set2 12”) and an instruction for returning (“clear2 12”) in the preceding and succeeding cycles. However, instructions are arranged in all slots in both the third and ninth cycles. Therefore, the slot stop / return instruction generation unit 238 inserts a new cycle one cycle before the fourth cycle and after the eighth cycle, and writes the two instructions in each cycle. FIG. 36 is a diagram illustrating an example of a schedule result in which an instruction is written in the processing (S188 to S192) when only the specific two slots in FIG. 33 are continuously used.

  In this embodiment, it is assumed that instructions are arranged in the order of the first slot, the second slot, and the third slot. Therefore, when two slots are operating, the third slot is not always operating, and when only one slot is operating, the second and third slots are always operating. It will not be.

  The processor 30 is provided with a 32-bit program status register (not shown). FIG. 37 is a diagram illustrating an example of a program status register. For example, the number of slots operating with 2 bits of 15 and 16 bits can be represented. In this case, FIGS. 37A to 37D show that the number of operating slots is 0 to 3, respectively.

  FIG. 38 shows another example of the program status register. In this program status register, the 14th bit corresponds to the first slot, the 15th bit corresponds to the second slot, and the 16th bit corresponds to the third slot. A value of “1” for each bit indicates that the slot is operating, and a value of “0” indicates that the slot is stopped. For example, the program status register shown in FIG. 38B indicates that the first slot is stopped and the second and third slots are operating.

  The value held in the program status register is rewritten by the above-described instruction “set1” or “set2”.

  Although the compiler according to the present embodiment has been described above, each part of the compiler 200 can be modified as follows. Next, the modifications will be sequentially described.

[Modifications of each part of the compiler]
[Modification of Operation of Instruction Rescheduling Unit 236]
In the present embodiment, the operation of the instruction rescheduling unit 236 has been described with reference to FIGS. 28 and 29. Instead of the optimum instruction fetching process (S122) of FIG. 28 described with reference to FIG. The optimum instruction fetch process shown in FIG. 39 may be performed.

  FIG. 39 is a flowchart showing another operation of the optimum instruction fetch process (S122) of FIG.

  The instruction rescheduling unit 236 obtains the minimum Hamming distance by the following method instead of the process of obtaining the minimum Hamming distance (S156) in FIG. That is, the instruction rescheduling unit 236 obtains the one in which the hamming distance of the bit pattern of the register field is the minimum compared with the instruction executed in the same slot of the previous cycle among the arrangement candidate instructions (S212). .

  FIG. 40 is a diagram for explaining the arrangement candidate instruction specifying process (S212). Assume that “add1 R0, R2” is arranged as an instruction to be executed in the first slot of the Nth cycle, and “sub1 R3” shown in FIG. 40A is an instruction that can be arranged in the first slot of the (N + 1) th cycle. , R1 ”and“ div R7, R1 ”shown in FIG. 40B. The bit pattern of each instruction is as shown in the figure. As shown in FIG. 40A, when the instruction “sub1 R3, R1” is arranged at the arrangement position, the Hamming distance between the register fields of the instruction “add1 R0, R2” is four. As shown in FIG. 40B, when the instruction “div R7, R1” is arranged at the arrangement position, the Hamming distance between the register fields of the instruction “add1 R0, R2” is 5. Therefore, “add1 R0, R2” is specified as the arrangement candidate instruction.

  Other processes (S152 to S154, S158 to S174) are the same as those described in FIG. Therefore, detailed description thereof will not be repeated here.

[First Modification of In-Cycle Arrangement Adjustment Processing Unit 237]
The in-cycle arrangement adjustment processing unit 237 may execute the process shown in FIG. 41 instead of the process described with reference to FIG.

  FIG. 41 is a flowchart showing a first modification of the operation of the in-cycle arrangement adjustment processing unit 237.

  The in-cycle arrangement adjustment processing unit 237 obtains the minimum Hamming distance by the following method instead of the process of obtaining the Hamming distance (S64) in FIG. That is, the in-cycle arrangement adjustment processing unit 237 obtains the Hamming distance between the bit patterns between the target instruction and the instruction of the previous cycle for each slot in each instruction list (S222). Other processes (S60 to S63, S65 to S69) are the same as those described with reference to FIG. Therefore, detailed description thereof will not be repeated here.

  FIG. 42 is a diagram for explaining the instruction Hamming distance calculation processing (S222). For example, when the Hamming distance of the instruction is calculated for each slot between the Nth cycle instruction sequence shown in FIG. 21 and the N + 1th cycle instruction sequence shown in FIG. 22C, the first slot and the second slot And the Hamming distances in the third slot are 12, 11 and 11, respectively.

  Therefore, the sum of the Hamming distances in the example of FIG. In the Hamming distance sum calculation process (S66), Hamming is performed between the instruction sequence at the Nth cycle shown in FIG. 21 and each of the six instruction sequences shown in FIGS. 22 (a) to (f). The sum of the distances is determined to be 28, 26, 34, 28, 34 and 30 respectively. In the instruction arrangement selection process (S68), the instruction arrangement shown in FIG. 22B that takes the sum of the minimum Hamming distances is selected from the six instruction arrangements.

  Note that, in the process of obtaining the Hamming distance (S222) of this modification, it is assumed that a register is allocated. For this reason, the process in the in-cycle arrangement adjustment processing unit 237 according to the present modification cannot be executed after the process in the instruction scheduling unit 232 to which no register is allocated, and after the process in the register allocation unit 234. Alternatively, it is executed after the processing in the instruction rescheduling unit 236.

[Second Modification of In-Cycle Arrangement Adjustment Processing Unit 237]
The in-cycle arrangement adjustment processing unit 237 may execute the process shown in FIG. 43 instead of the process described with reference to FIG.

  FIG. 43 is a flowchart showing a second modification of the operation of the in-cycle arrangement adjustment processing unit 237.

  The in-cycle arrangement adjustment processing unit 237 obtains the minimum Hamming distance by the following method instead of the process of obtaining the Hamming distance (S64) in FIG. That is, the in-cycle arrangement adjustment processing unit 237 obtains the Hamming distance between the bit patterns in the register field between the instruction of interest and the instruction of the previous cycle for each slot of each instruction list (S232). Other processes (S60 to S63, S65 to S69) are the same as those described with reference to FIG. Therefore, detailed description thereof will not be repeated here.

  FIG. 44 is a diagram for explaining the Hamming distance calculation process (S232) of the register field. For example, when the Hamming distance of the register field is calculated for each slot between the N-th cycle instruction sequence shown in FIG. 21 and the N + 1-th cycle instruction sequence shown in FIG. The Hamming distances in the slot and the third slot are 2, 2 and 6, respectively.

  Therefore, the sum of the Hamming distances in the example of FIG. In the Hamming distance sum calculation process (S66), Hamming is performed between the instruction sequence at the Nth cycle shown in FIG. 21 and each of the six instruction sequences shown in FIGS. 22 (a) to (f). The sum of distances is determined to be 14, 10, 10, 6, 10 and 10, respectively. In the instruction arrangement selection process (S68), the instruction arrangement of FIG. 22 (d) that takes the sum of the minimum Hamming distances is selected from the six instruction arrangements.

  Note that, in the process of obtaining the Hamming distance (S232) of this modification, it is assumed that a register is allocated. For this reason, the process in the in-cycle arrangement adjustment processing unit 237 according to the present modification cannot be executed after the process in the instruction scheduling unit 232 to which no register is allocated, and after the process in the register allocation unit 234. Alternatively, it is executed after the processing in the instruction rescheduling unit 236.

[Third Modification of In-Cycle Arrangement Adjustment Processing Unit 237]
The in-cycle arrangement adjustment processing unit 237 may execute the process shown in FIG. 45 instead of the process described with reference to FIG.

  FIG. 45 is a flowchart showing a third modification of the operation of the in-cycle arrangement adjustment processing unit 237.

  The in-cycle arrangement adjustment processing unit 237 executes the following process instead of the process (S64) for obtaining the Hamming distance in FIG. That is, the in-cycle arrangement adjustment processing unit 237 obtains the number of register fields having the same register number between the target instruction and the instruction of the previous cycle for each slot in each instruction list (S242).

  Further, the in-cycle arrangement adjustment processing unit 237 executes the following processing instead of the processing (S66) for obtaining the sum of the Hamming distances in FIG. That is, the in-cycle arrangement adjustment processing unit 237 obtains the sum of the number of register fields having the same register number obtained for each of the instructions in the three slots (S244).

  Further, the in-cycle arrangement adjustment processing unit 237 executes the following process instead of the instruction rearrangement process (S68) of FIG. That is, the in-cycle arrangement adjustment processing unit 237 selects an instruction sequence that takes the sum of the maximum number of register fields from the sum of the numbers of register fields obtained for each of the six instruction sequences, and the instruction sequence. The instructions are rearranged so as to be arranged as follows (S246). Other processes (S60 to S63, S65, S67, and S69) are the same as those described with reference to FIG. Therefore, detailed description thereof will not be repeated here.

  FIG. 46 is a diagram illustrating an example of arranged instructions. In the Nth cycle, “ld R0, R1”, “sub1 R2, R3” and “add1 R4, R5” are arranged as instructions executed in the first slot, the second slot, and the third slot, respectively. Shall. In the (N + 1) th cycle, “st R5, R8”, “mul R2, R3”, and “mod R0, R10” are arranged as instructions executed in the first slot, the second slot, and the third slot, respectively. Shall.

  FIG. 47 is a diagram for explaining the instruction arrangement creating process (S61). For example, six instruction sequences shown in FIGS. 47A to 47F are created from three instructions arranged in the (N + 1) th cycle shown in FIG.

  FIG. 48 is a diagram for explaining the register field number calculation process (S242). For example, the number of register fields having the same register number for each slot is obtained between the instruction sequence of the Nth cycle shown in FIG. 46 and the instruction sequence of the (N + 1) th cycle shown in FIG. 47 (f). For the first slot, the number is 1 because the register R0 is common to the same register field in both cycles and the registers in the other register fields are different. For the second slot, the number is 2 because registers R2 and R3 are common to the same register field in both cycles. For the third slot, the number is 0 because there is no common register in the same register field.

  Therefore, the sum of the number of register fields having the same register number in the example of FIG. In the register field number sum calculation process (S244), in this way, between the instruction sequence of the Nth cycle shown in FIG. 46 and each of the six instruction sequences shown in FIGS. 47 (a) to 47 (f). The sum of the number of register fields is obtained and becomes 0, 2, 0, 0, 0, 1 and 3, respectively. In the instruction arrangement selection process (S246), the instruction arrangement shown in FIG. 47 (f) that takes the maximum number of register fields is selected from the six instruction arrangements.

  Note that the processing (S242) for obtaining the number of register fields in this modification is based on the premise that registers are allocated. For this reason, the process in the in-cycle arrangement adjustment processing unit 237 according to the present modification cannot be executed after the process in the instruction scheduling unit 232 to which no register is allocated, and after the process in the register allocation unit 234. Alternatively, it is executed after the processing in the instruction rescheduling unit 236.

[Fourth Modification of In-Cycle Arrangement Adjustment Processing Unit 237]
The in-cycle arrangement adjustment processing unit 237 may execute the process shown in FIG. 49 instead of the process described with reference to FIG.

  FIG. 49 is a flowchart showing a fourth modification of the operation of the in-cycle arrangement adjustment processing unit 237.

  The in-cycle arrangement adjustment processing unit 237 executes the following process instead of the process (S63 to S66) for obtaining the sum of the Hamming distances for each instruction array in FIG. That is, the in-cycle arrangement adjustment processing unit 237 obtains the number of instructions that match the default logic of the slot among the instruction of interest and the included instructions (S252).

  The in-cycle arrangement adjustment processing unit 237 executes the following process instead of the instruction rearrangement process (S68) of FIG. In other words, the in-cycle arrangement adjustment processing unit 237 selects the instruction sequence that takes the maximum number from the number of instructions that match the default logic obtained for each of the six instruction sequences, and arranges the instruction sequences. The instructions are rearranged (S254). Other processes (S60 to S62, S67, and S69) are the same as those described with reference to FIG. Therefore, detailed description thereof will not be repeated here.

  For example, it is assumed that six instruction sequences shown in FIGS. 47A to 47F have been created in the instruction sequence creation process (S61). As described above, whether or not the instruction and the included instruction match the default logic of the slot in which the instruction is arranged can be determined by referring to the first two bits of the instruction. For example, in the instruction sequence shown in FIG. 47B, the first 2 bits of the instruction placed in the first slot is “01”, which matches the default logic of the slot, but the second slot and the third slot Since the first 2 bits of the instruction placed in are “11” and “10” respectively, they do not match the default logic of the slot. For this reason, there is one instruction that matches the default logic in the slot. In this way, in the number calculation process (S252), the number of instructions that match the default logic is obtained for each of the six instruction sequences, which are 3, 1, 1, 0, 0, and 1, respectively. In the instruction arrangement selection process (S254), the instruction arrangement shown in FIG. 47A that takes the maximum number of instructions that match the default logic is selected from the six instruction arrangements.

  As described above, according to compiler 200 in the present embodiment, instruction placement is optimized so that the Hamming distance between instructions, opcodes, and register fields is reduced between cycles in the same slot. Therefore, a machine language program is generated in which the bit change of the value held in the instruction register of the processor is small and the processor can be operated with low power consumption.

  In addition, the instruction arrangement is optimized so that accesses to the same register continue in the same register field of the same slot. For this reason, access to the same register is continued, a change in the control signal for selecting the register is reduced, and a machine language program that can operate the processor with low power consumption is generated.

  In addition, instructions are assigned to each slot to match the default logic. For this reason, in the same slot, an instruction using the same component of the processor is continuously executed. For this reason, a machine language program capable of operating the processor with low power consumption is generated.

  Furthermore, when an instruction cycle of an instruction that uses only one slot or two slots continues, the supply of power to the empty slot can be stopped during that period. For this reason, a machine language program capable of operating the processor with low power consumption is generated.

  Furthermore, the number of slots to be used when executing a program can be specified by a pragma or a compile option. For this reason, an empty slot can be generated and the supply of power to the empty slot can be stopped. For this reason, a machine language program capable of operating the processor with low power consumption is generated.

  Although the compiler according to the present invention has been described based on the embodiment, the present invention is not limited to this embodiment.

  For example, in the optimum instruction fetching process (S122) of the instruction rescheduling unit 232 described with reference to FIGS. 28 and 29, the number of fields having the same register number (S152) and hamming with the instruction executed immediately before Although the optimum instruction is specified in the order of distance (S156) and default logic (S160) of the slot, this priority is not limited to this, and the optimum instruction may be specified with other priorities.

  Further, various conditions such as the Hamming distance and the default logic of the slot considered when specifying the optimum instruction are not limited to this embodiment. In short, any combination of conditions or priority order may be used so that the total power consumption is reduced when the processor is operated by the compiler according to the present invention. Needless to say, the same applies to the processing other than the instruction scheduling unit 232, such as the instruction scheduling unit 232, the register allocation unit 234, and the in-cycle arrangement adjustment processing unit 237.

  Furthermore, a combination of these conditions and priorities may be parameterized and incorporated as a header file of the source program 202 at the time of compilation, or these parameters may be designated as compiler options.

  Furthermore, the processing in the optimization unit 230 of the present embodiment may be performed by selecting an optimum one from several scheduling methods for each basic block. For example, for each basic block, a scheduling result may be obtained for all of a plurality of scheduling methods prepared in advance, and a scheduling method that is predicted to have the smallest power consumption may be selected.

  Further, an optimal scheduling method may be selected using a method such as backtracking. For example, even after selecting a scheduling method in which the power consumption is predicted to be the smallest in the instruction scheduling unit 232, when the register allocation is performed in the register allocation unit 234, the predicted power consumption is less than the expected value. When the value becomes larger, the instruction scheduling unit 232 selects a scheduling method that is predicted to have the second lowest power consumption, and performs register allocation. As a result, if the predicted power consumption becomes smaller than the planned value, the instruction rescheduling process by the instruction rescheduling unit 236 may be executed. Furthermore, in this embodiment, an example of converting a source program written in C language into a machine language program has been described. However, the source program may be a high-level language other than C language, or another compiler. It may be a machine language program compiled in When the source program is a machine language program, a machine language program in which the machine language program is optimized is output.

It is a figure which shows the structure of the instruction | indication which a processor which concerns on this Embodiment decodes and performs. It is a block diagram which shows schematic structure of the processor which concerns on this Embodiment. It is a figure which shows an example of a packet. It is a figure for demonstrating the parallel execution boundary information contained in a packet. It is a figure which shows an example of the execution unit of the command performed in parallel produced based on the parallel execution boundary information of a packet. It is a block diagram which shows schematic structure of an arithmetic logic and comparison operation part. It is a block diagram which shows schematic structure of a barrel shifter. It is a block diagram which shows schematic structure of a divider. It is a block diagram which shows schematic structure of a multiplication and a product-sum operation part. FIG. 10 is a timing chart showing each pipeline operation when an instruction is executed by a processor. It is a figure which shows the command performed with a processor, the content of a process, and its bit pattern. It is a functional block diagram which shows the structure of the compiler which concerns on this Embodiment. It is a flowchart which shows operation | movement of an instruction scheduling part. It is a figure which shows an example of a dependence graph. It is a figure which shows an example of the schedule result of a command. It is a flowchart which shows the operation | movement of the optimal command extraction process of FIG. It is a figure for demonstrating the calculation method of the Hamming distance between the bit patterns of an opcode. It is a figure for demonstrating the calculation method of the Hamming distance between the operation codes from which bit length differs. It is a flowchart which shows operation | movement of the arrangement adjustment process part in a cycle. It is a figure which shows an example of 6 types of instruction sequences. It is a figure which shows an example of the arrange | positioned instruction | indication. It is a figure for demonstrating a command arrangement | sequence creation process (S61 of FIG. 19). It is a figure for demonstrating the Hamming distance calculation process (S64 of FIG. 19) of an opcode. It is a flowchart which shows operation | movement of a register allocation part. It is a figure which shows the lifetime of the variable used as allocation object. It is a figure which shows the interference graph of the variable produced based on the example of FIG. It is a figure which shows the intermediate result of instruction scheduling. It is a flowchart which shows operation | movement of an instruction rescheduling part. It is a flowchart which shows the operation | movement of the optimal instruction extraction process of FIG. It is a figure for demonstrating arrangement | positioning candidate command specific processing (S152 of FIG. 29). It is a figure for demonstrating arrangement | positioning candidate command specific processing (S156 of FIG. 29). It is a figure for demonstrating arrangement | positioning candidate command specific processing (S160 of FIG. 29). It is a flowchart which shows operation | movement of a slot stop / restoration command generation part. It is a figure which shows an example of the schedule result by which the instruction | command is arrange | positioned. It is a figure which shows an example of the schedule result in which the command was written by the process in case only one specific slot of FIG. 33 is used continuously. It is a figure which shows an example of the schedule result in which the command was written by the process in case only 2 specific slots of FIG. 33 are used continuously. It is a figure which shows an example of a program status register. It is a figure which shows another example of a program status register. FIG. 29 is a flowchart showing another operation of the optimum instruction fetch process of FIG. 28. FIG. It is a figure for demonstrating arrangement | positioning candidate command specific processing (S212 of FIG. 39). 12 is a flowchart showing a first modification of the operation of the in-cycle arrangement adjustment processing unit 237. FIG. 42 is a diagram for explaining a command Hamming distance calculation process (S222 in FIG. 41). 12 is a flowchart illustrating a second modification of the operation of the in-cycle arrangement adjustment processing unit 237. FIG. 44 is a diagram for describing a Hamming distance calculation process (S232 in FIG. 43) of a register field. 12 is a flowchart showing a third modification of the operation of the in-cycle arrangement adjustment processing unit 237. It is a figure which shows an example of the arrange | positioned instruction | indication. It is a figure for demonstrating a command arrangement | sequence creation process (S61 of FIG. 45). FIG. 46 is a diagram for describing a register field number calculation process (S242 in FIG. 45). 12 is a flowchart showing a fourth modification of the operation of the in-cycle arrangement adjustment processing unit 237.

Explanation of symbols

DESCRIPTION OF SYMBOLS 30 Processor 40 Instruction memory 50 Instruction supply issue part 52 Instruction fetch part 54 Instruction buffer 56 Instruction register part 56a-56c Instruction register 60 Decoding part 62 Instruction issue control part 64 Decoding part 64a-64c Instruction decoder 70 Execution part 72 Execution control part 74 PC unit 76 Register file 78a to 78c Arithmetic logic / comparison operation unit 80a, 80b Multiply / product sum operation unit 82a to 82c Barrel shifter 84 Divider 88 Operand access unit 90, 92 Data bus 94 OD bus 96 OA bus 100 Data memory 112, 114 Packet 122, 124, 126 Execution unit 132 ALU unit 134, 154, 180 Saturation processing unit 136 Flag unit 142, 162, 172 Accumulator unit 146, 148, 178 Selector 150 Rushifuta 152 lower barrel shifter 164 divider 174a, 174b 32-bit multiplier (MUL)
176a to 176c 64-bit adder (Adder)
DESCRIPTION OF SYMBOLS 200 Compiler 202 Source program 204 Machine language program 210 Parser part 220 Intermediate code conversion part 230 Optimization part 232 Instruction scheduling part 234 Register allocation part 236 Instruction rescheduling part 237 In-cycle arrangement adjustment processing part 238 Slot stop / return instruction generation part 239 Parallel execution boundary information setting unit 240 Code generation unit

Claims (4)

A compiler apparatus for translating a source program into a machine language program for a processor having a plurality of execution units capable of parallel processing and a plurality of instruction issuance units that respectively issue instructions executed by the plurality of execution units. ,
Parser means for parsing the source program;
Intermediate code conversion means for converting the analyzed source program into intermediate code;
Priority is given to an instruction that accesses the same register as the register of the instruction arranged at the position corresponding to the same instruction issuing unit of the immediately preceding instruction cycle without breaking the dependency relation of the instruction corresponding to the intermediate code, An optimization means for optimizing the intermediate code by arranging the instruction at a corresponding position in each of a plurality of instruction issuing units;
A compiler apparatus comprising: code generation means for converting the optimized intermediate code into a machine language instruction.   The optimization means prioritizes an instruction that accesses a register having a number close to the register number of the register of an instruction arranged at a position corresponding to the same instruction issuing unit of the immediately preceding instruction cycle, and the plurality of instruction issuing units. The compiler apparatus according to claim 1, wherein the instruction is arranged at a position corresponding to each of. A compiling method for translating a source program into a machine language program for a processor having a plurality of execution units capable of parallel processing and a plurality of instruction issuing units each issuing instructions executed by the plurality of execution units. ,
A parser step for parsing the source program;
An intermediate code conversion step of converting the analyzed source program into an intermediate code;
Priority is given to an instruction that accesses the same register as the register of the instruction arranged at the position corresponding to the same instruction issuing unit of the immediately preceding instruction cycle without breaking the dependency relation of the instruction corresponding to the intermediate code, An optimization step of optimizing the intermediate code by placing the instruction at a corresponding position in each of a plurality of instruction issuing units;
And a code generation step of converting the optimized intermediate code into a machine language instruction. A program for a compiler that translates a source program into a machine language program for a processor having a plurality of execution units capable of parallel processing and a plurality of instruction issuing units that issue instructions executed by the plurality of execution units. There,
The program is
A parser step for parsing the source program;
An intermediate code conversion step of converting the analyzed source program into an intermediate code;
Priority is given to an instruction that accesses the same register as the register of the instruction arranged at the position corresponding to the same instruction issuing unit of the immediately preceding instruction cycle without breaking the dependency relation of the instruction corresponding to the intermediate code, An optimization step of optimizing the intermediate code by placing the instruction at a corresponding position in each of a plurality of instruction issuing units;
A code generation step for converting the optimized intermediate code into a machine language instruction.

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