JP2000284968A - Method and device for compiling - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize register assignment for avoiding false dependence by deciding a real register as a candidate for preferentially assigning to a virtual register when the real register which never generate a new inter-instruction dependence relation exists based on information showing a section analyzing result and inter-instruction dependence relation. SOLUTION: By inputting a source program written in a high-level language, an analysis part 1 analyzes characters/phrases, syntax, etc., with respect to the inputted source program 11 to generate a first intermediate code 12. Next, an optimization part 2 optimizes the code 12 for accelerating processing to generate a second intermediate code 13. The part 2 executes flow analysis, data depending analysis, and instruction assignment, register assignment, etc. An output part 3 generates a machine language (object program) 14 which can be executed by an object processor based on the optimized code 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an out-of-o
The present invention relates to a compiling method and a compiling apparatus for generating an object program to be executed on a processor having a plurality of arithmetic units that operate in parallel and support rder execution.

[0002]

2. Description of the Related Art CPU for increasing instruction execution speed
As an architecture, a CPU architecture having a plurality of arithmetic units that operate in parallel while sharing a register and a cache is known. A typical example is VLIW, which statically allocates resources at compile time and uses them.
(Very Long Instruction Wo
rd) and superscalar that dynamically allocates resources at the time of execution (JL Hennessy).
& D. A. Patterson, “COMP
UTER ARCHITECTURE A QUANT
ITATIVE APPROACH ”, Chapter
r4). Hereinafter, such CPU architectures are collectively referred to as an ILP architecture (ILP: Ins).
fraction-Level Parallellis
m).

In the ILP architecture, hardware has resources capable of executing a program at high speed by executing a plurality of instructions in parallel. However, in order to actually exhibit high speed, the parallelism at the time of instruction execution (hereinafter, ILP) is required. Call it)
Must be high, and the strategy for this is key.

[0004] Out-of-
Order execution is known. That is, in the in-order execution, which is a normal method, the execution start order of an instruction arranged to start execution in a certain cycle and an instruction arranged to start execution in a later cycle is maintained. Can be However, even if the order of the instructions is later, if there is no dependency on the instructions placed earlier, the execution of the later instructions can be started without waiting for the earlier instructions, thereby increasing the speed. It is possible to achieve. A method for realizing this is called out-of-order execution. Many existing superscalars actually take out-of-order execution (however, conventional VLIW assumes in-of-order execution, and
VLIWs that take t-of-order execution are not known).

I for executing out-of-order execution
In the CPU of the LP architecture, it is important to avoid false dependency. What is false dependency?
FIG. 24 shows a dependency generated when a subsequent instruction redefines a register used in a preceding instruction.
As shown in (a), the register R2 used by the instruction A
Is defined by the instruction B executed after the instruction A,
appear. Here, using a register means referring to (reading) the value of the register, and defining a register means changing (writing) the value of the register. When the instruction sequence shown in FIG. 24A is executed, it is necessary to wait for the execution of the instruction B until the result of the instruction A is guaranteed to be correct even if the value of the register R2 is redefined by the instruction B. Instruction A and instruction B cannot be executed at the same time, resulting in a decrease in ILP.

[0006] In super scalar, false depth
In order to avoid dendency, a method called register renaming is often used. This is shown in FIG.
Taking (a) as an example, by replacing the register R2 which depends on the instruction B with a register (for example, register R7) which does not cause a dependency, a false dependency between the instruction A and the instruction B is replaced.
y is avoided. At this time, for the other instruction using the value of the register R2 defined by the instruction B in the original program, the used register R2 is also changed to the register R7.
Need to be replaced with In the case of this example, the instruction sequence after register renaming is as shown in FIG.
Instruction A and instruction B can be executed simultaneously.

Although false dependency is conventionally avoided by register renaming as described above, this process performs complicated control at the time of execution, and causes a problem that the frequency of the CPU cannot be increased. It was not the best way.

[0008] Fa without register renaming
In order to avoid a decrease in speed due to lsdependency, when the compiler generates an instruction sequence to be executed by the CPU in advance, falsedependency is used.
It is necessary to generate the cy so that it does not easily occur.

However, the order in which instructions are executed in out-of-order execution cannot be statically estimated at compile time. for that reason,
When real registers are assigned to virtual registers based on the virtual register live range that is statically estimated at compile time, the live range shifts due to dynamic instruction issuance at runtime, and the same real register is allocated. F between instructions
There was a problem that the "alse dependency" occurred.

[0010]

As described above,
In an ILP architecture processor that performs out-of-order execution, false
Avoiding dependency is important. Register renaming used in superscalar is fals
Although e dependency can be avoided, complicated control is performed at the time of execution, so that there is a problem that it is difficult to contribute to speeding up. In addition, there is no conventional compiling method that considers to avoid false dependency. On the other hand, there is no known VLIW capable of executing out-of-order execution.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a compiling method and a compiling apparatus for a processor that supports out-of-order execution, without using a register renaming mechanism by hardware. out-of-order execution specific fals
It is an object of the present invention to provide a compiling method and a compiling device that enable register allocation to avoid e-dependency.

[0012]

Means for Solving the Problems The present invention (claim 1) provides:
The present invention is directed to a processor having a plurality of arithmetic units capable of executing instructions in parallel and having a function of enabling execution of an instruction following the instruction in the instruction arrangement order to start before execution of the instruction preceding the instruction. A compiling method for generating an object program executable by the processor based on the source program obtained, comprising: an analyzing step of analyzing the source program to generate a first intermediate code; An instruction scheduling step of generating a second intermediate code which is described by allocating a virtual register as a register for storing a temporary result of an operation by performing instruction scheduling, and generating a second intermediate code, and a second intermediate code and a real register of the processor. Assigned to each virtual register based on information A register allocation step of determining a real register to be provided, and an output step of outputting an object program in which the virtual register has been replaced with the allocated real register, wherein the register allocation step is such that the real register is assigned to the virtual register. Analyzing the allocated and used section and the used section of the virtual register to which the real register is allocated; and analyzing the section analysis result and information indicating the inter-instruction dependency that has already occurred. If there is a real register that does not cause a new inter-instruction dependency even if it is allocated to the virtual register that has been allocated,
Determining the real register as a candidate to be preferentially assigned to the virtual register.

The information (for example, a dependency graph) indicating the inter-instruction dependency is created, for example, initially by analyzing a source program (for example, a data dependency analysis process). In addition, for example, when a new inter-instruction dependency is generated when the assignment of the real register to the virtual register is determined in the determining step, the new inter-instruction dependency is determined. It will be reflected.

Preferably, among the real registers which do not cause a new inter-instruction dependency even when assigned to the allocation-target virtual register, a redundant inter-instruction dependency is actually caused, but the redundant The priority order of real registers that can be regarded as not resulting in a new inter-instruction dependency as a result of the inter-instruction dependency already existing is determined by the actual inter-instruction dependency relationship. The priority may be set higher than the real register allocation priority such that no new instruction-to-instruction dependency is caused by not causing such a dependency.

[0015] Preferably, the register allocating step includes, among the registers other than the real register that does not cause the new dependency, the real register whose instruction arrangement order and instruction execution start order can be exchanged with each other. The method may further include the step of determining as a candidate to be assigned in the priority order next to the real register that does not cause any significant dependency.

Preferably, among the real registers capable of exchanging the instruction arrangement order and the instruction execution start order, the live range of the virtual register to be allocated and the real area whose allocation is determined at that time. An actual register having a greater distance from a register live range may be determined as a candidate to be assigned with a higher priority.

[0017] Preferably, the real register that makes the critical path length in the inter-instruction dependency smaller may be determined as a candidate to be assigned with a higher priority.

[0018] Preferably, the register allocating step sets a virtual register to which a real register is to be allocated based on the number of other virtual registers having a portion overlapping the live range of the virtual register and the number of real registers of the processor. The method may further include the step of determining the order of the registers.

Preferably, in the register allocating step, the real register having the highest priority among the real registers determined for the virtual register to be allocated and which can be actually allocated at that time is selected. The method may further include the step of selecting and storing a correspondence between the virtual register and the selected real register.

According to the present invention (claim 8), a plurality of arithmetic units capable of executing instructions in parallel are provided, and the execution of the following instruction in the instruction arrangement order can be started before the execution of the preceding instruction. A compiling device for generating an object program executable by the processor based on a given source program for a processor having a function of: generating a first intermediate code by analyzing the source program Analysis means; instruction scheduling means for performing instruction scheduling based on the first intermediate code, and assigning and describing a virtual register as a register for storing a temporary result of the operation to generate a second intermediate code; Based on the second intermediate code and information about the real registers of the processor, Register assignment means for determining a real register to be assigned to each virtual register; and output means for outputting an object program in which the virtual register is replaced with the assigned real register, wherein the register assignment means includes the real register Means for analyzing a section used by being assigned to the virtual register and a section used by the virtual register to which the real register is assigned; and the section analysis result and inter-instruction dependency already occurring. If there is a real register that does not cause a new inter-instruction dependency even if the real register is allocated to the allocation target virtual register based on the information indicating the real register, the real register is preferentially allocated to the virtual register. Determining means.

According to the present invention (claim 9), it is possible to provide a plurality of arithmetic units capable of executing instructions in parallel and to start the execution of the following instruction in the instruction arrangement order before the execution of the preceding instruction. For a processor having the function of, in order to generate an object program executable by the processor based on a given source program, the source program is analyzed to generate a first intermediate code, Performing instruction scheduling based on the first intermediate code, assigning a virtual register as a register for storing a temporary result of an operation to generate a second intermediate code, and generating a second intermediate code, the second intermediate code and the processor Real registers to be assigned to the respective virtual registers based on the information about the real registers of And an output step of outputting an object program in which the virtual register is replaced by the real register to which the virtual register is assigned. And the section used by the virtual register to which the real register is assigned is analyzed based on the section analysis result and information indicating the inter-instruction dependency that has already occurred. To
If there is a real register that does not cause a new inter-instruction dependency even if it is allocated to the allocation target virtual register, a program for determining the real register as a candidate to be preferentially allocated to the virtual register is recorded. The gist is a computer-readable recording medium.

In the present invention, when a real register is assigned to a virtual register in the second intermediate code, if there is a real register that does not cause a new inter-instruction dependency even if it is assigned to the virtual register to be assigned, The real register is preferentially determined (or determined to be allocated) as a candidate to be allocated to the allocated virtual register. Here, the “live range of the register” is a section from the point at which the value of the register is defined to the point at which the value is last referenced. Depending on how the registers are used, there may be multiple live ranges.

More specifically, for example, a flow analysis and data dependency are performed from the second intermediate code, a dependency graph is generated, and a live range of a virtual register in which a temporary result of the operation is stored is calculated. Based on this, a real register to be assigned to the virtual register is determined. The most ideal real register to be assigned to a virtual register is an actual register whose assignment does not cause a new dependency in the dependency graph. An actual register satisfying such a condition is determined based on, for example, a dependency graph.

By allocating the real registers as described above, it is possible to prevent a decrease in ILP at the time of executing the out-of-order.

If a real register that does not cause a new dependency can be allocated, the speed does not decrease due to the allocation of the register when executing the instruction. However, since real registers are finite and such real registers do not always exist, it is necessary to select a real register to be assigned to a virtual register from among real registers that cause a new dependency. In some cases.

In such a case, the newly generated dependency may cause a reduction in execution speed. However, even if a new dependency is generated by allocating to a virtual register, the dependency is out-of- orde
A real register that does not cause a decrease in speed during execution of r, or minimizes the decrease even if the speed decreases (for example, a new dependency is generated in the dependency graph when assigned to a virtual register) Even so, it is preferable to preferentially allocate an actual register that is expected to increase the difference between the timings at which those instructions are executed.

According to the present invention, it is possible to prevent a new dependency between instructions from occurring due to register allocation,
Even if it occurs, it is possible to make the execution timing between instructions having a new dependency relationship as far apart as possible. For this reason, without using a register renaming mechanism by hardware,
False dependency, which causes a decrease in ILP during execution of t-of-order, can be minimized. Moreover, while register renaming by hardware can be performed only for a limited number of instructions, a wide range of register analysis can be performed by a compiler, and registers can be more effectively used.

The present invention relating to the apparatus is also realized as an invention relating to a method, and the present invention relating to a method is also realized as an invention relating to an apparatus.

Further, the present invention relating to a compiler apparatus or a method is provided for causing a computer to execute a procedure corresponding to the present invention (or for causing a computer to function as means corresponding to the present invention, or for causing a computer to execute the procedure corresponding to the present invention). The present invention is also realized as a computer-readable recording medium on which a program (for realizing a corresponding function) is recorded.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

An optimizing compiler according to an embodiment of the present invention will be described. The optimizing compiler according to the present embodiment performs out-of-order
An executable processor (CPU) is assumed. Note that the present invention is applicable to a superscalar processor capable of executing out-of-order.
Although the present invention can be applied to a VLIW that can execute -of-order, a super scalar processor that can execute out-of-order is well known, so a detailed description thereof is omitted here, and the out-of-order is omitted. The executable VLIW will be described after the description of the compiler.

FIG. 1 shows a configuration example of the optimizing compiler according to the present embodiment.

This compiler receives a source program (11) written in a high-level language as an input,
The first intermediate code (12) is generated by performing lexical analysis, syntax analysis, and the like on the input source program (11). In the lexical analysis processing, a character string forming the input source program (11) is analyzed and divided into words. For example, in the syntax analysis processing, the words obtained by the analysis are collated with the grammar of the high-level language to determine whether or not they are correct, and if there is an error, this is notified and the execution is stopped. If it is correct, a syntax analysis result is generated as an intermediate code (12). The generated intermediate code (12) is stored in a storage device such as a main storage or a disk. The intermediate code (12) is
Usually, it is managed inside the compiler and cannot be accessed from outside.

Next, in the optimizing unit 2, optimization for speeding up the processing of the intermediate code (12) (to increase the execution speed when the generated object program is executed by the target processor). To optimize the second intermediate code (13). In the present embodiment, it is assumed that, in the optimizing unit 2, the register allocation by the register allocating unit 22 is performed after the instruction scheduling by the instruction scheduling unit 21 is performed. More specifically, for example, the optimization unit 2 performs flow analysis, data dependency analysis, instruction scheduling (instruction allocation), register allocation, and the like. In the flow analysis processing, when the intermediate code (12) is generated, the program flow is analyzed based on the intermediate code (12). In the data dependency analysis process, when the analysis of the program flow is performed, a data dependency analysis is performed on each instruction constituting the intermediate code (12) to create a dependency graph, and the instructions must be assigned in any order. Clarify the constraints such as not to be. In the instruction scheduling process, an intermediate code (one to which a virtual register is assigned) (13) is generated immediately before the object program based on the intermediate code. The generated intermediate code (13) is stored in a storage device such as a main storage or a disk. Intermediate code (13)
Is normally managed internally by the compiler and cannot be accessed externally. In the register allocation process, the intermediate code (13) generated by the instruction scheduling process
, The virtual register temporarily allocated in the instruction scheduling process is re-allocated to the real register of the target processor. Here, the correspondence between the virtual register and the real register is registered in the register correspondence table.

Then, the output unit 3 generates and outputs a machine language (object program) (14) executable by the target processor based on the optimized intermediate code (13). That is, the output unit 3 replaces the virtual register of the optimized intermediate code (13) with a real register based on the register correspondence table, and then outputs it as a machine language (14).

The processor that executes the machine language (14) (that is, the processor targeted by this compiler) has a plurality of arithmetic units that operate in parallel, can execute a plurality of instructions at the same time, and out-of-order
It has an execution function and further has a real register assigned to a virtual register by the compiler.

In the present embodiment, a description will be given of a register allocation method using a graph coloring technique as an example. The graph coloring technique is one of the most widely used methods for allocating real registers to virtual registers.

FIG. 2 shows an example of the processing procedure of the register allocation method using the graph coloring technique.

As shown in FIG. 2, the register allocation method starts with a phase for generating a register interference graph (step S11). The “node” in this graph is a “virtual register”, and as described in detail later, if the point at which the value of the virtual register is defined is within the live range of another virtual register, it corresponds to those virtual registers. Connected nodes are connected by "edges".

FIG. 3 shows an example of a program (written in MIPS assembly language) for which real registers are to be allocated. In the example of FIG. 3, {100, # 101, # 102, # 103,}
104 is a virtual register. Also, here
It is assumed that there are three registers $ 1, $ 2, and $ 3 that can be used for assignment.

FIG. 4 is a dependency graph showing the dependency between instructions in the case of the example of FIG. Instruction (2) “lui
The instruction (4) “s” based on the execution result of “$ 101, 0x2000” (in this case, the execution result is written in $ 101)
Since w {101, tmp1 ($ 0) "is executed,
An edge (shown by a unidirectional arrow in FIG. 4) indicating a dependency is provided between the instruction (2) and the instruction (4).
Similarly, the instruction (3) “lui @ 102,0x300
0 ”and instruction (5)“ ori $ 103, $ 102, 0x
1111 ", and the instruction (5) and the instruction (6)" s
It is shown that there is also a dependency between w {103, tmp2 ($ 0) ".

FIG. 5 shows a live range of each virtual register in the case of the example of FIG. As shown in FIG.
00 is from the start of the instruction (1) to the end of the instruction (7), $ 101 is from the start of the instruction (2) to the start of the instruction (4), and $ 102 is from the start of the instruction (3). Until the start of the instruction (5), $ 103 is from the start of the instruction (5) to the start of the instruction (6), and $ 104 is from the start of the instruction (7) to the end of the instruction (7). Let it be a live range.

FIG. 6 is a register interference graph generated in this case. In # 100, since the live range overlaps with all the other virtual registers, edges are set for all the virtual registers. $ 101 is $ 1 other than $ 100
02 and # 102 are overlapped, so an edge is also formed between # 102 and # 102. $ 1 for $ 103 and $ 104
Only 00 and the live range overlap.

It is necessary to allocate different real registers to virtual registers having overlapping live ranges. Therefore,
In the register interference graph thus created, by coloring (coloring) each node connected by an edge as if it were painted with another color (real register) (ie, The real register is allocated so that the same real register is not allocated to both nodes connected by the edge. Considering the example of FIG. 6, when the real register # 1 is allocated to $ 100, $ 101 and # 10 are connected to $ 100 by edges.
2, # 103 and # 104 must be assigned real registers other than $ 1 ($ 2 or $ 3 in this example).

When the register interference graph has been generated in step S11, it is next determined from which node in the register interference graph a real register is to be allocated. This process is performed by steps S12 to S15 shown in FIG.

In step S12, among the nodes in the register interference graph, the number of edges emerging from the node (ie, the number of other nodes adjacent to the node) is determined by the number of real registers that can be allocated. If fewer nodes are detected and such a node exists, the node is removed from the register interference graph in step S14 to reconstruct the register interference graph. Here, reconstructing the register interference graph means deleting the detected node and the edge in contact with the detected node from the register interference graph. The order in which the nodes to be removed are detected is arbitrary (that is, when there are a plurality of nodes satisfying the above conditions, any node may be selected first regardless of the number of edges thereof). Absent).

The case of performing this processing in the example of FIG. 6 will be described.

First, in the register interference graph of FIG. 6, if, for example, consider $ 104, the only node adjacent to $ 104 is $ 100, so the number of adjacent nodes can be assigned. Is smaller than the actual register number “3”. So first, $ 104
Is removed from the register interference graph of FIG. 6, and the register interference graph is reconstructed. As a result, the register interference graph after the reconstruction is as shown in FIG. The nodes that have been removed are recorded in the order in which they were removed.

If there is no node in which the number of adjacent nodes is less than the number of real registers that can be allocated in step S12, the node is selected as a candidate for register spill processing in step S13, and the node is selected in step S14. Removes from the register interference graph and reconstructs the register interference graph. Various methods have already been proposed for selecting a register spill candidate.

The above processing is repeated until the register interference graph becomes empty in step S15.

The processing in the phases up to this stage may be the same as that of the conventional technique, and is a well-known technique, so that detailed description thereof is omitted here (Andrew W. Appe).
l "modern compiler implement
nation in C ″ Chapter 11).

In the case of the example shown in FIG. 6, similarly to the above-described step # 104, for example, steps {103, # 102, # 101,}
Nodes are removed in the order of 100. The register interference graph reconstructed at that time is as shown in FIG. 7 (a) → FIG. 7 (b) → FIG. 7 (c) → FIG. 7 (d) in order from the state of FIG. The register interference graph becomes empty as shown in FIG. In the example of FIG. 6, when the nodes are removed from the register interference graph in the above order, the candidates for the register spill are empty sets.

By the phases so far, the correspondence between the identification information of the virtual register and the order in which the virtual register is removed from the register interference graph is recorded. In the case of this specific example, it is recorded that the virtual registers have been removed from the register interference graph in the order shown in FIG.

In the above description, when the program of FIG.
Although an example is shown in which nodes are removed in the order of 04, # 103, # 102, # 101, and # 100, the order is not limited to this order as described above.
Even in the order of $ 101, $ 104, $ 100, $ 104, $ 100
Other orders, such as 103, # 102, # 100, and # 101, may be used.

When all the nodes have been selected from the interference graph, in step S16, real registers are assigned to the respective nodes in the reverse order of the selection of the nodes, and the nodes are re-registered in the register interference graph. Perform the returning process. Hereinafter, the process of step S16 will be described in detail.

FIG. 9 shows this phase (step S16).
2 shows an example of a processing procedure of a method of determining an actual register to be assigned to a node.

First, a virtual register to which a real register is to be assigned is selected in the reverse order of the order removed from the interference graph (step S21). In the case of this specific example, $ 100 is selected.

Next, in steps S22 to S24,
A real register to be assigned to the selected register is determined. First, it checks whether there is a real register that does not cause a new dependency, and if such a real register exists, registers it in the sequence of real registers that are prioritized ( Step S22). Subsequently, for real registers other than the real registers that do not cause a new dependency, out-of-order
The real registers whose new dependencies are not affected as much as possible during execution are registered in the priority-registered real register columns with priority (step S23).

FIG. 10 shows a sequence of real registers in priority order. As shown in FIG. 10, the priority order is higher in the order of the real registers that do not cause a new dependency and the real registers that generate a new dependency. Details will be described later,
Among real registers that do not generate new dependencies, there are those that generate redundant dependencies but can be hidden by existing dependencies, and those that do not generate redundant dependencies. Is high. In addition, among real registers that cause a new dependency, the priority order becomes higher as the distance between the instructions having the new dependency increases.

Subsequently, if a column of real registers with priority order is generated, a real register that can be assigned to a node is searched from the column in accordance with the priority order, and if a real register that can be assigned is found, Is registered in the register correspondence table (see FIG. 11) (step S24). In addition, for example, when there is some restriction on the assignment of the real registers, a real register that cannot be assigned may occur.

Then, the assigned node is returned to the register interference graph again. If the live range of the already arranged node overlaps with the live range of the node,
The register interference graph is reconstructed by forming an edge between the nodes (step S25).

The above processing is repeated until all the registers deleted from the register interference graph are rearranged in the register interference graph (step S26).

For example, in the example of FIG.
When real registers are assigned to nodes in the order of 101, # 102, # 103, and # 104, the register interference graph becomes as shown in FIG.
(C) → FIG. 7 (b) → FIG. 7 (a) → reconstructed as shown in FIG.

Here, the register correspondence table indicates which real register is to be assigned to each virtual register as shown in FIG. 11, and has as many entries as the number of virtual registers. FIG. 11 shows virtual registers # 100 and # 1
An example is shown in which real registers # 1, # 2, # 3, # 3, and # 2 are sequentially assigned to 01, # 102, # 103, and # 104. When the compiler finally outputs the machine language (14) in the output unit 3, after replacing the virtual register of the intermediate code (13) optimized based on this table with a real register, Output the machine language (14).

Next, of the processing in step S16 shown in FIG. 2, the processing in step S22 shown in FIG. 9 will be described in detail.

For convenience of explanation, “a set of real registers that generate redundant dependencies but can be hidden by existing dependencies” in FIG. 10 is referred to as a first priority register set and “real registers that do not generate redundant dependencies”. Set to the second priority register set, and the set of real registers that create new dependencies.
Is referred to as a third priority register set.

FIG. 12 shows an example of a detailed procedure of step S22.

Here, by assigning a certain real register to a selected certain node (that is, a virtual register), a real dependency that does not cause a new dependency with another instruction referring to the same real register is generated. Detecting registers or real registers that have existing dependencies between their instructions even if such new dependencies occur and the new dependencies can be ignored, and prioritize those real registers The registered real register is registered in the column. More specifically, a real register corresponding to the first priority register set in FIG. 10 is registered in a series of processing in steps S31 to S38, and then the second processing is performed in step S39.
A real register corresponding to the highest priority register set is registered.

First, registration of a real register corresponding to the “first priority register set” will be described.

Steps S31 to S35 are performed for each live range of a node to which a real register is assigned (the virtual register selected in step S21 shown in FIG. 9). Detects real registers that have no relationship.

In steps S31 to S33, among the real registers already allocated to another virtual register, a real register which may not cause a new dependency even if allocated to the node is detected. In step S31, a real register is detected so as not to cause a new dependency with respect to the instruction defining the node (instruction to change the value of the virtual register), and in step S32, the instruction using the node is detected. The detection of a real register that does not cause a new dependency with respect to (an instruction that refers to the value of the virtual register) is performed.

As for the instruction defining the node,
In the live range of the selected node, search for the instruction that defines the node, find the predecessor-dependent instruction common to all the instructions that define the node in the live range, and detect all the registers (real registers) that are used. . At this time, the instruction itself that defines the node is also included as a preceding dependent instruction. The detected real registers are set as a set of real registers which may not cause a new dependency even if the instructions defining the node are assigned to the node.

In the example of FIG. 3, it is assumed that $ 100 = $ 1, $ 101 = $ 2, $ 102 = $ 3 have already been allocated to the virtual registers, and the real register to be allocated next to virtual register $ 103 is selected. Think about it. The virtual register # 103 has only one live range as shown in FIG. Therefore, analysis is performed on this live range (from the start of the instruction (5) to the start of the instruction (6)). The only instruction that defines virtual register $ 103 in the live range is instruction (5). Looking at the dependency graph of FIG. 4, it can be seen that the preceding dependent instruction of the instruction (5) is the instruction (3). Therefore, the preceding dependent instructions common to the defined instruction are the instruction (3) and the instruction (5). Of the registers used by these two instructions, only the real register is allocated to {102}, and thus the real register set detected in the phase (step S31) is {3}.

Similarly, for an instruction using the node, an instruction using the node is searched for in the life cycle of the selected node, and an instruction common to all instructions using the node in the life cycle is searched. Find the subsequent dependent instructions and detect all their defining registers (real registers). At this time, the instruction itself using the node is also included as a subsequent dependent instruction. The detected real registers are set as a set of real registers that may not cause a new dependency even if the instructions using the node are assigned to the node.

Continuing to consider the example of FIG.
The only instruction that uses virtual register $ 103 in the live range of 103 is instruction (6). Referring to the dependency graph of FIG. 4, there is no subsequent dependency instruction of the instruction (6). Therefore, the only subsequent instruction common to the used instruction is the instruction (6). Since there is no register to which a real register is assigned among the registers defined by this instruction, the real register set detected in the phase (step S32) is an empty set.

Finally, in step S33, the union of these is calculated, and among the real registers already allocated to another virtual register, there is a possibility that a new dependency will not occur even if the real register is allocated to the node. It is a real register set.

In the example of FIG. 3, the union of {3} and the empty set is calculated, and the actual register set obtained in the phase (step S33) is {3}.

Next, in steps S34 and S35, the real registers from which a new dependency relationship occurs when assigned to the node from the above register set are deleted. In step S34, a real register in which a new dependency is generated for the instruction defining the node is detected, and in step S35, a real register in which a new dependency is generated for the instruction using the node is detected.

As for the instruction defining the node,
In the live range, all preceding instructions other than the preceding dependent instruction common to all the instructions defining the node are found, and all of their actual registers are detected. At this time, the instruction itself defining the node is also included as a preceding instruction. These are a set of real registers which, when assigned to the node, causes a new dependency with respect to the instruction defining the node,
It is deleted from the set of real registers obtained in step S33.

Next, consider the example of FIG. The preceding instructions other than the leading dependent instruction common to all the instructions defining the node are instructions (1), (2), and (4). Of the virtual registers used, those to which the real registers are assigned Since it is $ 101 and the real register assigned to $ 101 is $ 2, the used real register set is {2}. Therefore, {2} is deleted from the set {3} obtained in step S33 to become {3}.

Similarly, for instructions using the node, all the subsequent instructions other than the subsequent dependent instructions common to all the instructions using the node are found in the live range, and all the definition real registers are detected. I do. At this time, the instruction itself using the node is also included as a subsequent instruction. These are set as a real register set that causes a new dependency when assigned to the node with respect to the instruction using the node, and are deleted from the set of real registers obtained in step S33.

Next, consider the example of FIG. The succeeding instruction other than the following dependent instruction common to all instructions using the node is the instruction (7), and the virtual register defined by the instruction (7) is $ 104, but the real register is still allocated to $ 104. Therefore, the real register set defined by them is an empty set. Therefore, step S3
Delete the empty set from the set {3} found in 4 and {3}
Becomes

The processing of steps S31 to S35 is performed for all the live ranges of the node (step S3
6).

Next, in step S37, a real register set that does not cause a new dependency relationship in all the live ranges is detected, and when a real register that has already been allocated is assigned to the node, a new dependency is set. Extract the real register set for which no relation is generated.

Referring to the example of FIG. 3, virtual register $ 10
3 has only one live range. Therefore, step S3
The real register set obtained at the time of 7 is {3}.

Then, in step S38, FIG.
Of the real registers corresponding to the first priority register set. The actual register set that corresponds to this is set in step S3.
7, the real registers included therein are registered as the real registers having the highest priority order in the column of the real registers in the priority order.

In the example of FIG. 3, since the real register set obtained at the time of step S37 is {3}, the real register # 3 is registered in the priority-registered real register column.

Next, registration of a real register corresponding to the second priority register set will be described.

At step S39, a real register which has never been assigned to a node in the register interference graph is detected. Even if a real register that has never been allocated is allocated to the node, there is no redundant dependency with other instructions. Therefore, such a register is detected as a real register having no redundant dependency, and is registered as a real register having the second highest priority order in a row of the real registers which are prioritized. The reason that such real registers are given a lower priority than already allocated real registers is to reuse already allocated real registers as much as possible and to minimize the number of real registers used. In order to

In the example of FIG. 3, there is no real register to which no real register has been assigned among real registers # 1 and # 2 (since all real registers have already been allocated to nodes in the interference graph). None of the registers are registered in the sequence of prioritized real registers.

The above is the detailed description of the processing in step S22.

Next, the processing in step S23 of the processing in step S16 will be described in detail.

At step S23, at step S2
The priority ordering (that is, registration of the real registers corresponding to the “third priority register set”) is performed for the real registers that did not apply in step 2. In this phase, assigning a real register to the selected node (i.e., a virtual register) creates a new dependency with another instruction referencing the same real register,
Since the execution timings of instructions having a dependency greatly differ from each other, an actual register which is not affected by the dependency at the time of actual out-of-order execution, or which is small even if received, Priority.

FIG. 13 shows an example of a procedure in which the process of step S23 is detailed.

Here, for convenience of explanation, step S22
An example different from that described above will be used. That is, consider the case where the real register to be allocated to virtual register $ 104 is selected in the program of FIG. Note that $ 100 = $ 1, $ 101 = $ 2, $ 102 = $ already exist in the virtual register.
3, ＄ 103 = ＄ 3 is assigned. Also, there is no real register detected in step S22 for virtual register # 104.

First, in step S41, if there is a node (a node to which a real register has already been allocated) in the interference graph, the live range of the real register allocated to all the nodes is analyzed.

FIG. 14 shows the live ranges of the real registers and virtual registers # 104 which have already been allocated at the time of allocation to virtual registers # 104. The live range of the real register # 3 is the sum of the live ranges of the virtual registers # 102 and # 103 to which $ 3 is assigned.

Next, in step S42, the distance between the live range of the real register already allocated and the live range of the node to which the real register is to be allocated is calculated. The distance between live ranges is the number of cycles from the end of one live range to the start of the other live range. If there are multiple live ranges for a certain register, the distance is calculated for all of those ranges. Calculate and set the minimum value as the distance between the live ranges. In the present embodiment, it is assumed that instructions are executed one by one according to the arrangement of intermediate codes.

Further, in this embodiment, it is assumed that the calculated distance between the live ranges is corrected. Here, when the calculated distance is equal to or more than a certain value X, the distance is assumed to be the certain value X. In general, as the value of X, a value that is considered to have no influence of dependence if the distance is longer than that is used.

In the case where the live ranges overlap (interfere), the distance is set to a negative number.

In this way, the distance from all the real registers to the live range of the node is calculated.

Consider a specific example here. Assuming that constant value X is 10, the distance between virtual register # 104 and the real register is as follows. However,
The distance between the live ranges of the register is dist (reg
1, reg2). dist (＄ 1, ＄ 104) = − 1 dist (＄ 2, ＄ 104) = 3 dist (＄ 3, ＄ 104) = 1 Here, a distance of −1 means that live ranges overlap.

Next, in step S43, the real registers assigned to the nodes are prioritized. The ordering is performed in such a manner that the one with the largest distance between the live ranges is prioritized.

However, when there are a plurality of real registers having a constant distance X, the real registers assigned to other nodes at least once have priority. By doing so, reuse of the real registers is promoted, and the number of used real registers can be reduced as much as possible. Further, a real register having a negative distance cannot be assigned to a node, and is therefore excluded from the priority order. This processing is performed in step S44.

Considering the specific example here, the priority order of the real registers to be assigned to the virtual register # 104 is # 2, # 3 in descending order of priority.

Finally, in step S45, the real registers are registered in the priority-registered real register column in accordance with the priority order determined by the above processing.

Incidentally, in the example of step S23, $ 1
00 = $ 1, $ 101 = $ 2, $ 102 = $ 3, $ 10
When the virtual register is allocated to the real register as in 3 = $ 3, the priority of the real register (corresponding to the third priority register set) allocated to the virtual register $ 104 is $ 2, $ 3 Is an example of step S22,
That is, ＄ 100 = ＄ 1, ＄ 101 = ＄ 2, ＄ 102 =
Virtual register $ 103 when $ 3 is assigned
Regarding the priority order of the real registers in the example of selecting the real registers to be assigned to, after ＄ 3 is registered in the first priority register set of FIG. 10 in step S22 (the second priority register set is an empty set), the remaining ＄ When the distance is calculated with respect to 1 and ＄ 2, dist (＄ 1, ＝ 103) = − 1 dist (＄ 2, １103) = 1. Become.

The above is the detailed description of the processing in step S23.

Thus, steps S22, S23
Is generated, and in step S24, a real register that can be assigned to the node is searched for and assigned in descending order of priority in step S24.

For example, the example used in step S22 (# 1
In the case where 00 = $ 1, $ 101 = $ 2, and $ 102 = $ 3, the real register to be allocated to the virtual register $ 103 is selected). The priority is [$ 3,
＄ 2], and in step S24, one that can be assigned in the order of ＄ 3, ＄ 2 is found, and in this case,
$ 3 is selected and registered in the register correspondence table.

Further, for example, the example used in step S23 (＄ 100 = ＄ 1, ＄ 101 = ＄ 2, ＄ 102 = ＄ 3,
In the example of selecting the real register to be allocated to the virtual register $ 104 when $ 103 = $ 3 is allocated), the priority of the real register finally allocated to the virtual register $ 104 is [$ 2, $ 3]. , Step S2
In step 4, an assignable element is found in the order of # 2 and # 3. In this example, # 2 is selected and registered in the register correspondence table.

As a result, a register correspondence table having contents as shown in FIG. 11 is obtained.

Here, an example of the processing result according to the present embodiment is compared with an example of the processing result according to the related art.

FIG. 15A is output when register assignment is performed to the virtual register of FIG. 3 by a conventional method (such that the prioritization of this embodiment is not performed for the real register). It is an example of a code. In this case, ＄ 100 = ＄ 1, ＄ 101 = ＄ 2, ＄ 102 = ＄
The real registers are allocated to the virtual registers such as 3, $ 103 = $ 2, $ 104 = $ 2. In this code, the dependency between instructions is such that a new false dependency occurs between the instruction (4) and the instruction (5) and between the instruction (6) and the instruction (7). It becomes like this.

On the other hand, FIG. 16A shows a code output when a real register that has been prioritized using this embodiment is assigned to the virtual register in FIG. In this case, ＄ 100 = ＄ 1, ＄ 101 = ＄ 2, ＄ 102 =
The real registers are allocated to the virtual registers such that $ 3, $ 103 = $ 3, $ 104 = $ 2.
In this code, the dependency between instructions is a new false dependency between the instruction (4) and the instruction (7).
Is generated as shown in FIG. 16B. This has less dependency between instructions and a higher degree of freedom for scheduling as compared to FIG.

As a result of performing the register allocation in consideration of the dependencies between instructions as described above, it is possible to prevent a decrease in ILP due to the register allocation. In addition, a false dependency between the instruction (4) and the instruction (7) in FIG.
Regarding the density, since the timings at which these instructions are executed are far apart, this dependency is out-of-of
The effect on -order execution is small.

In the above, the distance between the live ranges of the registers is used as a priority order criterion for determining the priority order of the third priority register set in FIG. 10, but the priority order is determined based on other criteria. It may be determined. Hereinafter, a case where the priority order is determined based on the critical path length will be described as an example of another criterion. In addition,
In this case, since the processing is the same as the above-described processing except that step S23 in FIG. 9 and the processing in FIG. 13 are different, the description will be made focusing on the different points.

The critical path is the longest path in the dependency graph as shown in FIG. The path length indicates the number of cycles required for processing the path. That is,
The critical path length indicates the minimum number of cycles required for the entire instruction sequence to complete processing when the instruction sequence is executed in parallel assuming that the arithmetic unit is infinite. Note that the execution of one instruction may require a plurality of cycles, and the present invention also includes the case where the execution of one instruction requires a plurality of cycles. The case where it is assumed that the processing is performed will be described.

FIG. 17 shows a sequence of real registers in the order of priority based on the critical path length. As shown in FIG. 17, the priority order is higher in the order of a real register that does not cause a new dependency and a real register that generates a new dependency (this point is the same as described above). Here, among real registers that cause a new dependency, the priority order becomes higher as the critical path length of the entire instruction sequence when the new dependency occurs becomes smaller.

In order to create such a sequence of real registers in which priority is assigned, in the above-described embodiment, the priority order of the real registers assigned to the virtual registers is determined by using the distances dist (reg1, reg2) between the live ranges of the registers. In contrast, in the present embodiment, the virtual register reg _p
The priority order of the real registers is determined using the critical path length cp_length (reg _r , reg _p ) when the real registers reg _r are assigned to the real registers. When a real register is assigned to a virtual register, a new dependency occurs, so that the critical path length may change. However, this value differs depending on the real register to be assigned. The smaller the critical path length, the higher the possibility that the processing time of the entire instruction sequence can be shortened. Therefore, priority is given to the real registers whose critical path length after the assignment is small. However,
Those with overlapping (interfering) live ranges cannot be assigned to nodes, and are excluded from priority ordering.

Now, {100, $ 101, $ 102,}
Real registers are allocated in the order of 103 and # 104, and there are three real registers, $ 1, $ 2 and $ 3.
In the present embodiment, similar to the previous example, no new dependency is generated.
Real registers can be assigned to 100, $ 101, $ 102, and $ 103. That is, in the virtual register, {100 = $ 1, $ 101 = $ 2, $ 102 = $ 3, $}
It is assumed that real registers are allocated as 103 = $ 3.

Here, a case is considered in which a real register is allocated to $ 104.

First, as described above, the first and second priority register sets are empty sets.

Next, the real registers corresponding to the third priority register set and their priorities are obtained based on the critical bus length.

In this case, for # 1, # 104 and #
1 is excluded from the priority ordering because the live ranges overlap (interfere).

As for $ 2, if $ 2 is assigned to $ 104, a new false is added between instruction (4) and instruction (7).
Since -dependency occurs, the dependency graph is as shown in FIG. 18A, and the critical path length at this time is 3.

On the other hand, when $ 3 is assigned to $ 104, $ f is newly added between the instruction (6) and the instruction (7).
Since the “alse-dependency” occurs, the dependency graph is as shown in FIG. 18B, and the critical path length at this time is 4.

Therefore, cp_length ($ 2, $ 104) = 3 cp_length ($ 3, $ 104) = 4, and if the priority is given to the one with the smaller critical path length, the priority of the real register to be assigned to the virtual register $ 104 is given. The order is # 2, # 3 in descending order of priority.

Then, the priority order of the real registers finally allocated to the virtual register # 104 is [$ 2, $ 3]. In step S24, a register that can be allocated in the order of $ 2, $ 3 is found. In this case, $ 2 is selected and registered in the register correspondence table. As a result,
In the case of this example, the result of the real register allocation is the same as that of FIG.

By the way, in this embodiment, FIG.
7 in the sequence of the 7 real-ordered real registers.
After obtaining a corresponding register for each of the third priority register sets, in step S24 shown in FIG. 9, a search is made for the real registers that can be assigned to the target node from the priority-ordered real register column according to the priority order. It is determined whether a register can be assigned, and if it can be assigned, it is selected and registered in the register correspondence table (see FIG. 11). Instead, it may be determined whether or not the assignment is possible each time, and when the assignable register is obtained, the real register assignment process for the virtual register may be terminated. That is,
If an actual register corresponding to the first priority register set is obtained, it is determined whether or not it can be allocated. If it is, it is selected and the subsequent processing is omitted. If the assignment is not possible or if the first priority register set is an empty set, the process for the second priority register set is performed, and if a real register corresponding to the second priority register set is obtained, is it possible to assign it? It is determined whether or not it can be assigned, and if it can be assigned, it is selected and the subsequent processing is omitted.
When the assignment is not possible or when the second priority register set is an empty set, the process for the third priority register set is performed. If it is not necessary to determine whether or not allocation is possible, if an actual register corresponding to the first priority register set is obtained, it is selected and the subsequent processing is omitted. May perform a process on the second priority register set, and may perform a process on the third priority register set when an actual register is not determined in the process.

In the above embodiment, the case where the register allocation by the graph coloring method is used has been described. However, the present invention is not limited to the graph coloring method, but allocates to virtual registers in various register allocation methods. This is applicable when a real register to be selected is selected from a plurality of candidates.

As described above, the present invention provides an out-
Although the present invention can be applied to a VLIW that can execute an out-of-order, a conventional VL that can execute an out-of-order can be used.
Since there was no IW itself, in the following, out-of-o
der instruction issuance VLIW (hereinafter referred to as dynamic VLI
W) An embodiment of the invention relating to a processor will be described.

In the following, each of the instructions constituting one VLIW instruction may be called an atom. FIG.
FIG. 9 shows an example of one VLIW instruction. This is an example in which one VLIW instruction is composed of three atoms. The position where each atom constituting the VLIW instruction should enter is called a slot.

As a method for increasing the degree of parallelism at the instruction level, there are a VLIW method in which resources are statically allocated and used at compile time, and a superscalar method in which resources are dynamically allocated during execution.
In the VLIW method, since a compiler detects instructions that can be executed simultaneously, a mechanism for detecting the instructions at the time of execution is not required, hardware at the time of execution is simplified, and a high frequency may be achieved. However, the method of detecting instructions that can be executed simultaneously by the compiler includes parameters that cannot be completely predicted by the compiler or that cannot be realistically predicted.

The dynamic VLIW system is located between the superscalar system and the VLIW system. Basically, the dynamic VLIW system partially executes the VLIW system so that it is possible to reduce problems that are difficult to predict at the time of compiler. However, it operates to some extent dynamically and can proceed with processing without stopping the entire processor. That is, this dynamic VL
The IW method seeks a new optimal point of hardware and software (compiler) and aims at optimizing performance.

In a basic configuration of a processor based on the dynamic VLIW method, a pending queue for temporarily saving an fetched but unexecutable atom in order to enable a subsequent atom to be executed in advance is provided. It stores and manages information on the use status of each register, determines whether or not the fetched atom can be executed based on this information, executes the fetched atom if executable, and fetches if not executable The accumulated atoms are stored in the pending queue,
Judgment of the execution of the atom stored in the pending queue is performed. If the execution is possible, the atom is executed. It can be executed first.

This dynamic VLIW method is based on the VLI
The point of fetching an atom for each W instruction is the conventional in
-Order instruction issuance VLIW is the same as that of the VLIW instruction, but when a plurality of atoms of the simultaneously fetched VLIW instruction cannot be executed, the conventional in-order
In the r instruction issue VLIW, the fetch is always interrupted, but in the dynamic VLIW method, there is a possibility that the fetch need not be interrupted.

FIG. 20 shows such a dynamic VLI.
It is a conceptual diagram showing the basic structure of W processor.
In FIG. 20, two pipeline units (1006-
1, 1006-2). This dynamic VLIW processor is provided with a pending queue (P) for saving an atom fetched from an instruction sequence as an execution wait when the atom cannot be immediately executed.
Using queues 1002-1 and 1002-2 provided independently for each slot called “ending queue” and a scoreboard 1004 for managing information on the usage status of each register for each register, o
This is an example of realizing out-of-order.

An atom that is not executed among a plurality of atoms of the fetched VLIW instruction is executed until it becomes executable.
Stored in the corresponding pending queue.

The pending queue is preferably constituted by a FIFO (first-in first-out buffer). When the pending queue is configured by FIFO, the execution is performed in order from the first atom stored in the pending queue, which is different from the conventional superscalar reorder buffer. In other words, in exchange for a performance constraint that an executable atom may not be executable even if it exists in the pending queue, the hardware can be greatly simplified and the speed can be increased.

Further, the pending queue is VLIW
It is preferably provided for each slot into which the individual atoms making up the instruction are to enter. For example, the VLI illustrated in FIG.
When the format of the W instruction is used, since there are two slots, two pending queues are prepared.
Then, an atom that is not executed among the fetched VLIW instructions is put into a pending queue corresponding to the slot. The fact that a pending queue exists for each slot as described above and does not span slots also constitutes one of the limitations for simplifying hardware and increasing the speed.

In each cycle / each slot, the atoms giving an opportunity to execute may be an atom fetched from a normal instruction sequence or an atom from the pending queue when the pending queue is not empty.
Execution is prioritized in the order of (1) the fetched atom and (2) the atom in the pending queue.

The determination as to whether an atom given an execution opportunity (a fetched atom or an atom at the head of a pending queue) can be executed is based on the contents of the scoreboard (use of registers related to the atom).
Basically, if the register used by the atom is not available to the atom, it is determined that the atom cannot be executed.

As described above, in the present dynamic VLIW method, an out-of-order is realized by temporarily saving atoms that cannot be executed immediately in the pending queue and executing them when they become executable. ing.

In this dynamic VLIW system, registers are assigned by a compiler without having a renaming structure in the processor. Eliminating register renaming can simplify the hardware.
For this purpose, as a compiler for generating a VLIW instruction sequence, a compiler that allocates registers so that false dependency does not occur is used (a known compiler may be used).

Next, an outline of the dynamic VLIW will be described with reference to a simple example in order to show the effect of the dynamic VLIW.

FIG. 21 shows an example of an instruction sequence to be executed.
An example of an instruction sequence when two atoms are included in one VLIW instruction is shown.

In FIG. 21, each atom is a mnemonic, a destination (dest) register,
Registers of the first source (src1) and registers of the second source (src2) are described in this order.

As shown in FIG. 21, this instruction sequence includes ADD R8, R9, R10 and LD R5, (R3), LDI R18, 1000 and ADD R13, R9,
4. ADD R21, R18, R9 and SUB R11, R
5, R8, LSR R22, R21, 5 and ORI R24, R2
1, 0xFF, SUBI R25, R24, 5 and NOP, BRZ R11, R0, ROOP_EXT and NOP are fetched one set at a time in this order.

Note that the NOP atom may be an instruction that does not actually cause any operation, or may be an instruction that executes ADD or the like but does not cause any change as a result.

Hereinafter, the instruction sequence illustrated in FIG.
n-order instruction issue VLIW method and dynamic V
A description will be made in comparison with the case where the respective processes are executed by the LIW method.

FIG. 22 shows that this instruction sequence is a conventional in-or
FIG. 23 shows a state in which the der instruction is executed by the VLIW method, and FIG. 23 shows a state in which the instruction sequence is executed by the dynamic VLIW method.

In the examples of FIGS. 22 and 23, the first VLIW
LD (load instruction), which is the atom of the second slot of the instruction
Caused a miss in the primary cache and the corresponding data was 2
It is assumed that four cycles are required to load this because it exists in the next cache.

As shown in FIG. 22, when this instruction sequence is executed by the conventional in-order instruction issue VLIW method, in cycle 1, ADD R of the first slot is used.
8, R9, R10 and LD R5, (R
3) is executed, but since the LD in the second slot causes a cache miss, the four cycles of cycles 2 to 5 are stall due to the LD miss in both the first and second slots (while fetch is interrupted). Thereafter, the instructions are sequentially executed, and as a result, the processing is completed in 10 cycles.

Next, as shown in FIG. 23, when this instruction sequence is executed by the dynamic VLIW method, first, in cycle 1, ADD R8, R
9, R10 and LD R5, (R3) in the second slot are executed, and the LD causes a cache miss. From the next cycle, an atom using the destination register R5 of this LD cannot be executed until the LD is completed (the status of this register R5 is reflected on the scoreboard).

In cycle 2, since each atom of the VLIW instruction does not use R5, which is the destination register of LD, LDI R18,1000 and ADDI
R13, R9, and 4 are executed.

In cycle 3, ADD of the first slot
R21, R18, and R9 are executed because R5 is not used, but SUB R11, R5, and R8 in the second slot are
Since R5 is referred to as the first source register, it cannot be executed and is put into the pending queue (it can be seen that R5 cannot be used by referring to the scoreboard, so it cannot be executed). Also, from the next cycle, atoms (excluding this SUB) using the SUB destination register R11 cannot be executed until this SUB is completed (the status of this register R11 is also reflected on the scoreboard). Is done).

In cycle 4, since neither R5 nor R11 is used, LSR R22, R21, 5 and ORI R2
4, R21, 0xFF is executed.

In cycle 5, since neither R5 nor R11 is used, the SUBI R25, R24, 5 and NOP are executed.

Here, the LD is completed, and from the next cycle, R5 becomes available (the status of this register R5 is also reflected on the scoreboard).

In cycle 6, first, B in the first slot
RZ R11, R0, and ROOP_EX cannot be executed because R11 is the destination. As will be described in detail later, when the register to be used as the destination cannot be used, the register is not put into the pending queue and waits for the executable state (the fetch is interrupted). Therefore, this cycle becomes an empty slot. Since the fetch is interrupted, the execution of the fetched instruction in the second slot is also suspended.

Here, in the second slot, since the interruption of the fetch has occurred, the execution opportunity is given to the atom in the pending queue. SUs in the pending queue
BR11, R5, and R8 are executable because the previous LD has been completed and R5 is available (it can be understood by referring to the scoreboard).
Therefore, SUB R11, R5, and R8 are taken out of the pending queue and executed.

Here, SUB is completed, and R11 becomes usable from the next cycle (the status of this register R11 is also reflected on the scoreboard).

In cycle 7, BRZ R11, R0, ROOP_EXT waiting for execution in the first slot are
Executable and executed, and in the second slot, the NOP waiting for execution is executed.

As a result, the process is completed in seven cycles.

As described above, the conventional in-order instruction issuance VLIW system takes 10 cycles.
In the dynamic VLIW method, other atoms can execute out-of-ord during a miss due to an LD atom.
It can be seen that the execution of the er function is completed in seven cycles and the speed can be increased.

The present invention is also applicable to a compiler for such a VLIW processor that can execute out-of-order.

Note that the compiler in the present embodiment can also be realized as software. Further, the compiler according to the present embodiment is a computer-readable program that records a program for causing a computer to execute predetermined means (or for causing a computer to function as predetermined means or for causing a computer to realize predetermined functions). It can also be implemented as a possible recording medium.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope.

[0170]

According to the present invention, it is possible to prevent a new dependency between instructions from being generated due to register allocation, and to execute a timing between instructions that have a new dependency even if it occurs. Can be as far away as possible. Therefore, without using a register renaming mechanism by hardware,
It is possible to minimize false dependency, which causes a decrease in ILP during execution of out-of-order. Moreover, while register renaming by hardware can be performed only for a limited number of instructions, a wide range of register analysis can be performed by a compiler, and registers can be more effectively used.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a compiler according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure of graph coloring;

FIG. 3 shows an example of a program.

FIG. 4 is a diagram showing a dependency graph.

FIG. 5 is a diagram showing a live range of each virtual register;

FIG. 6 shows a register interference graph.

FIG. 7 is a diagram for explaining reconstruction of a register interference graph;

FIG. 8 shows a record of the order in which virtual registers are removed from the register interference graph.

FIG. 9 is a flowchart illustrating an example of a procedure of a process of assigning a real register to a virtual register;

FIG. 10 is a diagram showing an example of a column of real registers in a priority order;

FIG. 11 shows an example of a register correspondence table.

FIG. 12 is a flowchart illustrating an example of a procedure of a process related to a real register that does not cause a new dependency even when assigned to a virtual register;

FIG. 13 is a flowchart illustrating an example of a procedure of a process related to a real register that does not cause a new dependency when assigned to a virtual register;

FIG. 14 is a diagram showing a live range of a target virtual register and a real register.

FIG. 15 is a diagram showing an example of a processing result according to a conventional method.

FIG. 16 is a diagram illustrating an example of a processing result according to the embodiment;

FIG. 17 is a diagram showing another example of a column of real registers in a priority order;

FIG. 18 is a diagram illustrating an example of a critical path when real registers are allocated using a critical bus length.

FIG. 19 is a diagram showing an example of a VLIW instruction;

FIG. 20 is a diagram for explaining a dynamic VLIW method;

FIG. 21 is a diagram showing an example of an instruction sequence of a VLIW instruction;

FIG. 22 is a view for explaining a case where the instruction sequence of FIG. 21 is executed by a conventional VLIW method;

FIG. 23 is a view for explaining a case where the instruction sequence of FIG. 21 is executed by a dynamic VLIW method;

FIG. 24 is a diagram for explaining a dependency relationship between instructions;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Analysis part 2 ... Optimization part 3 ... Output part 21 ... Instruction scheduling part 22 ... Register allocation part 1002-1, 1002-2 ... Pending queue (P
Ending Queue) 1004 ... Scoreboard 1006-1, 1006-2 ... Pipeline unit

Claims (9)

[Claims] A processor having a plurality of arithmetic units capable of executing instructions in parallel and having a function of enabling execution of an instruction following in an instruction arrangement order to be started before execution of an instruction preceding it. A compiling method for generating an object program executable by the processor based on a given source program as an object, comprising: an analyzing step of analyzing the source program to generate a first intermediate code; An instruction scheduling step of performing instruction scheduling based on the intermediate code of, assigning a virtual register as a register for storing a temporary result of an operation, and generating a second intermediate code which is described; and Based on the information about the real registers of the processor, each of the virtual registers A register allocating step of determining a real register to be allocated to the virtual register, and an output step of outputting an object program in which the virtual register is replaced with the allocated real register. Analyzing the section used by being assigned to the virtual register and the section used by the virtual register to which the real register is assigned; and showing the section analysis result and the inter-instruction dependency that has already occurred. Based on the information, if there is a real register that does not cause a new inter-instruction dependency even if the real register is allocated to the allocation target virtual register, the real register is determined as a candidate to be preferentially allocated to the virtual register. And a compiling method. 2. A real register which does not cause a new inter-instruction dependency even when assigned to the allocation-target virtual register, actually causes a redundant inter-instruction dependency, The allocation priority of real registers that can be regarded as not causing a new inter-instruction dependency as a result of the relationship being hidden by the already existing inter-instruction dependency actually causes a redundant inter-instruction dependency. 2. The compiling method according to claim 1, wherein the priority is set higher than the real register allocation priority such that no new instruction-to-instruction dependency is caused by not performing the instruction. 3. The register allocating step includes, among the registers other than the real registers that do not cause the new dependency, real registers whose instruction arrangement order and instruction execution start order can be exchanged with each other. 2. The compiling method according to claim 1, further comprising the step of determining as a candidate to be assigned to a real register that does not cause a dependency in the next priority. 4. A real register whose allocation is determined at the time and a live range of the virtual register to be allocated among the real registers in which the instruction arrangement order and the instruction execution start order can be exchanged. 4. The compiling method according to claim 3, wherein a real register having a larger distance from a live range of the real register is determined as a candidate to be assigned with a higher priority. 5. The compiling method according to claim 3, wherein an actual register having a smaller critical path length in the inter-instruction dependency relationship is determined as a candidate to be assigned with a higher priority. 6. The virtual register to which a real register is to be allocated, based on a number of other virtual registers having a portion overlapping a live range of the virtual register and a number of real registers of the processor. 6. The compiling method according to claim 1, further comprising a step of determining an order of the compilation. 7. The register allocating step selects a real register having the highest priority among real registers determined for the virtual register to be allocated and which can be actually allocated at that time. 7. The compiling method according to claim 1, further comprising the step of storing a correspondence between the virtual register and the selected real register. 8. A processor having a plurality of arithmetic units capable of executing instructions in parallel and having a function of enabling execution of an instruction following in an instruction arrangement order to be started before execution of an instruction preceding it. A compiling device for generating an object program executable by the processor based on a given source program as an object, wherein the analyzing unit analyzes the source program to generate a first intermediate code; Instruction scheduling means for performing instruction scheduling based on the intermediate code, assigning a virtual register as a register for storing a temporary result of the operation, and generating a second intermediate code described therein; Each of the virtual registers is assigned based on information on the real registers of the processor. Register allocating means for determining a real register to be assigned; and output means for outputting an object program in which the virtual register has been replaced with the real register to which the virtual register has been allocated. Means for analyzing a section used by being allocated to the virtual register and a section used by the virtual register to which the real register is allocated; and information indicating the section analysis result and the inter-instruction dependency already occurring. Means for, if there is a real register that does not cause a new inter-instruction dependency even if it is allocated to the virtual register to be allocated, the real register is preferentially determined as a candidate to be allocated to the virtual register; A compiling device comprising: 9. A processor having a plurality of arithmetic units capable of executing instructions in parallel and having a function of enabling execution of an instruction following an instruction in the instruction arrangement order to be started before execution of an instruction preceding the instruction. In order to generate an object program executable by the processor based on a given source program as a target, the source program is analyzed to generate a first intermediate code, and the first intermediate code is analyzed. A virtual intermediate register is allocated and described as a register for storing a temporary result of an operation, and a second intermediate code is generated based on the instruction scheduling based on the second intermediate code and information on a real register of the processor. Register allocation for determining the real register to be allocated to each virtual register. And outputting an object program in which the virtual register is replaced with the real register to which the virtual register is assigned.The real register is assigned to the virtual register in the register assigning step. Analyzing the used section and the used section of the virtual register to which the real register is to be assigned, the allocation target is determined based on the section analysis result and the information indicating the inter-instruction dependency already occurring. If there is a real register that does not cause a new inter-instruction dependency even if it is assigned to the virtual register, a computer-readable recording of a program for causing the real register to be preferentially determined as a candidate to be assigned to the virtual register Possible recording medium.