JP3311381B2 - Instruction scheduling method in compiler - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction scheduling method in a compiler capable of generating an object program having good execution performance for a program operating on a computer having a plurality of arithmetic units.

Recently, so-called super color calculators and V
Processors that can execute instructions by simultaneously operating a plurality of arithmetic units, such as LIW computers, have begun to be used. Effective use of the hardware resources of these computers,
In order to improve the execution performance of a program, it is necessary to appropriately perform instruction scheduling and register allocation in a compiler.

[0003]

2. Description of the Related Art Instruction scheduling is one of optimization techniques in a compiler for reducing hardware delay by rearranging instructions. In particular, in hardware using a parallel RISC processor that can execute a plurality of processing units at the same time, this instruction scheduling technique is a technique called parallel instruction scheduling that rearranges instructions so that as many processing units as possible can be used simultaneously. is there.

In this parallel instruction scheduling, a plurality of instructions which do not have a conflict between data and arithmetic units are searched, and the instructions are rearranged so as to execute them simultaneously. Therefore, in order to make the instruction scheduling effective, it is necessary to separately allocate hardware resources such as registers and arithmetic units to each instruction.

[0005] Register allocation is also an important compiler optimization technique that exists from the beginning. Generally, the technique of register allocation deals with the problem of how to effectively use registers having a finite number. Therefore, processing has been carried out with a policy of sharing resources as much as possible.
This is, for example, when there are different data A and B,
When the live ranges of A and B do not overlap, the same register is assigned to these two.

Although both parallel instruction scheduling and register allocation are useful optimization techniques in compilers, they are intended to be mutually exclusive from the viewpoint of register use. This is because, from the viewpoint of parallel instruction scheduling, registers used for each instruction are mutually independent as much as possible, that is, it is desirable to allocate different registers as much as possible, whereas from the viewpoint of register allocation, This is because it is desirable to allocate the same register to each instruction as much as possible.

However, in a conventional compiler that supports both instruction scheduling and register allocation, the instruction scheduling phase and the register allocation phase are generally independent, and the operation enters the register allocation phase after the instruction scheduling phase ends. Alternatively, it has been considered that the instruction allocation phase is started after the register allocation phase is completed.

[0008]

As described above, instruction scheduling and register allocation have the following problems depending on the order in which they are applied due to the difference between the two purposes. Had been the problem above.

1) When Instruction Scheduling is Performed Prior to Register Allocation In order to enhance the effect of instruction scheduling, data renaming is frequently performed. Each instruction is executed without considering the register live range. Move instructions.

This code is the best if the actual registers are allocated for all data. However, since the number of registers is finite,
In some cases, the number of registers may be insufficient. In this case, in the register allocation phase, it is necessary to issue a spill code, which is an instruction for saving the register value, which degrades the performance. Further, since this spill code is not subject to instruction scheduling, use of the arithmetic unit may be wasted, resulting in poor execution performance.

Note that data renaming is an optimization technique often used in instruction scheduling and refers to the following processing. For example,
Consider the intermediate text strings (a) to (d).

(A) A = B + C A = B + C (b) D = A + E → D = A + E (c) A = FG (renaming) X = FG (d) H = IA H = I− X At this time, changing the variable A of (c) to X and replacing all the variables A after (c) with X (in this case, existing in (d)) is called renaming.

By performing renaming,
In (a) and (c), there is no data dependency, and the two can be executed in parallel. 2) When instruction scheduling is performed after register allocation In this case, the same register may be allocated to two data that can be executed in parallel by register allocation. In parallel. Therefore, the effect of instruction scheduling is reduced.

To deal with such a problem, there are presently processing systems which attempt to allocate registers while paying attention to parallelism as much as possible at the time of register allocation. Since the parallelism that is possessed is not considered, it is not enough for processing.

An object of the present invention is to solve the above-mentioned problems, to balance instruction scheduling giving priority to parallelism and register allocation to reduce the number of registers, and to enable generation of object code with high execution efficiency. I have.

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 10 is a source program to be compiled, 11 is a compile processing device on which a compiler operates, 12 is a front end that inputs the source program 10, performs syntax analysis and semantic analysis, and outputs the result as intermediate text. Processing phase, 13
Is an optimization processing phase for performing general optimization on intermediate text; 14 is an instruction scheduling / register allocation phase according to the present invention; 15 is an instruction output phase for outputting instructions of an object program; and 16 is an object program obtained as a result of compilation. Represent.

In the present invention, when compiling a source program 10 to be operated on a computer having a plurality of arithmetic units each of which can operate in parallel, the arrangement order of instructions is determined based on the optimized intermediate text. The instruction scheduling to be determined and the register allocation to determine the registers to be used for each instruction are executed in the same instruction scheduling / register allocation phase 14.

In the processing of the instruction scheduling / register allocating phase 14, a parallelism priority scheduling means 14-2 and a scheduling means 14-3 for reducing the number of simultaneously active registers are provided. Switch by 1.
In other words, by analyzing the intermediate text and comparing the estimated number of registers used with the number of registers that can be actually used, instruction scheduling that enhances the parallelism related to the use of multiple arithmetic units is performed, or the number of simultaneously active registers is reduced. Whether to perform instruction scheduling,
By switching, it is possible to output an object code that effectively utilizes a plurality of arithmetic units and registers.

In the case where the number of registers to be allocated is insufficient even after instructions are rearranged, the spill code insertion means 1
According to 4-4, a spill code as an instruction to save the contents of the register to another location is inserted, and the spill code is also subjected to instruction scheduling.

[0020]

The problems pointed out in the description of the prior art are caused by the following. -Information transmission of hardware resources (registers, arithmetic units) used between register allocation and instruction scheduling has not been successfully performed.

In the conventional instruction scheduling, instructions are moved only by a policy of increasing their parallelism, and the concept of register live range is not provided. The present invention performs the following processing to improve these two disadvantages.

A) Instruction scheduling and register allocation are performed at the same time (instruction scheduling is performed with reference to the state of use of registers). b) As an instruction scheduling method, there are two types of means, a means for increasing the parallelism and a means for reducing the register live range, and these are used properly by comparing the number of registers that can be used with the actually required number of registers.

C) When it is necessary to output a spill code, the spill code is also subjected to scheduling. With the above-described processing method, it is possible to increase the parallelism of execution by the arithmetic unit while using the available registers to the maximum extent, and to reduce the execution time of the compiled object program 16. In particular, even when the number of registers that can be actually used is insufficient by scheduling spill code,
It is possible to eliminate useless use of hardware resources (registers, arithmetic units).

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, first,
A description will be given of terms related to the description.

[Explanation of Terms] (1) Live Range The live range is a range in which the contents of data are valid.

The range from an instruction that defines the value of a register or a variable (an instruction for writing a value) to an instruction that last uses the value. For example, assume that there is an instruction sequence in assembler notation as shown in FIG. In this assembler notation, the final operand is the object to be defined. The instruction of
This is an instruction to load the variable X on the memory into the register R1, and defines the value of R1. Instruction in register R
This is an instruction to add the value of 1 to the value of the register R2 and set the value in the register R3. This instruction refers to the value of the register R1. Is a subtraction instruction, which refers to the value of the register R1. Is assigning the new value of the variable Y to the register R1.

Therefore, the last use of the value defined by is the instruction of, and the register live range for R1 is the range from. (2) Basic block Control is given to the first instruction (intermediate text), and then a block consisting of a sequence of instructions (intermediate text) that does not branch or stop halfway is a basic block. That.

(3) Entrance busy Generally, when control is passed to the basic block, data that is valid (has a value already set) is referred to as entrance busy data.

In the present invention, a plurality of basic blocks are defined as one scheduling range. Therefore, in this definition, "basic block" may be replaced with "scheduling range" (the same applies hereinafter).

(4) Exit Busy In general, when data of a basic block being processed is referred to by another basic block (in the present invention, a scheduling range), this data is said to be exit busy data.

(5) IP IP is an abbreviation of Immediate Predecessor. When considering the flow of a program, a block that may transfer control directly to a certain basic block A is called a basic block A.
Called IP.

For example, when there is a control flow (control flow) as shown in FIG. 3A, each IP becomes as shown in FIG. That is, there is no IP of the basic block A, and the IPs of the basic blocks B and C.
Is A, and the IPs of the basic block D are B and C.

(6) Global Data Global data is defined and defined over a plurality of basic blocks (in the present invention, a plurality of scheduling ranges).
Refers to the data being referenced.

(7) Dependency There are an instruction A and an instruction B. If the instruction B refers to the execution result of the instruction A, the instruction B must wait for the execution of the instruction A (or be executed after execution). Cannot be executed. When one of the instructions is affected by one of them, it is said that both have "dependency".

(8) Simultaneously Active (Register) When the clock number is an arbitrary number t, a register in which data is valid (t is included in the live range) is said to be simultaneously active.

The description of the phrase has been completed. The following technologies used in the embodiments of the present invention will be collectively described as technical descriptions 1 and 2 at the end of the description of the embodiments. [Technical Description 1] A method of instruction scheduling that reduces simultaneous activation of register live. [Technical explanation 2] Insertion procedure of spill code.

FIG. 4 shows a processing flow of the instruction scheduling / register allocating phase according to the embodiment of the present invention. In the instruction scheduling / register allocating phase 14 shown in FIG. 1, for example, processing 1) to FIG.
Perform 5). The processing in the other phases may be the same as that of the conventional technique, and is a well-known technique, and thus detailed description thereof will be omitted. Hereinafter, processing 1) to FIG.
This will be described according to 5).

1) [Entry busy (refer to the above explanation of words and phrases)
Setting of Information] This scheduling is performed for one scheduling range. The scheduling range is usually a basic block (see description of phrase). However, it is also conceivable that the scheduling range is expanded by global scheduling or the like. It is not essential for this method whether the scheduling range is a basic block.

FIG. 5 is an explanatory diagram of a data structure showing the correspondence between global data (see description of words and phrases) and registers. For each entry and exit of each scheduling range,
Correspondence information between global data and register numbers to which the data is assigned is queue-managed in a data structure as shown in FIG. Information between scheduling ranges (which global data is reserved in which register) is propagated using the data structure shown in FIG.

Information such as whether or not certain data is global data can be obtained by using data flow analysis of a normal compiler. Here, information setting means the following processing.

A) A virtual register (temporary) is prepared for data that is busy at the entrance. Note that this is treated as if the register has already been used.
This is reflected in the initial value of a variable for remembering the number of registers described in Technical Description 1 described later.

B) The information (relationship between data and register number) of the IP (see the description of words and phrases) in this scheduling range is fetched and stored in a data structure as shown in FIG. This is used at the time of register allocation described later.

2) [Creation of DAG] Using one intermediate text as a node, DAG (Directed
Create Acyclic Graph).

DAG is a graph showing the executable order of instructions having the contents shown in FIG. 6 (B) when there is an intermediate text instruction sequence as shown in FIG. 6 (A). is there. Since the instruction refers to the value of t4 defined by the instruction, it cannot be executed until after the execution of the instruction. Similarly, the instruction is an instruction, t defined by the instruction.
Since the values of 2 and t6 are referred to, they cannot be executed unless the instruction and the instruction have been executed.

The detailed contents of the DAG and the method of creating the DAG are described in well-known techniques (for example, co-authored by Aho Sesi Ullman, translated by Harada, "Compiler II-Principles, Techniques,
Tool ”in Chapter 9).

At this time, the definition and reference relationship of the operands between the instructions are held in a data structure as shown in FIG. That is, as shown in FIG. 7, for each identifier id of a virtual register (temporary), a definition (DEF) and a reference (US
The list in E) is managed by a chain. The definition field indicates a DAG node, and the reference field indicates a list of node and clock information. This is used for the scheduling described below.

3) [Instruction Scheduling] In the instruction scheduling, the following steps 3-1) to 3-4) are executed for each node of the DAG.

During this instruction scheduling, the status of register use (register live range) is always grasped. Processing is divided into the following three cases depending on the balance between the register live range and the number of registers that can be used at that time.

Case 1: There are enough registers. Instructions can be scheduled ignoring register usage. Case 2: The number of registers used may exceed the number of available registers depending on the instruction arrangement. Therefore, instructions must be placed with the number of registers in mind.

Case 3: In order to arrange instructions, it is necessary to output a spill code because the number of registers is absolutely insufficient. The above cases are classified by comparing the increase / decrease value of the register live range when each instruction is executed with the registers available in each scheduling range.

The flow of the instruction scheduling process will be described. 3-1) Candidate determination A candidate for scheduling is searched from the DAG.

The scheduling candidate is a DAG
There is no parent (preceding one) or the parent has already been processed. The scheduling candidates are arranged in the scheduling candidate list in the order of priority.

The following 3-2) to 3-4) are applied to the nodes on the above list of scheduling candidates. 3-2) Determining arithmetic units In an architecture with multiple arithmetic units, the operations that can be performed are determined by instructions. this is,
It can be found by creating a table with each instruction as an index.

3-3) Finding the execution time τ of the instruction The execution time τ of the instruction n is obtained by the following steps. a) The number of clocks t at the time of scheduling is obtained by ignoring the number of registers n.

This utilizes a conventional technique that focuses on the dependency of n and the way in which a computing unit is used. However, here, the location of the instruction n is not determined. Here, the location of the instruction n is represented by a computing unit and the number of clocks t at which the computing unit is executed (estimated).

B) For t obtained in step a), the number of registers active at that time is calculated. The estimated usage of the number of registers can be calculated as follows.

Estimation of use of register number (t, n) = current register use number (t) + increase / decrease of register number by instruction (n) Here, increase / decrease of register number by instruction (n) corresponds to instruction n
When there is register data (rl, ..., rn) defined and referenced by

Increase / decrease in the number of registers (n) = Σ (if (ri == definition) +1 else if (ri == referenced and ri does not appear thereafter) −1 else 0) (where Σ is from i = 1 Here, the definition and reference of each register (and the number of references)
Can be calculated when the DAG is generated, so it is necessary to remember this. For this, the data structure of FIG. 7 can be used.

C) If the use estimate (t, n) of the number of registers obtained in the process b) is smaller than the allowable number of registers, it is determined that the instruction n is arranged at the position of the clock t.

D) When the use estimate (t, n) of the number of registers obtained in the process b) is larger than the allowable number of registers, the instruction n cannot be arranged at the position of the clock t. Therefore, simultaneous active (refer to the phrase explanation)
Instruction scheduling is required to reduce the number of registers.

The following method can be considered as a process in such a case. A) Start from 3-2) for the next candidate n '. B) For the instruction n, find t 'that satisfies the above condition c). The procedure at that time will be described in Technical Description 1 described later.

C) The above a) and b) are combined. In this embodiment, c) is adopted. That is, if there is an instruction that does not increase the number of registers used, such as a store instruction, among the candidates, a)
Apply If there is no such instruction, a) shall apply.

E) In the process d), there is a case where an appropriate t 'cannot be found for the instruction n. In this case, the number of registers is insufficient. In such a case, a spill code is required.

The processing procedure for inserting the spill code is as follows.
This will be described later as Technical Description 2. As a result, the spill code is scheduled in the same manner as a normal instruction.

3-4) Data Registration When the arithmetic unit for executing the instruction n and the number of clocks t for executing the same are obtained, the information is registered.

Here, the data to be registered is the following 3
Seed data. -Data indicating the usage status of the arithmetic unit for each clock for each arithmetic unit. This is represented by a data structure as shown in FIG. That is, each operating unit has a chain 80 in use and a clearance chain 81, and the chain 80 in use
The information of each instruction node to which the use time of the computing unit is assigned is managed, and the gap chain 81 manages the clocks in which the computing unit is idle and the length thereof.

Data for remembering how many registers are in use (active) for each clock for each register type. This will be described later in Technical Description 1.

-The relationship between the definition command and the reference command for each data. In this registration, when generating the DAG described in 2),
Since a table as shown in FIG. 7 is prepared, each instruction linked to this chain is marked as to whether or not it has been scheduled (the number of clocks assigned to the arithmetic unit Clock).
Attached.

Thus, it can be determined which data is active at which time. 4) [Register allocation] By the procedure up to the above 3) (particularly according to 3-3 e)), the situation where the register is insufficient for the data to be loaded in the register is eliminated.

Therefore, the register allocation here can be realized by the conventional local register allocation processing without outputting the spill code. 5) [Processing of Exit Busy (Refer to Phrase Description) Information] The information is transmitted to the next scheduling range. This information indicates the correspondence of which register is allocated to the exit busy data.

In this processing, the result of register allocation for the data of the exit busy is stored in the exit busy portion of the data structure as shown in FIG. Next, examples of specific processing results according to the embodiment of the present invention will be described with reference to FIGS.
Explanation will be made according to 2.

Here, a machine having the following functions is assumed as a computer on which the object program operates. However, the present invention is not limited to such a computer.

Three operations can be executed simultaneously by one instruction. -This machine has 2 integer operation units * 1 floating point operation unit * 1. Although the memory operation is performed by the integer operation unit, only one memory operation can be performed in one instruction.

The multiplication is performed by the floating-point operation unit. -Instructions are described as follows. load R1,0, R2: add R3, R4, R5: mul R6, R7, R8 st R8, R1,4: sub R5, R0, R0 bne label1 Here, one instruction is represented by one line, and each operation is They are separated by “:”. If there are only two or less operations in one instruction, the remaining part is NO
It is interpreted that P (No Operation) is inserted.

-Instructions are executed line by line, and the next instruction cannot be executed unless the previous instruction is completed. -The load and st instructions take 2τ to execute, and the add and
The sub and mul instructions take 4τ to execute.

The intermediate text optimized by the optimization processing phase 13 shown in FIG. 1 is a sequence of instructions (operations) as shown in FIG. 9 (a). Assumed to be performed.

In the intermediate text, t1 to t11 represent virtual registers, that is, registers temporarily allocated as long as the number of registers is not limited. In this scheduling range, t1, t3, and t5 are:
It is assumed that there is an entrance busy and an exit busy.

Since the number of integer operation units is 2 and the number of floating-point operation units is 1, integer operations (load / store), multiplication, and addition can be performed simultaneously unless there is a conflict between registers and the like.

The instruction of the intermediate text shown in FIG.
As shown in FIG. 10, (1) to (10) are converted to respective times (time-1 to ti).
me-22), the live ranges of the registers t1 to t11 are as shown in FIG.

Here, the maximum number of simultaneously active registers is eight from time-9 to time-10. Therefore, when there are eight or more registers that can be used, scheduling can be performed without being affected by the number of registers. As a result, an instruction sequence that can be output as an object program is as shown in FIG. 9B, and the execution time of this instruction sequence is 22τ.

Here, it is assumed that there are only seven registers that can be used temporarily. In the conventional method, for example, register allocation is performed after instruction scheduling is completed, and a spill code (instruction to save the register value) is output when the register becomes insufficient.

Therefore, an instruction sequence based on a conventional processing result is as shown in FIG. In FIG. 11A, an instruction (4) is a spill store instruction for saving the contents of the register R5 to a work area MEM in the memory, and an instruction (7) is an instruction for storing the contents of the register R5 in the work area MEM of the memory.
This is a spill load instruction to restore from.

When the relationship between the register live range and the execution time at this time is examined, it becomes as shown in FIG. 11 (b). As is clear from the register usage shown by the solid line in FIG. The execution time of the instruction sequence shown in (a) is 28τ.

On the other hand, in the present invention, as described above, instruction scheduling and register allocation are performed in the same phase, and when the number of available registers is seven and is smaller than the initial estimate, a spill code is output as much as possible. Scheduling is performed so that instructions are not rearranged.

As a result, the instruction sequence output according to the present invention is, for example, as shown in FIG. The relationship between the register live range and the execution time at this time is shown in FIG. As is apparent from this figure, the execution time of the instruction sequence shown in FIG.

Therefore, it can be seen that this instruction sequence is executed at a higher speed than the instruction sequence for issuing the spill code shown in FIG. [Technical Description 1] A method of instruction scheduling that reduces simultaneous activation of register live.

The following variables are used. char Num-of-Live-reg [2] [N]; For each clock number 0, 1, 2,.
This is an array for storing the number of active general-purpose registers and floating-point registers.

For example, Num-of-Live-reg [0] [10]
Stores the number of (active) general-purpose registers used at clock 10. Where N
Is the final value of the number of clocks, but N does not always need to be an accurate value, and may be estimated to be relatively large. Also, since this value can be used to determine the number of instructions while creating a DAG,
You can estimate based on that. Here, there are two types of registers, a general-purpose register and a floating-point register, but the types can be increased depending on the processing system and hardware.

The procedure of the instruction scheduling is as follows.
It looks like this: (3-3) d) Continuation from d) a) 3-3) From T (the number of clocks obtained by the conventional scheduling method) obtained in a), TT (currently , The number of registers is estimated for each clock.

If the estimated number of registers is smaller than the allowable number of registers, t at that time is calculated as t
It is. If such t is not found, it indicates that scheduling for reducing the live range of the register has not been performed for the target instruction n.

When the above flow is written in a pseudo program,
It looks like this: LOOP from t = T: to t = TT; 使用 Estimated use of register number (t, n) = Num-of-Live-reg [I] [N] + increase / decrease of register number (n); Estimated use <the number of available registers) return t;｝ return not found; Here, I is a number corresponding to the type of register to be used, which is determined by the instruction n. [Technical explanation 2] Insertion procedure of spill code.

The spill code is an instruction generated when there is no register to be assigned to data requiring a register. The spill code is
In most cases, it is composed of the following two.

1) By issuing an instruction (herein referred to as a store instruction) for saving the contents of a register to another location (memory or another type of register), the register can be used. To do.

2) When the saved data is used, an instruction to be brought into the register (herein referred to as a load instruction) is issued from the location saved in 1).

In this method, the spill code is output in the following procedure. 1) Selection of data to be spilled The problem of which register contents to store is important, and this is being studied by existing compilers. However, since it is not directly related to the gist of the present invention, here, data to be spilled by the same procedure as that of the conventional compiler is selected.

2) Processing of store and load instructions a) DAG nodes corresponding to store and load instructions are created. B) The DAG node corresponding to the store instruction is inserted at the position of the parent (previously executed) DAG of the instruction n requiring spill.

The DAG node corresponding to the load instruction inserts the data saved by the store instruction into the position of the parent of the instruction actually used and the child of the instruction n requiring spill.

3) Update the data definition / use information. As described above, the spill code can be incorporated into the scheduling procedure and processed in the same manner as a normal instruction.

[0099]

As described above, according to the present invention,
It is possible to output efficient code that balances instruction scheduling and register allocation. Since instruction scheduling is performed in consideration of the live range of the register, the occurrence of spill code can be reduced. Also, even if a spill code occurs,
Since those codes are subjected to instruction scheduling, the spill code is parallelized with other operation codes, so that the operation unit can be effectively used.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a live range for explaining an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an IP for describing an embodiment of the present invention.

FIG. 4 shows an instruction scheduling method according to an embodiment of the present invention.
FIG. 9 is a diagram showing a flow of processing in a register allocation phase.

FIG. 5 is an explanatory diagram of a data structure representing a correspondence between global data and a register used in the embodiment of the present invention.

FIG. 6 is an explanatory diagram of a DAG used in the embodiment of the present invention.

FIG. 7 is an explanatory diagram of a data structure for representing a definition / use chain of each data used in the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a data structure representing a use state of a computing unit used in the embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a processing result according to the embodiment of the present invention.

FIG. 10 is a diagram showing a register live range according to a processing result of the embodiment shown in FIG. 9;

FIG. 11 is a diagram illustrating an example of a processing result according to the related art for comparison with a processing result according to the embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a processing result according to the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Source program 11 Compile processing unit 12 Front-end processing phase 13 Optimization processing phase 14 Instruction scheduling / register allocation phase 14-1 Register use status inspection means 14-2 Parallelism priority scheduling means 14-3 The number of simultaneously active registers Scheduling means for reducing 14-4 Spill code inserting means 15 Instruction output phase 16 Object program

────────────────────────────────────────────────── (7) Continuation of the front page (72) Inventor: Manabu Matsuyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-3-150637 (JP, A) R. Goodman et al., Code Scheduling and Register Allocation in Large Basic Blocks, International Conference on Supercomputing, 1988, p. 442 −452 (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/38 G06F 9/45

Claims (2)

(57) [Claims] 1. A processing method for compiling a program to be executed on a computer having a plurality of arithmetic units, each of which can operate in parallel, comprising: an instruction scheduling for determining an instruction arrangement order; and a register for determining a register used by each instruction. Performing the allocation in the same phase and increasing the parallelism regarding the use of the plurality of arithmetic units, and the instruction scheduling reducing the simultaneous activation of the registers. for switching by collating a certain instruction n ignoring register number schedule
Of registers that can be used for register estimation
If the value is greater than
Search for the instruction n ', and if the candidate is found,
Performs scheduling processing for the candidate
Is not found, the instruction n is stored in the register
Number usage estimate is less than available registers
At the same time
An instruction scheduling method in a compiler, which performs instruction scheduling to reduce the number of instructions . 2. The method according to claim 1, wherein when the number of registers to be allocated is insufficient even if the instructions are rearranged, a spill code which is an instruction to save the contents of the registers to another location is inserted. And a spill code for the instruction scheduling.