JP2006285761A - Integrated circuit, microcomputer and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the current consumption of a memory without deteriorating a function in an integrated circuit containing a CPU performing the access of a built-in memory. <P>SOLUTION: This integrated circuit device 10 comprises a CPU 20, a memory 30, a memory interface circuit 40, and a memory data bus having a bus width larger than the request data width of the CPU. The memory interface circuit 40 reads, based on a request address, data for the bus width of the memory data bus larger than the request data width of the CPU, holds the read data in the request data width units of the CPU so as to be freely fetched, outputs the data held in a data holding circuit when data of the request address from the CPU are held in the data holding circuit, and generates and outputs, in a cycle where no access to the memory according to the request address from the CPU is performed, a low-power control signal for stopping the clock of the memory or reducing the power thereof. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, a microcomputer, and an electronic device.

  In the CPU and microcomputer, access to the built-in RAM and the like frequently occurs with programs, data, and the like. This RAM has become a larger size than the year, and the ratio of the consumption current of the RAM to the consumption current of the chip is increasing.

  In general, when a RAM is attached to a 32-bit CPU, the instruction length is set to 32 bits, the data length is set to 32 bits, and the 32-bit data is designed to be continuously read / written once per clock.

For example, in a 32-bit RISC CPU having a 0.18 um process, a current consumption of 0.2 mA / MHz flows in the logic unit, which corresponds to half of the current consumption of the entire chip.
Japanese Patent Application Laid-Open No. 2004-287761 JP 2003-256068 A

  The present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the current consumption of a memory without degrading the function in an integrated circuit device with a built-in CPU that accesses the built-in memory.

(1) The present invention
An integrated circuit device comprising:
CPU,
Memory,
A memory interface circuit that receives a CPU request address, reads data in the memory based on the request address, and outputs data corresponding to the CPU request address to the CPU;
A memory data bus connected to the memory and the memory interface circuit and having a bus width larger than a requested data width of the CPU;
A CPU data bus connected to the CPU and a memory interface circuit;
The memory interface circuit includes:
A data read circuit for reading out data corresponding to the bus width of the memory data bus larger than the requested data width of the CPU from the memory via the memory data bus based on the requested address received from the CPU;
A data holding circuit for holding the read data so that it can be taken out in units of CPU request data width;
It is determined whether or not the data of the CPU request address is held in the data holding circuit, and if it is held, the memory is not accessed in accordance with the CPU request address and held in the data holding circuit. An output circuit that outputs data corresponding to the CPU request address to the CPU via the CPU data bus, and a cycle in which the memory is not accessed according to the CPU request address stops the memory clock or has low power. A low power control signal generation circuit that generates and outputs a low power control signal for
It is characterized by including.

  The memory is a memory built in the integrated circuit device, and may be SRAM, ROM, flash memory, or DRAM.

  The CPU data bus may have the same bus width as the requested data width of the CPU.

  When data corresponding to the bus width of the memory data bus is read from the memory via the memory data bus based on the request address received from the CPU, an actual read address is generated based on the request address received from the CPU. To access. At this time, for example, when the bus width of the memory data bus is 2 to the nth power of the request bus width of the CPU, the read address may be generated excluding the lower n bits of the CPU request address.

  The data holding circuit that can hold the data in units of CPU requested data width is, for example, a required number of Philip flops that can store data of CPU requested data width (| (data width of memory data bus / CPU requested data). It can be realized by providing width) +1 |).

  The data holding circuit may be provided with a necessary number of Philip flops capable of storing data having a data width required by the CPU, for example, and the read data may be temporarily stored in the Philip flop.

  In addition, a Philip flop corresponding only to the data of the pre-read portion among the read data may be provided, and only the data of the pre-read portion may be stored in the Philip flop. The pre-read portion is a data portion other than the CPU requested data width in the data read from the CPU data bus. In this case, of the read data, the data corresponding to the CPU request address is output as it is to the CPU data bus.

  If the data of the CPU request address is not held in the data holding circuit, the bus width of the memory data bus larger than the CPU request data width from the memory via the memory data bus based on the CPU request address The process of reading the minute data is performed.

  To make the memory low power means to reduce the current consumption value in the memory.

  The integrated circuit device includes a circuit that stops or lowers the clock of the memory based on the low power control signal. However, this circuit may be provided with a dedicated circuit, for example, a general-purpose function provided in the memory. May be used to stop or reduce the memory clock based on the low power control signal.

  According to the present invention, the memory bus width (memory data bus width) is made larger than the CPU request data width, and the excess data read from the memory is held as pre-read data, and the next request address of the CPU is stored. If there is a match, the stored data is passed to the CPU. Therefore, when data at the next request address of the CPU is held (when the CPU requests data at consecutive addresses), it is possible to omit access for memory packing. During that time (cycle in which the memory is not accessed according to the requested address of the CPU), a low power control signal is generated and output to stop or reduce the power of the memory clock. Can be.

  As described above, according to the present invention, the frequency of memory access can be lowered, and the process of explicitly reducing the power during non-access (the process of stopping the supply of the clock to the memory or the process of reducing the current consumption in the memory) ), The power consumption of the memory portion in the integrated circuit device can be reduced, and a low-power integrated circuit device (IC) can be created.

(2) The integrated circuit device of the present invention is
The memory is
Input the low power control signal from the chip select terminal,
A low power control circuit is included for controlling the clock in the memory to stop or reduce current consumption based on the low power control signal.

  A low power control signal is connected to the chip select terminal of the memory.

  According to the present invention, even in an integrated circuit device having a memory having a function of controlling the inside of the memory to low power based on the chip select signal, the power consumption of the memory portion in the integrated circuit device can be reduced, and the low power An integrated circuit device (IC) can be created.

(3) The integrated circuit device of the present invention
In claim 1,
A clock control circuit for controlling a clock supplied to the memory based on the low power control signal;
The memory is
A clock signal controlled by a clock control circuit is input from a clock control terminal.

  According to the present invention, even in an integrated circuit device having a memory whose memory itself does not have a function of controlling the inside of the memory at low power, the power consumption of the memory unit in the integrated circuit device can be reduced by controlling the clock supplied to the memory. And a low power integrated circuit device (IC) can be created.

(4) The integrated circuit device of the present invention is
The memory data bus has a bus width that is a power of 2 times the data width required by the CPU.

(5) The integrated circuit device of the present invention is
The data holding circuit is
It is characterized in that only the prefetched portion of the read data is held so as to be able to be taken out in units of CPU requested data width.

  For example, a Philip flop corresponding only to the data of the pre-read portion of the read data may be provided and only the data of the pre-read portion may be stored in the Philip flop. The pre-read portion is a data portion other than the CPU requested data width in the data read from the CPU data bus. In this case, of the read data, the data corresponding to the CPU request address is output as it is to the CPU data bus.

  According to the present invention, since it is not necessary to provide a data holding circuit other than the prefetched portion, an increase in the circuit scale of the data holding circuit can be prevented.

(6) The integrated circuit device of the present invention is
The determination circuit includes:
An address holding circuit that holds an address corresponding to the upper bits common to the data address held in the data holding circuit among the CPU request addresses;
It is determined whether the address held in the address holding circuit matches the corresponding bit portion of the CPU request address, and based on the determination result, it is determined whether the data of the CPU request address is held in the data holding circuit. It is characterized by doing.

  According to the present invention, when the bus width of the memory data bus is 2 to the nth power of the required data width of the CPU, it is not necessary to hold n bits of lower bits, so that the circuit scale can be saved.

(7) The integrated circuit device of the present invention is
The memory interface circuit includes:
The present invention is characterized in that data corresponding to a CPU request address is returned in one clock cycle.

(8) The integrated circuit device of the present invention is
The memory interface circuit includes:
It is characterized in that data corresponding to the CPU request address is returned in a cycle of 2 clocks or more.

(9) The integrated circuit device of the present invention is
The CPU
Outputs the increment signal of the program counter,
The determination circuit of the memory interface circuit includes:
Based on the increment signal, it is determined whether data of a CPU request address is held in the data holding circuit.

  If there is no branch or jump, the program counter is sequentially incremented by the instruction code length. Therefore, when the increment signal indicates that the data is sequentially incremented, the CPU requests data at consecutive addresses, and therefore it is determined that the data at the requested address of the CPU is held in the data holding circuit. be able to.

(10) The present invention
A microcomputer including any one of the integrated circuit devices described above.

(11) The present invention
A microcomputer as described above;
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
It is an electronic device characterized by including.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

1. Note that the embodiment described below does not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

  FIG. 1 is a functional block diagram for explaining the configuration of the integrated circuit device of the present embodiment.

  The integrated circuit device 10 of this embodiment includes a CPU (processing circuit in a broad sense) 20, a memory 30, a memory interface circuit 40, a memory data bus 70, a CPU data bus 60, and an address bus 24.

  The CPU 20 outputs a chip select signal 22 and a request address 24 (16 bits of A0 to A15 here) to the memory interface circuit 40, and data (here, D0 to D31) corresponding to the request address 24 from the memory interface circuit 40. 32 bits) 60 is received.

  The chip select signal 22 is a signal that becomes Low active.

  The memory interface circuit 40 is configured to return data 60 corresponding to the request address 24 of the CPU 20 in a cycle of one clock.

  For example, the CPU reads out an instruction code stored in the memory 30 via the memory interface circuit 40 and executes a process of executing the read instruction.

  The memory 30 may be, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), an SRAM, a flash memory, or a DRAM, and stores data and instruction codes used by the CPU.

  The memory interface circuit 40 receives the chip select signal 22 and the request address 24 of the CPU 20, outputs a read address 90 to the memory based on the request address 24, reads the data 70 of the memory 30, and based on the read data. A process of outputting the data 60 of the request address of the CPU 20 to the CPU 20 is performed.

  The memory data bus 70 is connected to the memory 30 and the memory interface circuit 40 and has a bus width larger than the data width required by the CPU 20. Here, it has a data width of 64 bits which is a data width twice as large as 32 bits which is a required data width of the CPU 20.

  The CPU data bus 60 is connected to the CPU 20 and the memory interface circuit 40 and has a bus width (in this case, 32 bits) of the requested data width of the CPU 20. The CPU 10 is configured to handle 16-bit instruction codes while handling 32-bit data.

  The address bus 24 is connected to the CPU 20 and the memory interface circuit 40 and has a bus width (in this case, 32 bits) of the requested address width of the CPU 20. Although the CPU 10 handles a 32-bit width address, it is actually only 16 bits, so it is configured to process only the lower 16 bits.

  The memory interface circuit 40 generates read addresses (request addresses A1 to A15) based on the request address 24 received from the CPU 20, and transmits data corresponding to the bus width of the memory data bus 70 from the memory 30 via the memory data bus 70. A data read circuit for reading data (64-bit data), a data holding circuit 42 for holding the read (extra prefetched) data 70 so as to be able to be taken out in units of CPU request data width, and data at the CPU request address 24 are the data A determination circuit (comparator 47) for determining whether or not the data is held in the holding circuit 42, and, if held, data corresponding to the request address of the CPU held in the data holding circuit 42 is An output circuit for output to the CPU 20 via the bus 60 and data to the CPU 20 Low power that generates and outputs a low power control signal 54 for stopping or reducing the clock of the memory 30 during a period when the pre-read data held in the holding circuit 42 is passed and the memory 30 does not need to be accessed And a control signal generation circuit.

  In addition, the integrated circuit device 10 includes various types such as BCU (Bus Control Unit), MMU (Memory Management Unit), DMAC (Direct Memory Access Controller), LCD (Liquid Crystal Display) driver, or SIO (Serial Input Output). Peripheral circuitry can be included.

  In the present embodiment, a Philip flop FF capable of holding 32 bits of data is connected to 32 bits of data on the CPU data bus in order to hold the data in units required by the CPU (32 bits here). For example, a Philip flop FF that can hold 32-bit data may be connected to each of the read data 1 (32 bits from D0 to D31) and data 2 (32 bits from D32 to D63). Further, for example, as indicated by 24 in FIG. 1, only the prefetched portions (D32 to D61) of the read data (D0 to D61) may be held so as to be able to be taken out in units of the requested data width of the CPU. The read data 1 (32 bits from D0 to D31) may be read and output to the CPU data bus as it is. In this way, if the minimum required width (D0 to D31) of the memory data bus 70 is not held, an increase in the circuit scale of the memory interface circuit 40 can be prevented.

  FIG. 2 is a diagram for explaining an example of the determination circuit according to the present embodiment.

  As shown in FIG. 2, the determination circuit 50 includes a chip select signal 22 (Low active) from the CPU 20, a comparison result signal (matched by 1 and mismatched by 0) 48 output from the comparator 47, and the least significant address of the CPU request address. Based on these signals, bit A0 is input, and a chip select signal (low power control signal) 54, selection signal 45, and address / data holding signal 52 input to the memory are generated and output, and low power control is performed. It functions as a signal generation circuit.

  The determination circuit includes, for example, an AND circuit 81 and an OR circuit 83, the input of the AND circuit 81 is connected to A0 and the comparison result signal 48, and the output 82 of the AND circuit 81 and the chip select signal 22 are input to the OR circuit 83. The output of the OR circuit 83 may be used as the low power control signal 54.

  The output 82 of the AND circuit 81 becomes 1 when A0 is 1 (odd address) and the comparison result signal is 1 (match) (in this case, data corresponding to the CPU request address is held in the data holding circuit). . In this case, the output of the OR circuit 83 becomes 1 regardless of the value of the chip select signal 22, and the chip select signal 22 output from the CPU can be masked. In this way, when data corresponding to the CPU request address is held in the data holding circuit, data is not read from the memory, so that the memory is reduced in power by masking the chip select signal 22. be able to.

  The determination circuit 50 includes an inverting buffer (inverter and buffer) 84. The inversion buffer 84 receives the address / data holding signal 52 and outputs the inverted value as the address / data holding signal 52.

  When A0 is 0 (when the CPU request address is an even address), the address / data holding signal 52 becomes 1, and the data and address are held in the data holding circuit and the address holding circuit. When A0 is 1 (when the CPU request address is an odd address), the address / data holding signal 52 is 0, and no data or address is held in the data holding circuit and the address holding circuit.

  The determination circuit 50 includes an inversion buffer (inverter and buffer) 85. The inverting buffer 85 receives A0 and outputs the inverted value as the first selection signal 45-1. Therefore, when A0 = 0 (that is, when the CPU request data is an even address), the first selection signal 45-1 = 1 (H) and the selection circuit 41 selects data 72 (D0 to D31 of the memory data bus). To the CPU data bus.

  The determination circuit 50 includes an inverting buffer (inverter and buffer) 86 and an AND circuit 88. The inversion buffer 86 receives the comparison result signal 48 and outputs an inversion value 87 thereof. The AND circuit 88 receives the inverted value 87 and A0, and the output value becomes the second selection signal 45-2. Therefore, when A0 = 1 (that is, when the CPU request data is an odd address) and the comparison result does not match, the second selection signal 45-2 = 1 (H) and the selection circuit 41 receives the data 74 (memory data bus). D32 to D61) are selected and output to the CPU data bus.

  The determination circuit 50 includes an AND circuit 89. The AND circuit 89 inputs A0 and the comparison result signal 48, and the output value becomes the third selection signal 45-3. Therefore, when A0 = 1 (that is, when the CPU request data is an odd address) and the comparison result is the same, the third selection signal 45-3 = 1 (H), and the selection circuit 41 receives the data 76 (in the data holding circuit). The stored data is selected and output to the CPU data bus.

  The address / data holding signal 52 changes to a level (first level) at which address / data holding is performed when A0 of the request address 24 from the CPU is 0.

  The address holding circuit 46 is a Philip flop FF capable of holding an address for 15 bits, and its input is connected to the signal lines of the request addresses A1 to A15 of the address bus 24 of the CPU 20 and the address / data holding signal 52, and its output is compared. Connected to the device 47. The address holding circuit 46 holds the CPU request addresses A0 to A15 at the timing when the address / data holding signal 52 is at the first level.

  As shown in FIG. 1, among the addresses (A0 to A15) for reading data from the memory, the addresses corresponding to the upper bits (15 bits of A1 to A15) common to the data addresses held in the data holding circuit 42 are held. An address holding circuit 46 may be provided.

  As described above, the address holding circuit 46 has the number of bits corresponding to the power of 2 of the CPU data bus width (here, 32 bits × 2 to the power of 1), which is n when 32 bits × 2 is the nth power. It can be configured not to retain the lower bits.

  When the memory data bus has a data width twice as large as the CPU data bus as shown in FIG. 1, the timing at which the address is held in the FF of the address holding circuit 46 is the data of the even address (A0 = 0). Case). When the data width is 2 to the nth power, the request address is the 2nd power.

  The data holding circuit 42 is a Philip flop FF capable of holding 32 bits of data, and its input is connected to the signal lines of the data DA32 to D61 of the memory data bus 70 and the address / data holding signal 52, and its output is the selection circuit 41. It is connected to the. The data holding circuit 42 holds the data DA32 to D61 of the memory data bus 70 at the timing when the address / data holding signal 52 is at the first level.

  The comparator 47 inputs the address held in the address holding circuit 46 and the corresponding bits (15 bits A1 to A15) of the CPU request address 24, determines whether they match, and determines the comparison result signal 48 as a determination circuit. Output to 50. Based on the comparison result of the comparator 47, it can be determined whether or not the data of the CPU request address is held in the data holding circuit.

  The selection circuit (MUX) 41 inputs the data 72 of D0 to D31 of the memory data bus 70, the data 74 of D32 to D71 of the memory data bus 70, and the output data 76 of the data holding circuit 42, and the determination circuit 50 outputs them. Based on the selection signal 45, one of the data 72, 74, and 76 is selected and output to the CPU data bus 60.

  Here, if the least significant bit A0 = 0 of the request address, the data 72 is selectively output, and the least significant bit A0 = 1 of the request address holds the CPU request addresses A1 to A15 in the FF of the address holding circuit 46. If the address does not match (when the comparison result of the comparator 47 indicates a mismatch), the data 74 is selected and output, the least significant bit A0 = 1 of the request address, and the CPU request addresses A1 to A15 are the address holding circuit 46. The selection circuit (MUX) 41 is controlled by the selection signal 45 so that the data 76 is selected and output if the address held in the FF matches (if the comparison result of the comparator 47 indicates a match). .

  3 and 4 are flowcharts for explaining the processing of the memory interface circuit.

  When chip select ON and a request address are received from the CPU, the following processing is performed (step S10).

  When A0 = 0, which is the least significant bit of the request address 24 of the CPU (step S20), the request addresses A1 to A15 are held in the address holding circuit 46 (step S30), and from the memory 30 via the memory data bus 70. Data twice the request data (D0 to D61) is read (step S40), and the CPU request address data D0 to D31 are selected from the read data D0 to D61 and output to the CPU data bus (step S50). The pre-read data D32 to D61 are held in the data holding circuit 42 (step S60).

  When A0 = 1, which is the least significant bit of the CPU request address 24 (step S70), the comparator detects whether the request addresses A1 to A15 match the address holding circuit address (step S80). If they match (step S90), the data held in the FF of the data holding circuit 42 is output (step S100).

  If they do not match, the request addresses A1 to A15 of the CPU 20 are held in the address holding circuit 46 (step S110), and twice the requested data (D0 to D61) is received from the memory 30 via the memory data bus 70. Read (step S120), CPU requests address data D32 to D61 among the read data D0 to D61 are selected and output to the CPU data bus (step S130).

  The determination circuit 50 receives the chip select signal 22 from the CPU 20, the comparison result signal 48 output from the comparator 47, and the least significant bit A0 of the CPU request address, and the chip select signal input to the memory based on these signals. (Low power control signal) 52, selection signal 45, and address / data holding signal 52 are generated and output to function as a low power control signal generation circuit. The address / data holding signal 52 changes to a level (first level) at which address / data holding is performed when A0 of the request address 24 from the CPU is "0".

  FIG. 5 is a timing chart of the present embodiment.

  Reference numeral 12 denotes a clock.

Reference numeral 200 denotes various signals exchanged between the CPU and the memory interface.
A chip select signal 22 is output from the CPU to the memory interface. This is a Low active signal, and the CPU instructs reading of the memory at the L level. Reference numeral 24 denotes a request address output by the CPU. Reference numeral 60 denotes an instruction code (one instruction in 32 bits) that the CPU receives from the memory interface via the CPU data bus. Data is exchanged between the CPU and the memory interface every data 601 clock corresponding to the request address 24.

  Reference numeral 210 denotes various signals exchanged between the memory interface and the memory. A chip select signal (low power control signal) 54 is output from the memory interface to the memory. When the level is L, the memory is read. When the level is H, the memory is not read. Therefore, when the chip select signal (low power control signal) is at the H level, the memory is controlled to reduce the power. Reference numeral 90 denotes a read address output from the memory interface. In this embodiment, the read address is output only when the CPU request address is an even address. Therefore, the actual access to the built-in RAM is half the number of requests for the CPU request address. Reference numeral 70 denotes an instruction code (two instructions stored at a continuous address of 64 bits) received by the memory interface circuit from the memory through the first data data bus.

  In the present embodiment, the memory interface circuit accesses the memory when the requested address from the CPU is an even address, reads two consecutive instructions in one access (reading an even address), and reads prefetched data (next (Data at odd addresses) is held in the data holding circuit. When the next request address (reading of an odd address) is received from the CPU, if it is a continuous address, the data of the data holding circuit is transferred to the CPU. Accordingly, when the CPU request address is a continuous address as indicated by 230, the actual access may be performed once in two CPU request times.

  In this embodiment, since the memory data bus is twice the data width required by the CPU, the current consumption for reading is increased by approximately 30%. However, if one access is performed twice, the current consumption is 65% per cycle, and the power of the memory can be reduced.

  However, if the CPU request address is discontinuous as in 240, the data held in the data holding circuit may not be used every time access is made.

  FIG. 6 is a diagram for explaining an example of reducing the power of the memory.

  When the memory has a function of performing low power control based on the chip select signal, the low power control signal 54 output from the memory interface is not supplied to the chip select terminal 38 of the memory instead of the chip select signal 22 output from the CPU. Connecting. In this way, the memory 30 receives the low power control signal 54 as a chip select signal, and the built-in low power control circuit 32 is based on the low power control signal 54 so that the clock stoppage or current consumption in the memory is reduced. To control.

  The low power control signal (chip select signal) 54 is a signal for instructing to be inactive at H (use to be in a low current state) and to operate at L.

  The low power control circuit 32 includes an inverting buffer 32, an FF 34, and an AND circuit 35. The inverting buffer 32 receives a low power control signal (chip select signal) 54 and outputs an inverted value similar to that of the FF 34. The AND circuit 35 inputs the output of the FF and the clock 12 and outputs the supply clock 14. Accordingly, when not operating (when the low power control signal (chip select signal) 54 is H), the supply clock 14 remains at the L level and the supply of the clock is stopped.

  FIG. 6 illustrates the case where the memory 30 has a configuration for controlling the presence or absence of internal clock supply based on a signal input from the chip select terminal 38, but is not limited thereto.

  For example, when the memory itself does not have such a function, a low power control circuit 32 may be provided in the integrated circuit as shown in FIG. The configuration of the low power control circuit 32 is the same as that shown in FIG. In this case, the output clock 14 of the low power control circuit 32 is connected to the clock terminal 39 of the memory.

  FIG. 8 is a timing chart regarding the clock supplied to the memory of this embodiment.

  12 is a reference clock, and 14 is a clock supplied to the memory.

  When addresses are continuous as indicated by 250, the supply clock is masked, so that the power of the memory can be reduced.

  FIG. 9 is a functional block diagram for explaining another configuration of the integrated circuit device of the present embodiment.

  The integrated circuit device 10 ′ of the present embodiment includes a CPU (processing circuit in a broad sense) 20, a memory 30, a memory interface circuit 40, a memory data bus 70, a CPU data bus 60, and an address bus 24.

  The CPU 20 outputs a chip select signal 22 and a request address 24 (16 bits of A0 to A15 here) to the memory interface circuit 40, and data (here, D0 to D31) corresponding to the request address 24 from the memory interface circuit 40. 32 bits) 60 is received.

  The chip select signal 22 is a signal that becomes Low active.

  The memory interface circuit 40 is configured to return data 60 corresponding to the request address 24 of the CPU 20 in a cycle of one clock.

  For example, the CPU reads out an instruction code stored in the memory 30 via the memory interface circuit 40 and executes a process of executing the read instruction.

  The memory 30 may be, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), an SRAM, a flash memory, or a DRAM, and stores data and instruction codes used by the CPU.

  The memory interface circuit 40 receives the chip select signal 22 and the request address 24 of the CPU 20, outputs a read address 90 to the memory based on the request address 24, reads data from the memory 30, and reads the data from the memory 20 based on the read data. The process of outputting the request address data 60 to the CPU 20 is performed.

  The memory data bus 70 ′ is connected to the memory 30 and the memory interface circuit 40 and has a bus width that is larger than the required data width of the CPU 20. Here, it has a data width of 128 bits that is four times the data width of 32 bits that is the required data width of the CPU 20.

  The CPU data bus 60 is connected to the CPU 20 and the memory interface circuit 40 and has a bus width (in this case, 32 bits) of the requested data width of the CPU 20. The CPU 10 is configured to handle 16-bit instruction codes while handling 32-bit data.

  The address bus 24 is connected to the CPU 20 and the memory interface circuit 40 and has a bus width (in this case, 32 bits) of the requested address width of the CPU 20. Although the CPU 10 handles a 32-bit width address, it is actually only 16 bits, so it is configured to process only the lower 16 bits.

  The memory interface circuit 40 generates read addresses (request addresses A2 to A15) based on the request address 24 received from the CPU 20, and the data corresponding to the bus width of the memory data bus 70 ′ from the memory 30 via the memory data bus 70. A data read circuit for reading (data for 128 bits), data holding circuits 42-1 to 42-4 for holding the read (extra prefetch) data 70 so as to be able to be taken out in units of CPU requested data width, and a request from the CPU A determination circuit (comparator 47) for determining whether or not the data at the address 24 is held in the data holding circuits 42-1 to 42-4, and if held, the data holding circuits 42-1 to 42-42. -4 stores the data corresponding to the request address of the CPU stored in the CPU 2 through the second bus 60. The pre-read data held in the data holding circuits 42-1 to 42-4 is delivered to the CPU 20 and the output circuit for outputting to the CPU 20, and the clock of the memory 30 is stopped or low power during a period when the memory 30 is not required to be accessed. A low power control signal generation circuit for generating and outputting a low power control signal 54 for generating a low power control signal.

  In addition, the integrated circuit device 10 ′ includes a BCU (Bus Control Unit), an MMU (Memory Management Unit), a DMAC (Direct Memory Access Controller), an LCD (Liquid Crystal Display) driver, or an SIO (Serial Input Output). Various peripheral circuits can be included.

  In the present embodiment, a Philip flop FF capable of holding 32 bits of data is connected to 32 bits of data on the CPU data bus in order to hold the data in units required by the CPU (32 bits here). For example, 32 bits of data can be stored in each of data 1 (32 bits from D0 to D31), data 3 (32 bits from D64 to D95), and data 4 (32 bits from D96 to D127). Philip flops FF may be connected.

  As shown in FIG. 10, the determination circuit 50 'receives the chip select signal 22 (Low active) from the CPU 20 and the comparison result signal 48 output from the comparator 47 (matches at 1 and does not match at 0). The chip selection signal (low power control signal) 54, the selection signal 45, and the address / data holding signal 52 input to the memory are generated and output to function as a low power control signal generation circuit.

  The determination circuit 50 ′ may include an OR circuit 91, the input of the OR circuit 91 may be connected to the chip select signal 22 and the comparison result signal 48, and the output may be the low power control signal 54. In this way, if the addresses match, the low power control signal 54 masking the chip select signal output from the CPU can be generated.

  Therefore, when the data corresponding to the CPU request address is held in the data holding circuit, the data is not read from the memory. Therefore, the memory can be reduced in power by masking the chip select signal 22. it can.

  The determination circuit 50 ′ may include an inverting buffer 92 and output an inverted value of the comparison result signal 48 as an address / data holding signal. In this way, when the CPU request addresses A2 to A15 do not match the addresses held in the address holding circuit, the addresses and data are held in the address holding circuit 46 'and the data holding circuits 42-1 to 42-4. To do.

  Further, the decision circuit 50 'comparison result signal 48 is passed through and output as the first selection signal 45'. The first selection signal 45 'is input as a selection signal to the first selection circuits 49-1 to 49-4.

  The first selection circuit 49-1 receives the data D0 to D31 of the first data buffer 42-1 and the CPU data bus, selects one based on the first selection signal 45 ', and outputs it.

  The first selection circuit 49-2 receives the first data buffer 42-2 and the data D32 to D63 of the CPU data bus, selects one based on the first selection signal 45 ', and outputs it.

  The first selection circuit 49-3 receives the first data buffer 42-3 and CPU data bus data D64 to D95, selects one based on the first selection signal 45 ', and outputs it.

  The first selection circuit 49-4 receives the first data buffer 42-4 and CPU data bus data D96 to D127, selects one of them based on the first selection signal 45 ', and outputs it.

  When the comparison result signals do not match, the first selection circuits 49-1 to 49-4 output the values of the data holding buffers 42-1 to 42-4 connected to the first selection circuits 49-1 to 49-4. Outputs data from the memory data bus.

  The second selection circuit 41 ′ receives the output of the first selection circuits 49-1 to 49-4 as input, selects one of the CPU request addresses A0 and A1 as a selection signal, and sends it to the CPU data bus 60. Output.

  When A0 and A1 are '11', the output of the first selection circuit 49-4 is selected and output. When A0 and A1 are '10', the output of the first selection circuit 49-3 is selected. Select and output. When A0 and A1 are '01', select and output the output of the first selection circuit 49-2. When A0 and A1 are '00', the first selection circuit. The output 49-1 is selected and output.

  The address holding circuit 46 is a Philip flop FF capable of holding an address for 14 bits, and its input is connected to the signal lines of the request addresses A2 to A15 of the address bus 24 of the CPU 20 and the address / data holding signal 52, and its output is compared. Connected to the device 47. The address holding circuit 46 holds the CPU request addresses A0 to A15 at the timing when the address / data holding signal 52 is at the first level.

  As shown in FIG. 9, among the addresses (A0 to A15) for reading data from the memory, the upper bits (14 bits A2 to A15) common to the data address held in the data holding circuit 42 are held. An address holding circuit 46 may be provided.

  As described above, the address holding circuit 46 has the number of bits corresponding to the power of 2 of the bus width of the memory data bus (here, 32 bits × 2), which is n in the case of 32 bits × 2 to the nth power. It can be configured not to hold the lower bit of the minute.

  In the above embodiment, the case where the memory interface circuit is configured to return data corresponding to the CPU request address in a cycle of one clock has been described as an example, but the present invention is not limited to this. For example, the memory interface circuit may be configured to return data corresponding to a CPU request address in a cycle of two clocks or more.

  FIG. 11 is a timing chart when the memory interface circuit is configured to return data corresponding to a CPU request address in a cycle of 2 clocks or more.

  In this case, it is necessary to issue a wait signal 96 from the memory interface circuit to the CPU as shown in FIG.

  In this embodiment, as shown by 310, two clocks are required for one memory access. However, as shown by reference numeral 320, it is possible to send data to the CPU in one clock for a name having data retention.

2. Microcomputer FIG. 13 is an example of a hardware block diagram of the microcomputer of this embodiment.

  The microcomputer 700 includes a CPU 510, a cache memory 520, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller / bus I / F 570, an interrupt controller 580, a serial interface 590, and a bus controller 600. A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 560, prescaler 570 and general-purpose bus 680 connecting them, dedicated bus 730, etc. A memory interface circuit 740, various pins 690, and the like are included.

  The memory interface circuit 740 has the configuration described with reference to FIGS. 1 and 9, for example.

3. Electronic Device FIG. 14 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  FIG. 15A illustrates an example of an external view of a mobile phone 950 which is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 15B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 15C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 15A to 15C, an electronic device with low cost and high image processing speed can be provided.

  As electronic devices that can use this embodiment, in addition to those shown in FIGS. 15A, 15B, and 15C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

1 is a functional block diagram of an integrated circuit device of an embodiment mode. FIG. 6 illustrates an example of a determination circuit in this embodiment. The flowchart figure of a process of a memory interface circuit. The flowchart figure of a process of a memory interface circuit. FIG. 6 is a timing chart of this embodiment. The figure for demonstrating an example of low-power of memory. Explanatory drawing of the example which provides a low power control circuit in an integrated circuit. The timing chart figure regarding the clock supplied to memory. FIG. 10 is a functional block diagram for explaining another structure of the integrated circuit device of this embodiment. FIG. 10 illustrates an example of a determination circuit having another configuration of the present embodiment. The timing chart figure in case a memory interface circuit respond | corresponds with the cycle of 2 clocks or more. It is a figure for demonstrating a wait signal. The hardware block diagram of the microcomputer of this Embodiment. An example of a block diagram of an electronic device including a microcomputer is shown. 15A, 15B, and 15C are examples of external views of various electronic devices.

Explanation of symbols

10 integrated circuit device, 20 CPU, 22 chip select signal, 24 address bus, 30 memory, 32 low power control circuit, 40 interface circuit, 44 selection circuit, 42 data holding circuit, 44 address holding circuit, 47 comparator, 50 judgment Circuit, 54 Low power control signal, 60 CPU data bus, 70 Memory data bus, 510 CPU, 530 LCD controller, 540 Reset circuit, 550 Programmable timer, 560 Real time clock (RTC), 570 DRAM controller / bus I / F, 580 Interrupt controller, 590 serial interface, 600 bus controller, 610 A / D converter, 620 D / A converter, 630 input port, 640 output port, 650 I / O port, 6 60 Clock generator (PLL), 670 Prescaler, 680 General-purpose bus, 690 Various pins, 700 Microcomputer, 710 ROM, 720 RAM, 730 MMU, 800 Electronic device, 850 LCD

Claims (11)

An integrated circuit device comprising:
CPU,
Memory,
A memory interface circuit that receives a CPU request address, reads data in the memory based on the request address, and outputs data corresponding to the CPU request address to the CPU;
A memory data bus connected to the memory and the memory interface circuit and having a bus width larger than a requested data width of the CPU;
A CPU data bus connected to the CPU and a memory interface circuit;
The memory interface circuit includes:
A data read circuit for reading out data corresponding to the bus width of the memory data bus larger than the requested data width of the CPU from the memory via the memory data bus based on the requested address received from the CPU;
A data holding circuit for holding the read data so that it can be taken out in units of CPU request data width;
It is determined whether or not the data of the CPU request address is held in the data holding circuit, and if it is held, the memory is not accessed in accordance with the CPU request address and held in the data holding circuit. An output circuit that outputs data corresponding to the requested address of the CPU to the CPU via the CPU data bus;
A low power control signal generation circuit that generates and outputs a low power control signal for stopping or reducing the clock of the memory in a cycle that does not access the memory in accordance with the requested address of the CPU;
An integrated circuit device comprising: In claim 1,
The memory is
Input the low power control signal from the chip select terminal,
An integrated circuit device, comprising: a low power control circuit that controls the clock in the memory to stop or reduce current consumption based on the low power control signal. In claim 1,
A clock control circuit for controlling a clock supplied to the memory based on the low power control signal;
The memory is
An integrated circuit device configured to receive a clock signal controlled by a clock control circuit from a clock control terminal. In any one of Claims 1 thru | or 3,
2. The integrated circuit device according to claim 1, wherein the memory data bus has a bus width that is a power of 2 times the data width required by the CPU. In any one of Claims 1 thru | or 4,
The data holding circuit is
An integrated circuit device characterized in that only a pre-read portion of read data is held so as to be able to be taken out in units of CPU requested data width. In any one of Claims 1 thru | or 5,
The determination circuit includes:
An address holding circuit that holds an address corresponding to the upper bits common to the data address held in the data holding circuit among the CPU request addresses;
It is determined whether the address held in the address holding circuit matches the corresponding bit portion of the CPU request address, and based on the determination result, it is determined whether the data of the CPU request address is held in the data holding circuit. An integrated circuit device. In any one of Claims 1 thru | or 6.
The memory interface circuit includes:
An integrated circuit device configured to return data corresponding to a request address of a CPU in a cycle of one clock. In any one of Claims 1 thru | or 6.
The memory interface circuit includes:
An integrated circuit device configured to return data corresponding to a request address of a CPU in a cycle of 2 clocks or more. In any one of Claims 1 thru | or 8.
The CPU
Outputs the increment signal of the program counter,
The determination circuit of the memory interface circuit includes:
An integrated circuit device comprising: determining whether data of a CPU request address is held in the data holding circuit based on the increment signal.   A microcomputer comprising the integrated circuit device according to claim 1. A microcomputer according to claim 10;
Means for receiving input information;
Means for outputting a result processed by the information processing device based on input information;
An electronic device comprising:

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