JP2006285372A - Z-sorting processing circuit and three-dimensional image drawing device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-dimensional image drawing device which can quickly sort polygons, and also provide a sorting-processing method. <P>SOLUTION: The three-dimensional image drawing device is provided with; a memory 30 which stores sorting data including depth values which are the functions of the depths on a screen of polygons; a sorting-data reading control circuit 100 which reads out the sorting data from the memory 30 according to a starting address stored in a buffer 140 for a reading-start address value and an end address stored in a buffer 150 for a reading-end address value; a depth value comparison circuit 120 which compares the depth value of the sorting data thus read out with a reference depth value; and reading-start address determination circuit 160 and reading-end address determination circuit 170 which each control a reading-start address and a reading-end address, respectively, in accordance with the sorting data having image-drawing order determined, when the sorting data are repeatedly read out from the memory 30. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a three-dimensional image drawing apparatus for drawing a three-dimensional image, and more particularly to a Z sort processing technique for sorting semi-transparent drawing data (semi-transparent polygon) in the Z direction.

  A three-dimensional object called “model” used in 3D graphics is composed of a plurality of triangles called polygons, and is represented as a three-dimensional object by three-dimensional coordinate values (x, y, z) of each vertex. In general, as shown in FIG. 8, the coordinate space of vertices constituting this model data is “model coordinates”, the coordinate space where the model is arranged is “world coordinates”, and the camera for copying the picture displayed on the monitor is used as a reference This coordinate space is called “camera coordinates”, and the final coordinate space on the monitor screen is called “screen coordinates”.

Basic 3D graphics processing when displaying model data arranged in a three-dimensional space on a two-dimensional screen such as a monitor is performed in the following order.
1) Place the model and camera in the world coordinate space.
2) Each vertex data (model coordinates) of the model data is converted into world coordinates, and further converted into camera coordinates so that each vertex coordinate value becomes a coordinate value when viewed from the camera.
3) Perform lighting calculation (brightness and color calculation) for each vertex of the model according to the direction and color of the “light (light source)” set in the world coordinate space.
4) Each vertex coordinate in camera coordinates is perspective-transformed into screen coordinates, and the coordinate value is input to a drawing circuit to perform drawing processing.

  In three-dimensional graphics, an object such as colored glass that can be seen through the other side may be drawn. This is generally called translucent drawing. The translucent rendering process reads each pixel color data of the background that is already stored in the frame buffer at the drawing position of the glass, calculates the background color and glass color, and stores the calculated color data in the frame buffer. Just do it. In the translucent drawing process, for example, the addition result is halved. By the way, translucent is easy to understand in terms of words, so the actual color calculation ratio can be freely specified, and the graphics terminology is “α blending” (the color calculation ratio parameter is an α value). Is called).

  If you mix "opaque drawing" like background and "semi-transparent drawing" like glass in one screen, draw only the opaque thing first, and after that drawing is semi-transparent The drawing is performed while translucent processing is performed in order from the object on the back side of the screen. For example, as shown in FIG. 9A, first, all opaque backgrounds such as mountains and the sun are drawn, and then, as shown in FIGS. 9B and 9C, from the back side of the screen. The translucent glass is drawn in the order of A, C, and B.

  As described above, in the semi-transparent drawing process, it is necessary to draw in order from the drawing object on the back side of the screen toward the front side of the screen, so the semi-transparent drawing objects are arranged in order from the back side of the screen before the drawing process. It is necessary to change. In the above example, the translucent glasses are arranged in the order of A → C → B. This process is generally called “Z sort process” because it sorts by the Z coordinate value corresponding to the coordinate axis perpendicular to the screen.

  The translucent object in 3D graphics is not limited to the above-described planar object such as glass, but is a three-dimensional object as shown in FIG. When rendering this cube translucently, Z sort processing is performed in units of polygons, and translucent rendering processing is performed in order from the polygons at the back of the screen.

  Several techniques have been reported for the Z sort process. In Patent Document 1, opaque polygon data and semi-transparent polygon data are identified by a polygon identification unit, an estimated drawing time required for drawing Z-sorted semi-transparent polygon data is calculated, and opaque polygons and semi-transparent data are calculated from the estimated drawing time. The switching time of drawing with transparent polygons is calculated, and switching from opaque polygon data to transparent polygon data is enabled. Accordingly, a translucent drawing generation apparatus is provided which can shorten the program development time and can draw the translucent polygon data to be drawn in one frame period without omission.

  Patent Document 2 distinguishes polygons constituting an image from translucent ones and opaque ones, and when drawing of all opaque polygons is completed, the semi-transparent polygons are moved in the order from the back to the front in the Z buffer. Rendered using. This speeds up drawing of an image including an opaque polygon and a translucent polygon.

  Patent Document 3 prepares information indicating whether or not each of a plurality of polygons can be seen for each viewpoint in order to eliminate the waste of drawing a polygon that is hidden behind the object and cannot be seen, and uses this information at the time of drawing processing. Only the visible polygons are drawn.

  Patent Document 4 selects object data located within a field of view defined with reference to a viewpoint position from object data, and perspective-converts the selected object data into image data to be a projected image on a screen, and the converted image Data is Z-sorted, image data that is more than a predetermined distance away from the viewpoint position is extracted from the Z-sorted image data, and a semi-transparent dummy polygon with a translucent image shifted by several dots as a texture is generated. A blurry and blurred image is drawn according to the image data including the dummy polygon. Thereby, the three-dimensional image data is displayed as a realistic image.

  Japanese Patent Application Laid-Open No. 2004-151867 shows an order indicating the processing order of each block by using, as an address, information in the Z direction of each block obtained by dividing the image into a plurality of order tables on the memo-in memory allocated for each object constituting the image Data is written and drawing data is created by Z-sorting a plurality of order tables step by step by the DMA controller. As a result, even when physically separated objects are close in depth, it is possible to eliminate the polygon unit interference and generate drawing data with good image quality.

JP 2000-268190 A JP-A-10-11610 JP 9-44697 A JP 2000-93654 A JP-A-7-114654

  In a conventional three-dimensional image drawing apparatus, Z sort processing is performed using software or hardware. When performing Z sort by software, there is a degree of freedom that can provide a Z sort processing method most suitable for the content to be drawn, but on the other hand, designing an algorithm for optimizing the processing requires a large cost. Further, since a relatively large memory capacity for storing the calculation result is required and the frequency of access to the memory is increased, there is a limit to speeding up the Z sort processing time.

  On the other hand, when a hardware dedicated Z sort circuit is installed, all processing from vertex coordinate calculation to drawing processing can be executed by hardware processing, so a simple configuration can be realized and the CPU load is reduced. Can improve the processing performance of the system. However, when the Z sort circuit of the method of comparing and sorting the Z coordinate values for each polygon one by one, it is possible to deal with any drawing content and has the advantage of reducing the sort circuit scale. If the number of polygons to be sorted increases, Z coordinate value comparison is performed by the squared number of times, so that a lot of time is required for the sorting process, and it is difficult to speed up the Z sorting process.

The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a three-dimensional image drawing apparatus and a sort processing method that can perform polygon sorting at high speed.
A further object of the present invention is to provide a three-dimensional image drawing apparatus capable of processing from vertex coordinate calculation to drawing processing by hardware by providing a hardware Z sort processing circuit.
A further object of the present invention is to provide a three-dimensional image drawing apparatus that reduces the burden on other hardware resources by providing a Z sort processing circuit and enables high-speed drawing of three-dimensional graphics. .

  The three-dimensional image drawing apparatus according to the present invention includes the following configuration including a function of sorting polygons from the back of the screen toward the front of the screen or from the front of the screen toward the back of the screen. Storage means for storing sort data including depth values that are functions of the screen depth for polygons, read means for reading sort data from the storage means, and the depth value of the sort data read by the read means as a reference depth Comparing means for determining the drawing order by comparing with the value, and reading control means for controlling reading of the sorting data in accordance with the sorting data for which the drawing order is determined when the reading data is repeatedly read by the reading means Including.

  Preferably, the reading control unit controls the reading unit so as to exclude the sorting data for which the drawing order of the sorting data has been determined from being read. Preferably, the read control unit supplies the read start address and the read end address of the sort data to the read unit, and updates at least one of the read start address and the read end address according to the sort data for which the drawing order is determined. To do.

  Further, the reading unit reads the sorting data in units of blocks, and the reading control unit reads out the block to be excluded from the reading target when the drawing order of all the sorting data included in the block is determined. Control means. The read control unit holds flag information for determining whether or not the drawing order of all sort data included in the block has been determined, and controls the read address of the read unit based on the flag information. May be.

  Preferably, the polygon to be sorted is a translucent polygon. In order to perform sorting at a higher speed, a synchronous memory such as DDR-SDRAM is used as the storage means, and the sorting data block is read by burst read. The polygon depth value may be an average value, minimum value or maximum value in the Z-axis direction of the vertex coordinates of the polygon, and the reference depth value is a polygon selected from a plurality of polygons to be compared. Is the depth value of.

  Furthermore, a polygon sorting method for sorting polygons according to the present invention from the back side of the screen toward the near side of the screen or from the near side of the screen toward the far side of the screen is a sort that includes a depth value that is a function of the screen depth for a polygon that is a drawing object. Storing data for storage in a storage device, reading out data for sorting from the storage device, comparing a depth value of the read data for sorting with a reference depth value, and determining a drawing order; When the sorting data is repeatedly read out from, the step of controlling the reading of the sorting data according to the sorting data for which the drawing order is determined is included.

  Preferably, the sort data is read in units of blocks, and when the drawing order of all sort data in the block is determined, the reading is controlled so that the block is excluded from the read target. More preferably, the step of reading reads out the data for sorting according to the end address from the start address, and the step of controlling controls at least one of the start address and the end address.

  According to the 3D image drawing apparatus of the present invention, when the sorting data stored in the storage unit is repeatedly read, the address for reading the sorting data is controlled according to the sorting data for which the drawing order is determined. As a result, sorting data can be read efficiently, sorting data can be compared and the drawing order can be determined, and the polygon sorting process can be speeded up.

  A three-dimensional image drawing apparatus according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a system configuration of a three-dimensional image drawing apparatus according to an embodiment of the present invention. The three-dimensional image drawing apparatus 1 controls a CPU 10 that controls the entire system, a drawing circuit 20 that controls two-dimensional or three-dimensional graphic drawing, a memory 30 that stores programs and image data, and access to the memory 30. A memory controller 40, an image display circuit 50 for outputting image data stored in the memory to a monitor, an external memory 60 connected to an external port for storing data such as a program, an internal bus and an external port (serial I / F) A peripheral control circuit 70 that performs control and a monitor 80 that displays image data output from the image display circuit 50 are configured.

  The drawing circuit 20 further performs a three-dimensional calculation (rotation, expansion, movement, etc.) of each vertex coordinate value of the model, light source calculation, and the like, a geometry circuit 22 for obtaining vertex data in the screen coordinate space, and a drawing minimum unit. A Z sort processing circuit 24 that performs Z sort processing and clipping processing of triangular or quadrilateral polygon data, and a rendering circuit 26 that performs graphic drawing according to a drawing list. In this embodiment, by configuring the drawing circuit 20 with hardware, model coordinate operations, Z sort processing, and drawing processing can be realized with hardware.

  FIG. 2 is a diagram illustrating a basic flow of a drawing process in the three-dimensional image drawing apparatus. The CPU 10 calculates each parameter serving as a basis for rotation and movement of the model in accordance with the program data 31 and the three-dimensional model data 32 in the memory 30 (step a). The CPU 10 generates geometry circuit drawing list data 33 in a format accepted by the geometry circuit 22 according to each parameter of the calculated model data, and stores it in the memory (step b).

  The geometry circuit 22 performs the determined vertex calculation process while reading the geometry circuit drawing list data 33 in the memory, and sends the result to the sort processing circuit 24 (step c).

  The sort processing circuit 24 performs Z sort processing and clipping processing in accordance with the drawing list data 33 subjected to the vertex calculation received from the geometry circuit 22, and generates rendering circuit drawing list data 34 in a format accepted by the rendering circuit 26. This is stored in the memory (step d).

  The rendering circuit 26 calculates the rendering process pixel parameters while reading the rendering circuit rendering list data 34 in the memory (step e). The pixel parameter for drawing processing is a parameter necessary for pixel drawing, such as a texture coordinate value of the drawing pixel, a depth value of the drawing pixel (that is, a screen depth direction coordinate value: Z value), and a frame buffer coordinate value of the drawing pixel. .

  The rendering circuit 26 reads the texture data 35 corresponding to each pixel from the memory according to the texture coordinate value of the drawing pixel and processes it to obtain the color data of the drawing pixel (step f), and further, the depth value and the depth of the drawing pixel. It is determined whether to perform pixel drawing according to the comparison result of the depth values read from the buffer 36 (step g).

  The rendering circuit 26 further calculates the color data of the drawing pixel in accordance with the α blending processing specification, and stores the data at the coordinate position of the drawing pixel frame buffer 37 (step h).

  Next, details of the sort processing circuit 24 of this embodiment will be described. As the Z coordinate value to be compared when the polygons constituting the three-dimensional object are Z-sorted, the “average value” of the Z coordinate values of the respective vertexes (three vertices in the case of a triangle) of the polygon can be used. However, the minimum value or the maximum value of the Z coordinate value of the polygon may be used.

  The value used for the comparison may be a value in the depth direction related to the coordinate axis perpendicular to the screen, and is not limited to the “Z coordinate value”. Therefore, in this specification, in the following description, values used for comparison are collectively referred to as “depth values”.

The outline of the Z sort processing in the sort processing circuit 24 is as follows.
1) The input translucent drawing object is divided into polygons, and a depth average value of each polygon is obtained.
2) The depth average values of the polygons are compared in size and rearranged sequentially from the back of the screen. When the depth average values are equal, the order is determined according to a predetermined rule. Normally, the earlier processing order is set to the back side of the screen.

  In general, the vertex xyz coordinate value and the depth value are expressed using “16-bit / 32-bit fixed-point number” or “32-bit floating-point number”. In recent three-dimensional computer graphics, a 32-bit floating point number having a large expressible range as a numerical value is often used. The following table shows the data structure of a 32-bit floating point number defined by the international standard by IEEE.

  FIG. 3 is a diagram illustrating a flow of the Z sort process. Here, it is assumed that the depth value is smaller on the back side of the screen than on the near side of the screen. First, the sort processing circuit 24 sets a predetermined maximum number of values as the minimum holding depth value (step S101). The minimum retained depth value is the average depth value of the polygons that are on the farthest screen side (in other words, the depth value is the minimum value) among all the translucent drawn polygons. The minimum hold depth value is stored in, for example, the memory 30 or a register.

  The sort processing circuit 24 divides the semi-transparent drawing object after the screen coordinate projection processing having the vertex coordinates after the three-dimensional calculation in the order of input, into triangle polygon units, and stores this in the memory 30 as polygon data ( Step S102).

  The sort processing circuit 24 calculates the depth average value of the three vertices of the triangular polygon in the order of input, and this average value is stored in the memory 30 as sort data together with the head address of the polygon data stored in the memory 30. Stored (step S103).

  FIG. 4 shows a state in which polygon data and sorting data are stored in the memory 30. As shown in the figure, the sort processing circuit 24 stores the polygon data 0, 1, 2,... In the memory 30 in the input order. Each polygon data includes xyz coordinate values, texture coordinate values, shading colors, and the like for three vertices. The sort processing circuit 24 stores sort data 0, 1, 2,... Corresponding to polygon data 0, 1, 2,. Each sort data includes the head address of the corresponding polygon data and the depth average value. For example, the sort data 0 includes the top address of the polygon data 0 and its depth average value.

  The sort processing circuit 24 compares the polygon depth average value and the minimum hold depth value, and holds the smaller one in the register as the minimum hold depth value (step S104). Until the polygon data and sort data of all the translucent drawing objects are stored in the memory 30, the processes from step S102 to step S104 are repeated.

  Next, the sort process is started. The sort processing circuit 24 sets the depth average value of the first sort data (sort data “0” in FIG. 4) as a temporary holding depth value in the register (step S106). The sort processing circuit 24 sequentially reads the sort data from the memory 30, and compares the depth average value with the minimum hold depth value (step S107).

  As a result of the depth value comparison (step S108), when the depth average value of the sorting data is larger than the minimum holding depth value, the depth average value of the sorting data is further compared with the temporary holding depth value. When the depth average value of the sorting data is smaller than the temporary holding depth value (depth average value <primary holding depth value), the temporary holding depth value is updated to the depth average value of the sorting data (step S109).

  If the depth average value of the sort data is equal to the minimum hold depth value, the polygon data head address value in the sort data is stored in the memory 30 as “polygon drawing order data” (step S110).

  When the depth average value is smaller than the minimum holding depth value, the comparison result is not processed. In this way, when comparison processing has been performed for all sort data, a translucent polygon of a translucent drawing object to be drawn first on the back side of the screen is detected (step S111). In addition, since the depth value (second depth value) next to the minimum holding depth value is stored in the temporary holding depth value, the minimum holding depth value is updated to the temporary holding depth value (step S112). ). In the next sorting process, a semi-transparent polygon having the second smallest depth average value is detected.

  The above process is repeated until “polygon drawing order data” for all polygons is completed (step S113), and the Z sort process is completed (step S114). The polygon drawing order data is stored in the memory 30 as the drawing list data 34.

  FIG. 5 is a diagram illustrating a storage state of polygon drawing order data. As shown in the figure, as a result of the sorting process, the head address value of the polygon data to be drawn first is stored in the head address of the polygon drawing order data (polygon head address “0”). The address stores the start address value of the polygon data to be drawn second. By referring to the contents in order from the top address of the polygon drawing order data, the translucent polygon data can be read.

  When the drawing order of polygons is determined by comparing the depth average values of polygon data, if there are N triangular polygons having different depth average values, N × N comparison processes are executed. become. That is, the depth value comparison processing must be performed as many times as the square of the number of semitransparent drawing polygons.

  In this embodiment, when the sorting data is read from the memory 30 in order to create the polygon drawing order data, the Z sorting process is speeded up by controlling the reading of the sorting data of the already sorted polygons. I am letting.

  FIG. 6 is a block diagram showing the internal configuration of the sort processing circuit. The sort processing circuit 24 includes a sort data read control circuit 100 that controls reading of sort data, a sort data buffer 110 that temporarily stores sort data read from the memory 30 via the memory controller 40, and a sort Floating-point depth value comparison circuit 120 that compares depth average values of data, drawing order data write control circuit 130 that writes the drawing order of polygons that match the minimum holding depth value based on the comparison result by comparison circuit 120, and for sorting The read start address of the data is stored, the read start address value buffer 140 that supplies the read start address of the data to the sort data read control circuit 100, and the read end address of the sort data are stored, and this is stored as the sort data read control circuit 100. Read end address value buffer supplied to 150 includes a read start address judging circuit 160 to update the contents of the read start address value buffer 140, the read end address determination circuit 170 to update the contents of the read address temporary buffer 180.

  Preferably, the memory 30 for storing polygon data and sort data uses DDR-SDRAM (Double Data Rate Synchronous Dynamic RAM) capable of burst read and burst write. Alternatively, it may be SDRAM, DRAM, or synchronous SRAM. By burst read, for example, sorting data can be read out in blocks of 8 or 16 units.

  The sort data read control circuit 100 reads the sort data block in the burst mode according to the read start address held in the read start address value buffer 140, and follows the read end address held in the read end address value buffer 150. Finish reading the sort data block.

  The read start address value buffer 140 is set with the storage start address value of the sort data when the Z sort process is started. The read end address value buffer 150 is set with the final sort data storage address value for each block when the Z sort process is started. These buffer address values are held when polygon data and sort data are stored in the memory 30.

  The read start address determination circuit 160 determines that the depth value comparison result based on the sorting data in the read block never becomes “depth average value> minimum holding depth value”, in other words, for sorting in the block. When all of the data already matches the minimum hold depth value and the drawing order has been determined, it is determined that the read start address needs to be updated, and the start address value of the next block is read start address value. Set to.

  The read address temporary buffer 180 stores the head address value of the read block, and this address value is updated by the read final address determination circuit 170. When the depth value comparison result based on the sorting data in the block has never been “depth average value> minimum holding depth value”, the read final address determination circuit 170 continues to hold the value, and even once, “ When “depth average value> minimum holding depth value” is satisfied, the data is updated to the head address value of the block read by the next sort data read.

  Further, when the read address value of the read block matches the read final address value, the read final address determination circuit 170 determines that there is final sort data in the block, and compares the depth value with the final sort data. When the processing is completed, the address value held in the read address temporary buffer 180 is set as the read end address value.

  Next, the operation of the sort processing circuit will be described with reference to the example of FIG. The sort data in FIG. 7 includes data 0 to data 21 and two invalid data (shown in gray in the figure). Invalid data is identified, for example, by providing a flag in the data. The value in parentheses of the sort data is the depth average value. As sort processing, eight sort data are read out in block units by burst read.

  The sort data read control circuit 100 starts the Z sort process as shown in step S107 in the flowchart of FIG. The read start address value buffer 140 holds an address corresponding to data 0, and the read end address value buffer 150 holds an address corresponding to data 21. The sort data read control circuit 100 reads the first block, that is, the sort data blocks from data 0 to data 7, based on the read start address.

  The sort data read control circuit 100 holds the head address of the block (the address of “data 0”) in the read address temporary buffer 180 as the block is read. The read sort data block is temporarily stored in the sort data buffer 110 and then compared with the minimum hold depth value in the depth value comparison circuit 120.

  In the first Z sort process, the minimum holding depth value is “0.2”. In this depth value comparison processing, the depth average value of “data 0” and “data 3” is “0.2”, and the drawing order of polygons corresponding to “data 0” and “data 3” is determined. Whether “data 0” or “data 3” is drawn first can be determined, for example, in the order in which polygon data is input. In this case, the order is “data 0” and “data 3”. Based on this result, the drawing order data write control circuit 130 writes the drawing order data.

  The read start address determination circuit 160 does not update the read start address value buffer 140 because the average depth value> the minimum retained depth value exists. Further, since the average depth value> minimum holding depth value exists, the read end address determination circuit 170 stores the read address temporary buffer 180 in the next block read head address, that is, “data 8”. Update to the address.

  When the sorting process of the first block is completed, the sorting data read control circuit 100 reads the sorting data (“data 8” to “data 15”) of the second block. In the second block, there is no sort data equal to the minimum holding depth value, that is, since there is a depth average value> minimum holding depth value, the read start address value buffer 140 is not updated. The read address temporary buffer 180 is updated to the head address of the block, that is, the address of “data 16” when the next block is read.

  When the sorting process of the second block is completed, the sorting data read control circuit 100 reads the sorting data (“data 16” to “data 21”) of the third block. In the third block, since the address of “data 21” matches the address held in the read end address value buffer 150, the sort data read control circuit 100 determines that this block is the last read block. The address value held in the read address temporary buffer 180 is set in the read end address value buffer 150. That is, the address of “data 16” that is the head address of the third block is set.

  In the second sort process, the minimum hold depth value is updated to “0.3”. In the first block, “data 1”, “data 5”, and “data 6” coincide with the minimum holding depth value, and the drawing order of these is determined. In the second block (“data 8” to “data 15”), there is no sorting data that matches the minimum holding depth value, and in the third block, “data 18” and “data 20” are the minimum holding depth values. These drawing orders are determined.

  In the second sort, the read start address determination circuit 160 does not update the start address held in the read start address value buffer 140 because the depth average value> the minimum hold depth value exists. Also, the end address of the read end address value buffer 150 is not updated.

  In the third sort, the minimum hold depth value is updated to “0.4”. In the first block, “data 2”, “data 4”, and “data 7” coincide with the minimum holding depth value, and the drawing order of these is determined. In the second block, “data 10” matches the minimum holding depth value, and in the third block, “data 16” matches the minimum holding depth value, and the drawing order thereof is determined.

  The read start address determination circuit 160 determines that the depth value comparison result is never the depth average value> minimum holding depth value in all sort data included in the first block, and the read start address value buffer 140. Is set to the start address value of the second block. That is, the address value of “data 8” is set to the read start address value.

  In the fourth sort, the sort data read control circuit 100 performs burst read on the block having “data 8” at the head address in accordance with the start address of the read start address value buffer 140. In the fourth sorting, the minimum holding depth value is updated to “0.5”, and “data 9” matches the minimum holding depth value in the first block, and “data 17”, “ Data 19 "matches the minimum hold depth value, and the drawing order of these is determined.

  In the fifth sort, the minimum hold depth value is updated to “0.6”. In the first block, “data 8” and “data 11” match the minimum holding depth value, and in the second block, “data 21” matches the minimum holding depth value, and the drawing order is determined.

  The read end address determination circuit 170 determines that the depth value> minimum holding depth value never occurs in the second block, updates the read address temporary buffer 180 to the head address of the previous block, and reads the read end address value. The buffer 150 is updated to the head address.

  In the sixth sort, the minimum holding depth value is updated to “0.7”, and the sorting data read control circuit 100 reads only the blocks including “data 8” to “data 15”, and compares these depth values. Process.

  In this way, until the polygon drawing order data is completed, in other words, until the depth value comparison result never becomes “depth average value> minimum holding depth value”, the reading of the sorting data and the depth value comparison processing are repeated. It is. At the time of reading the sorting data repeated several times, all the polygons in the block have already been sorted (the depth value comparison result in the block has never been “depth average value> minimum holding depth value”). Since the sort data is controlled so as not to be read again, the number of sort data read before the end of the Z sort process is reduced, and the Z sort process can be speeded up.

  In the sort processing circuit according to the present embodiment, by controlling the read start address and the end address value, the number of read sort data is gradually reduced while the sort data is read a plurality of times. In the configuration shown in FIG. 6, except for the read start address determination circuit 160, the read end address determination circuit 170, and the read address temporary buffer 180, these three circuits are necessary for normal depth value comparison processing. By adding a simple circuit, the Z sort process can be speeded up.

  Of course, if there is a polygon closest to the screen in the first sorting data block, the number of reads based on the read start address value cannot be reduced. In addition, even when the last sorting data block includes a polygon that is at the back of the screen, the number of reads based on the read end address value cannot be reduced. However, in this case, sort processing in the depth direction of the screen is performed by software in units of translucent drawing objects, etc., so that object input to the sort accelerator is performed in order from the object at the back of the screen (that is, the sort data) Are stored in order from the back side of the screen), and the number of sorting data reads can be reliably reduced.

  Furthermore, in the method of the above embodiment, the block between the read start address value and the read end address value is read even if the sorting processing of all the polygons in the block has already been completed. In order to avoid this, block processing end flag circuits (maximum number of blocks × 1 bit) corresponding to the maximum number of sort data blocks may be added, and the block to be read may be controlled according to the flag value. The block process end flag control in this case can be performed as follows.

1) When the Z sort process is started, all the block process end flags are cleared to “0”.
2) If the depth value comparison result based on the sorting data in the read block has never become “depth average value> minimum holding depth value”, the block processing end flag corresponding to the block is set to “1”. .
3) A block whose block processing end flag corresponding to a block between the read start address value and the read end address value is “1” is not read-processed. By doing so, it is possible to perform the read control of the sorting data block more efficiently.

  Further, in the above embodiment, the read start address value and the end address value are used as the head address value in block units, but it is of course possible to control with one data unit address value. Further, all the sort data may not be stored continuously in the memory. For example, when storing the sort data in the memory, the address value for storing the next block data is put in the last data of the block unit, and when reading the sort data, the block unit is sequentially ordered according to the address value. It is also possible to lead by.

  Furthermore, the Z sort processing circuit according to the above embodiment has shown an example of Z sort for a semi-transparent polygon. However, the present invention is not limited to this, and it is possible to perform Z sort of polygons of an opaque drawing object. In particular, the present invention can be applied to a case where opaque polygons are Z-sorted and drawn from the back side of the screen to the near side of the screen or from the near side of the screen to the far side of the screen without using the Z buffer.

  Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed.

  The three-dimensional image drawing apparatus and the Z sort processing method according to the present invention are used in a three-dimensional graphics computer, a video game machine, a game machine, and other video apparatuses.

It is a block diagram which shows the system configuration | structure of the three-dimensional image drawing apparatus which concerns on the Example of this invention. It is a figure which shows the basic process of the circuit for drawing. It is a figure which shows the flow of Z sort process. It is a figure which shows the storage state of the polygon data and the data for sorting. It is a figure which shows the storage state of the data for polygon drawing order. It is a block diagram which shows the structure of the sort processing circuit of a present Example. It is a figure which shows the example of a sort process of a present Example. It is a figure which shows the coordinate space of model data. It is a figure explaining translucent drawing. It is a figure which shows the example of the semi-transparent object of a solid object.

Explanation of symbols

1: 3D image drawing apparatus 10: CPU
20: Drawing circuit 30: Memory 40: Memory controller 50: Image display circuit 100: Sort data read control circuit 110: Sort data buffer 120: Depth value comparison circuit 130: Drawing order data write control circuit 140: Read Start address value buffer 150: Read end address value buffer 160: Read start address determination circuit 170: Read end address determination circuit 180: Read address temporary buffer

Claims (12)

A 3D image drawing apparatus having a function of sorting polygons from the back of the screen toward the front of the screen or from the front of the screen toward the back of the screen,
Storage means for storing sorting data including depth values that are functions of screen depth for polygons;
Reading means for reading data for sorting from the storage means;
Comparing means for determining the drawing order by comparing the depth value of the sorting data read by the reading means with the reference depth value;
A read control means for controlling the reading of the sort data according to the sort data for which the drawing order has been determined when the sort data is repeatedly read by the read means;
A three-dimensional image drawing apparatus. The three-dimensional image drawing apparatus according to claim 1, wherein the reading control means controls the reading means so as to exclude the sorting data for which the drawing order of the sorting data has been determined from being read. The three-dimensional image drawing apparatus according to claim 1, wherein the read control unit supplies the read start address and the read end address of the sort data to the read unit. The three-dimensional image drawing apparatus according to claim 3, wherein the read control unit updates at least one of the read start address and the read end address in accordance with the sorting data for which the drawing order is determined. The reading unit reads the sorting data in units of blocks, and the reading control unit reads out the block from the reading target when the drawing order of all the sorting data included in the block is determined. The three-dimensional image drawing apparatus according to any one of claims 1 to 4, wherein the three-dimensional image drawing apparatus is controlled. The read control means holds flag information for determining whether or not the drawing order of all sort data included in the block has been determined, and controls the read address of the read means based on the flag information. The three-dimensional image drawing apparatus according to 5. The three-dimensional image drawing device according to claim 1, wherein the storage unit includes a memory capable of burst reading. The three-dimensional image drawing apparatus according to any one of claims 1 to 7, wherein the polygon is a translucent polygon. A polygon sorting method for sorting polygons from the back of the screen toward the front of the screen or from the front of the screen toward the back of the screen,
Storing sort data in a storage device including a depth value that is a function of a screen depth for a polygon that is a drawing object;
Reading the sort data from the storage device;
Comparing the depth value of the read sort data with the reference depth value to determine the drawing order;
When repeatedly reading the sorting data from the storage device, the step of controlling the reading of the sorting data according to the sorting data for which the drawing order is determined;
Sort processing method having The sort processing method according to claim 9, wherein the controlling step updates the read address of the storage device. The sorting data is read in units of blocks, and when the drawing order of all the sorting data in the block is determined, the reading is controlled so that the block is excluded from the reading target. Sort processing method described in 1. 12. The sort processing method according to claim 10, wherein the reading step reads the sort data from the read start address according to the read end address, and the controlling step updates at least one of the start address and the end address. .

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