JP2006279085A - Method of manufacturing circuit device - Google Patents

Method of manufacturing circuit device Download PDF

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Publication number
JP2006279085A
JP2006279085A JP2006194079A JP2006194079A JP2006279085A JP 2006279085 A JP2006279085 A JP 2006279085A JP 2006194079 A JP2006194079 A JP 2006194079A JP 2006194079 A JP2006194079 A JP 2006194079A JP 2006279085 A JP2006279085 A JP 2006279085A
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separation groove
plasma
manufacturing
circuit device
conductive foil
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JP2006194079A
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Ryosuke Usui
良輔 臼井
Hideki Mizuhara
秀樹 水原
Yuusuke Igarashi
優助 五十嵐
Noriaki Sakamoto
則明 坂本
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
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Priority to JP2006194079A priority Critical patent/JP2006279085A/en
Publication of JP2006279085A publication Critical patent/JP2006279085A/en
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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Abstract

<P>PROBLEM TO BE SOLVED: To improve adhesion between a conductive pattern 21 and sealing resin 28 by making the surface of the conductive pattern 21 coarse using plasma. <P>SOLUTION: Conductive foil 10 is selectively etched to form isolating trenches 11, thereby forming the conductive pattern 21. Circuit elements such as semiconductor elements 22A are mounted at desired places of the conductive pattern 21 to electrically connect with the conductive pattern 21. The surface of the isolating trench 11 is made coarse by irradiating plasma from above the conductive foil 10, resulting in improving adhesion strength between the sealing resin 28 filled in the isolating trench 11 and the conductive pattern 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は回路装置の製造方法に関し、特に、導電箔にプラズマを照射することにより、その表面に付着した残査を除去する回路装置の製造方法に関する。   The present invention relates to a method for manufacturing a circuit device, and more particularly, to a method for manufacturing a circuit device that removes residues adhering to the surface of a conductive foil by irradiating with plasma.

従来、電子機器にセットされる回路装置は、携帯電話、携帯用のコンピュータ等に採用されるために小型化・薄型化・軽量化が求められている。例えば、回路装置としての半導体装置では、このような要求を満たすために、ＣＳＰ（Chip size package）と呼ばれる、チップサイズと同等若しくは若干大きいサイズの半導体装置が開発されている。しかしながら一般的なＣＳＰでは、装置全体を支持するために、ガラスエポキシ基板やセラミック基板等の支持基板が必須の構成要素であった。このことから、支持基板が厚い部材であるために半導体装置全体のサイズが大きくなってしまう等の問題があった。   2. Description of the Related Art Conventionally, circuit devices set in electronic devices are required to be reduced in size, thickness, and weight in order to be used in mobile phones, portable computers, and the like. For example, in a semiconductor device as a circuit device, in order to satisfy such a requirement, a semiconductor device called a CSP (Chip size package) having a size equal to or slightly larger than the chip size has been developed. However, in a general CSP, a support substrate such as a glass epoxy substrate or a ceramic substrate is an essential component in order to support the entire apparatus. For this reason, since the support substrate is a thick member, there is a problem that the size of the entire semiconductor device is increased.

上記のような問題を鑑みて、支持基板を不要にした回路装置が開発された（例えば、特許文献１を参照）。以下にてその回路装置の製造方法を説明する。   In view of the above problems, a circuit device that does not require a support substrate has been developed (see, for example, Patent Document 1). A method for manufacturing the circuit device will be described below.

図１０（Ａ）を参照して、銅等の金属から成る導電箔１００を用意し、所定の電気回路が実現されるような導電パターン１００Ａを形成する。分離溝を形成する手法としては、耐エッチングマスクを用いた公知のエッチング工程で行うことができる。   Referring to FIG. 10A, a conductive foil 100 made of a metal such as copper is prepared, and a conductive pattern 100A that realizes a predetermined electric circuit is formed. As a method for forming the separation groove, a known etching process using an etching resistant mask can be used.

図１０（Ｂ）を参照して、導電パターン１００Ａの表面に回路素子を固着する。回路素子としては、コンデンサや抵抗等のチップ部品１０３および半導体素子１０２等が固着される。更に、半導体素子１０２の電極と導電パターン１００Ａとは、金属細線を介して電気的に接続される。   Referring to FIG. 10B, a circuit element is fixed to the surface of conductive pattern 100A. As circuit elements, a chip component 103 such as a capacitor and a resistor, a semiconductor element 102, and the like are fixed. Furthermore, the electrode of the semiconductor element 102 and the conductive pattern 100A are electrically connected through a fine metal wire.

図１０（Ｃ）を参照して、封止樹脂１０５による被覆を行う。前工程で固着された回路素子は被覆され、導電箔１００の分離溝１０１にも封止樹脂１０５が充填される。   With reference to FIG. 10C, coating with the sealing resin 105 is performed. The circuit element fixed in the previous process is covered, and the separation groove 101 of the conductive foil 100 is also filled with the sealing resin 105.

図１０（Ｄ）を参照して、導電箔１００を裏面からエッチングを行い、分離溝１０１に充填された封止樹脂１０５が露出するまで、導電箔１００の除去を行う。このことにより、各導電パターン１００Ａは電気的に分離される。更に、ソルダーレジストの形成、外部電極の形成等を行う。最後に、一点鎖線の箇所で封止樹脂１０５をダイシングすることにより、各回路装置を分離する。上記のような工程で、支持基板を不要にした回路装置が製造されていた。   Referring to FIG. 10D, the conductive foil 100 is etched from the back surface, and the conductive foil 100 is removed until the sealing resin 105 filled in the separation groove 101 is exposed. As a result, the conductive patterns 100A are electrically separated. Further, solder resist formation, external electrode formation, and the like are performed. Finally, each circuit device is separated by dicing the sealing resin 105 at the dot-and-dash line. In the process as described above, a circuit device that does not require a support substrate has been manufactured.

また、金属から成るパターンの表面に付着した汚染物質の除去等を行う技術として、プラズマ照射の技術がある。図１１を参照して、半導体装置が実装されたリードフレームにプラズマを照射して、表面に付着した汚染物質を除去する方法を説明する。   Further, there is a plasma irradiation technique as a technique for removing contaminants attached to the surface of a pattern made of metal. With reference to FIG. 11, a method of removing contaminants attached to the surface by irradiating plasma to a lead frame on which a semiconductor device is mounted will be described.

図１１（Ａ）を参照して、リードフレームの加工を行う工程および素子の実装工程等を経たリードフレーム１１０の構成を説明する。ランド状に形成されたアイランド１１４には半導体素子１１２が実装され、アイランド１１４を囲むように多数個のリード１１１が設けられている。また、リード１１１は半導体素子１１２の表面に設けた電極に対応しており、金属細線１１３を介して各電極はリード１１１と電気的に接続されている。   With reference to FIG. 11A, the structure of the lead frame 110 that has undergone a lead frame processing step, an element mounting step, and the like will be described. A semiconductor element 112 is mounted on the island 114 formed in a land shape, and a large number of leads 111 are provided so as to surround the island 114. The lead 111 corresponds to an electrode provided on the surface of the semiconductor element 112, and each electrode is electrically connected to the lead 111 through a fine metal wire 113.

図１１（Ｂ）を参照して、プラズマ照射を行う工程を説明する。先ず、密閉された容器内部にリードフレーム１１０を載置する。次に、容器内部にガスを導入して、放電によりプラズマガスを生成する。そしてプラズマガス中に存在するラジカルまたはイオンが、リードフレーム１１０の表面に衝突することによりリードフレーム１１０表面の洗浄が行われる。
特開２００２−０７６２４６号公報（第７頁、第１図） With reference to FIG. 11B, a step of performing plasma irradiation will be described. First, the lead frame 110 is placed inside a sealed container. Next, a gas is introduced into the container, and plasma gas is generated by discharge. Then, radicals or ions present in the plasma gas collide with the surface of the lead frame 110, whereby the surface of the lead frame 110 is cleaned.
JP 2002-076246 A (page 7, FIG. 1)

しかしながら、上記した回路装置の製造方法では、樹脂封止を行うまでの工程等の為に、導電箔１００の表面が汚染されてしまう問題があった。この汚染物質としては、分離溝１０１の形成工程で使用するエッチャントに含まれる有機性の残査や、空気中の埃等が考えられる。更に、上記のような汚染物質が導電箔１００の表面に付着したまま封止樹脂１０５の封止を行うと、封止樹脂１０５と導電箔１００との付着力が低下してしまう恐れがあった。   However, the above-described method for manufacturing a circuit device has a problem that the surface of the conductive foil 100 is contaminated due to a process until resin sealing is performed. As this contaminant, the organic residue contained in the etchant used in the step of forming the separation groove 101, dust in the air, and the like can be considered. Furthermore, if the sealing resin 105 is sealed while the contaminants as described above are attached to the surface of the conductive foil 100, the adhesion between the sealing resin 105 and the conductive foil 100 may be reduced. .

また、図１１に示したようなプラズマ照射によるリードフレームの洗浄方法では、アイランド１１４やリード１１１が形成されるように複雑な形状に加工されているため、プラズマ照射によりリードフレーム１１０に局所的な電位の増加が発生する。このことから、リードフレームの局所的な電位差により、金属細線１１３を介して半導体素子１１２に電流が流れ込み、半導体素子表面に形成されたＣＭＯＳ等の素子が破壊されてしまう問題があった。更に、プラズマ照射の工程でリードフレーム１１０が高温となることから、リードが変形して、金属細線１１３が断線してしまう問題があった。   Further, in the lead frame cleaning method by plasma irradiation as shown in FIG. 11, since the island 114 and the lead 111 are processed into a complicated shape, the lead frame 110 is locally exposed to the plasma irradiation. An increase in potential occurs. For this reason, there is a problem that a current flows into the semiconductor element 112 through the fine metal wire 113 due to a local potential difference of the lead frame, and an element such as a CMOS formed on the surface of the semiconductor element is destroyed. Further, since the lead frame 110 becomes high temperature in the plasma irradiation process, there is a problem that the lead is deformed and the metal thin wire 113 is disconnected.

本発明はこのような問題を鑑みて成されたものであり、本発明の主な目的は、導電箔の表面にプラズマを照射することにより導電箔表面の洗浄および粗化を行う回路装置の製造方法を提供することにある。更に、本発明の主な目的は、プラズマを用いて導電性材料の表面に付着した汚染物質を除去する際に発生する半導体素子の破壊等の問題を解決する回路装置の製造方法を提供することにある。   The present invention has been made in view of such problems, and the main object of the present invention is to manufacture a circuit device that cleans and roughens the surface of the conductive foil by irradiating the surface of the conductive foil with plasma. It is to provide a method. Furthermore, the main object of the present invention is to provide a method of manufacturing a circuit device that solves problems such as destruction of semiconductor elements that occur when removing contaminants attached to the surface of a conductive material using plasma. It is in.

本発明の回路装置の製造方法は、表面から分離溝が形成されることにより凸状の導電パターンが設けられた導電箔を導電部材の材料として用いる回路装置の製造方法に於いて、前記導電箔の上方から前記分離溝を含む前記導電箔の表面にプラズマを照射して、前記分離溝の側面を粗化することを特徴とする。   The method for manufacturing a circuit device according to the present invention is the method for manufacturing a circuit device in which a conductive foil provided with a convex conductive pattern by forming a separation groove from the surface is used as a material for a conductive member. The surface of the conductive foil including the separation groove is irradiated with plasma from above to roughen the side surface of the separation groove.

更に、本発明の回路装置の製造方法は、導電箔に表面から分離溝を形成して凸状の導電パターンを形成する工程と、前記導電パターンに回路素子を電気的に接続する工程と、前記導電箔の上方から前記分離溝を含む前記導電箔の表面にプラズマを照射して、前記分離溝の側面を粗化する工程と、前記回路素子を被覆し且つ前記分離溝に充填されるように封止樹脂で封止する工程とを具備することを特徴とする。   Furthermore, the method for manufacturing a circuit device of the present invention includes a step of forming a separation groove from the surface of the conductive foil to form a convex conductive pattern, a step of electrically connecting a circuit element to the conductive pattern, A step of irradiating the surface of the conductive foil including the separation groove with plasma from above the conductive foil to roughen the side surface of the separation groove; and covering the circuit element and filling the separation groove And a step of sealing with a sealing resin.

本発明によれば、導電箔の上方から進入するプラズマのイオンにより、分離溝の側面を粗化することができる。従って、この導電箔から形成される導電パターンと封止樹脂との密着強度を向上させて、品質に優れた回路装置を製造することができる。   According to the present invention, the side surface of the separation groove can be roughened by plasma ions entering from above the conductive foil. Therefore, it is possible to improve the adhesion strength between the conductive pattern formed from the conductive foil and the sealing resin, and to manufacture a circuit device with excellent quality.

本発明の回路装置の製造方法は、導電箔１０に表面から分離溝１１を形成して底部で一体に連結された導電パターン２１を形成する工程と、導電パターン２１の所望の箇所に回路素子２２を実装する工程と、回路素子２２を被覆し且つ分離溝１１に充填されるように封止樹脂２８で封止する工程とを有し、導電箔１０の表面にプラズマを照射することにより回路装置を製造する。プラズマの照射には２つの方法があり、第１の方法は回路素子２２の実装を行う前にプラズマ照射を行う方法であり、第２の方法は回路素子２２の実装を行った後にプラズマ照射を行う方法である。以下に上記した各工程の詳細を説明する。   The method for manufacturing a circuit device according to the present invention includes a step of forming a separation groove 11 on the conductive foil 10 from the surface and forming a conductive pattern 21 integrally connected at the bottom, and a circuit element 22 at a desired location of the conductive pattern 21. A circuit device by covering the circuit element 22 and sealing with a sealing resin 28 so as to fill the separation groove 11 and irradiating the surface of the conductive foil 10 with plasma. Manufacturing. There are two methods for plasma irradiation. The first method is a method in which plasma irradiation is performed before the circuit element 22 is mounted. The second method is a method in which plasma irradiation is performed after the circuit element 22 is mounted. How to do it. Details of each of the above steps will be described below.

本発明の第１の工程は、図１から図３に示すように、導電箔１０に表面から分離溝１１を形成して底部で一体に連結された導電パターン２１を形成する工程である。   As shown in FIGS. 1 to 3, the first step of the present invention is a step of forming a conductive pattern 21 integrally formed at the bottom by forming a separation groove 11 on the conductive foil 10 from the surface.

本工程では、まず図１（Ａ）の如く、シート状の導電箔１０を用意する。この導電箔１０は、ロウ材の付着性、ボンディング性、メッキ性が考慮されてその材料が選択され、材料としては、Ｃｕを主材料とした導電箔、Ａｌを主材料とした導電箔またはＦｅ−Ｎｉ等の合金から成る導電箔等が採用される。   In this step, first, a sheet-like conductive foil 10 is prepared as shown in FIG. The conductive foil 10 is selected in consideration of the adhesiveness, bonding property, and plating property of the brazing material. As the material, a conductive foil mainly composed of Cu, a conductive foil mainly composed of Al, or Fe is used. A conductive foil made of an alloy such as Ni is employed.

具体的には、図１（Ｂ）に示す如く、短冊状の導電箔１０に多数の搭載部が形成されるブロック１２が４〜５個離間して並べられる。各ブロック１２間にはスリット１３が設けられ、モールド工程等での加熱処理で発生する導電箔１０の応力を吸収する。また導電箔１０の上下周端にはインデックス孔１４が一定の間隔で設けられ、各工程での位置決めに用いられる。続いて、ブロック毎の導電パターン２１を形成する。   Specifically, as shown in FIG. 1B, 4 to 5 blocks 12 in which a large number of mounting portions are formed are arranged on the strip-shaped conductive foil 10 so as to be spaced apart. A slit 13 is provided between each block 12 to absorb the stress of the conductive foil 10 generated by heat treatment in a molding process or the like. In addition, index holes 14 are provided at regular intervals at the upper and lower peripheral ends of the conductive foil 10 and are used for positioning in each step. Subsequently, a conductive pattern 21 for each block is formed.

まず、図２に示す如く、導電箔１０の上に、ホトレジスト（耐エッチングマスク）ＰＲを形成し、導電パターン２１となる領域を除いた導電箔１０が露出するようにホトレジストＰＲをパターニングする。そして、図３（Ａ）に示す如く、ホトレジストＰＲを介して導電箔１０を選択的にエッチングする。エッチングにより形成された分離溝１１の深さは、例えば５０μｍであり、その側面は、粗面となるため封止樹脂２８との接着性が向上される。   First, as shown in FIG. 2, a photoresist (etching resistant mask) PR is formed on the conductive foil 10, and the photoresist PR is patterned so that the conductive foil 10 excluding the region to be the conductive pattern 21 is exposed. Then, as shown in FIG. 3A, the conductive foil 10 is selectively etched through the photoresist PR. The depth of the separation groove 11 formed by etching is, for example, 50 μm, and its side surface is a rough surface, so that the adhesiveness with the sealing resin 28 is improved.

またこの分離溝１１の側壁は、除去方法により異なる構造となる。この除去工程は、ウェットエッチング、ドライエッチング、レーザによる蒸発、ダイシングが採用できる。ウェットエッチングの場合、エッチャントは、塩化第二鉄または塩化第二銅が主に採用され、導電箔１０は、このエッチャントの中にディッピングされるか、このエッチャントでシャワーリングされる。ここでウェットエッチングは、一般に非異方性にエッチングされるため、側面は湾曲構造になる。   Further, the side wall of the separation groove 11 has a different structure depending on the removal method. This removal process can employ wet etching, dry etching, laser evaporation, and dicing. In the case of wet etching, ferric chloride or cupric chloride is mainly used as the etchant, and the conductive foil 10 is dipped in the etchant or showered with the etchant. Since wet etching is generally non-anisotropic, the side surface has a curved structure.

図３（Ｂ）に具体的な導電パターン２１を示す。本図は図１（Ｂ）で示したブロック１２の１個を拡大したものに対応する。点線で囲まれた部分の１個が１つの搭載部１５であり、導電パターン２１を構成し、１つのブロック１２には５行１０列のマトリックス状に多数の搭載部１５が配列され、各搭載部１５毎に同一の導電パターン２１が設けられている。   A specific conductive pattern 21 is shown in FIG. This figure corresponds to an enlarged view of one of the blocks 12 shown in FIG. One of the parts surrounded by a dotted line is one mounting part 15, which constitutes a conductive pattern 21. A plurality of mounting parts 15 are arranged in a matrix of 5 rows and 10 columns in one block 12, and each mounting part 15 is mounted. The same conductive pattern 21 is provided for each portion 15.

本発明の第２の工程は、図４に示す如く、導電パターン２１の所望の箇所に回路素子２２を実装することにある。回路素子２２としては、トランジスタ、ダイオード、ＩＣチップ等の半導体素子、チップコンデンサ、チップ抵抗等の受動素子である。また厚みが厚くはなるが、ＣＳＰ、ＢＧＡ等のフェイスダウンの半導体素子も実装できる。   The second step of the present invention is to mount a circuit element 22 at a desired location of the conductive pattern 21 as shown in FIG. The circuit element 22 is a semiconductor element such as a transistor, a diode, or an IC chip, or a passive element such as a chip capacitor or a chip resistor. Although the thickness is increased, face-down semiconductor elements such as CSP and BGA can also be mounted.

ここでは、ベアの半導体素子２２Ａが導電パターン２１にダイボンディングされ、半導体素子２２Ａの電極と導電パターン２１とが金属細線を介して電気的に接続されている。また２２Ｂは、チップコンデンサまたは受動素子等のチップ部品２２Ｂであり、半田等のロウ材２４等の導電ペーストで固着される。   Here, the bare semiconductor element 22A is die-bonded to the conductive pattern 21, and the electrode of the semiconductor element 22A and the conductive pattern 21 are electrically connected through a fine metal wire. Reference numeral 22B denotes a chip component 22B such as a chip capacitor or a passive element, which is fixed with a conductive paste such as a brazing material 24 such as solder.

本発明の第３の工程は、図５を参照して、導電箔１０表面に回路素子２２を含めてプラズマを照射することにより洗浄を行うことにある。図５（Ａ）はプラズマ洗浄を行う概要を示す図であり、図５（Ｂ）は１つの搭載部１５にプラズマ照射を行う様子を示す断面図である。   The third step of the present invention is to perform cleaning by irradiating plasma on the surface of the conductive foil 10 including the circuit element 22 with reference to FIG. FIG. 5A is a view showing an outline of performing plasma cleaning, and FIG. 5B is a cross-sectional view showing a state in which plasma is applied to one mounting portion 15.

図５（Ａ）を参照して、プラズマ照射による洗浄を説明する。プラズマ洗浄機３０は、密閉容器３４の内部に設けた上段電極３１と、上段電極３１に対向して設けられて上部に導電箔１０が載置される下段電極３２とを有している。また、ガスを容器内部に供給する注入口３５と、その排気を行う排気口３６が設けられている。上段電極３１と下段電極３２のどちらかは、高周波電源と接続されており、電源と接続されない電極は接地されている。   With reference to FIG. 5A, cleaning by plasma irradiation will be described. The plasma cleaner 30 has an upper electrode 31 provided inside the sealed container 34 and a lower electrode 32 provided opposite to the upper electrode 31 and on which the conductive foil 10 is placed. An inlet 35 for supplying gas into the container and an exhaust port 36 for exhausting the gas are provided. Either the upper electrode 31 or the lower electrode 32 is connected to a high frequency power source, and the electrode not connected to the power source is grounded.

導電箔表面の汚染物質を行うプラズマ洗浄は、化学的エッチングと物理的エッチングの２つの方法がある。化学的エッチングにはＤＰ（Direct Plazma）またはＰＥ（Plazma Etching）が含まれ、ガスとして酸素を使用することができる。物理・化学的エッチングにはＲＩＥ（Reactive Ion Etching）が含まれ、ガスとしてアルゴン、ネオンまたはヘリウムを使用することができる。化学的エッチングでは化学的効果を使用して有機物の汚染物質を除去することができ、物理的エッチングではスパッタ効果で有機物および無機物の汚染物質を除去することができる。本発明では、どちらの手法も用いることが可能である。   There are two methods of plasma cleaning for conducting contaminants on the surface of the conductive foil: chemical etching and physical etching. Chemical etching includes DP (Direct Plazma) or PE (Plazma Etching), and oxygen can be used as a gas. Physical / chemical etching includes RIE (Reactive Ion Etching), and argon, neon, or helium can be used as a gas. Chemical etching can remove organic contaminants using chemical effects, and physical etching can remove organic and inorganic contaminants using sputtering effects. In the present invention, either method can be used.

図５（Ｂ）を参照して、プラズマによる洗浄の詳細を説明する。本発明では、プラズマの照射は、導電箔１０の全域に渡って行われる。具体的には、放電により生成されたプラズマ３３の中のイオンを、導電箔１０の表面全域に衝突させている。従って、導電パターン２１の表面、分離溝１１、回路素子２２および金属細線２５にイオンが衝突して、それらの表面に付着した有機性または無機性の汚染物質が除去される。   The details of cleaning with plasma will be described with reference to FIG. In the present invention, the plasma irradiation is performed over the entire area of the conductive foil 10. Specifically, ions in the plasma 33 generated by the discharge collide with the entire surface of the conductive foil 10. Accordingly, ions collide with the surface of the conductive pattern 21, the separation groove 11, the circuit element 22, and the fine metal wire 25, and organic or inorganic contaminants attached to these surfaces are removed.

分離溝１１の側面には、エッチングの工程に用いたエッチャントの残査や空気中の埃等の汚染物質が付着しており、これらの汚染物質もプラズマ洗浄により除去される。また、分離溝１１はエッチングにより形成されているのでその側面は曲面と成っている。従って、上方から進入したイオンは、分離溝１１の側面で反射されるので、１つのイオンが幾度も分離溝１１の側面に衝突する。このことから、分離溝１１の側面では、イオンによる表面の洗浄の効果が大きいので、分離溝１１の側面に付着した有機性および無機性の汚染物質は除去される。   Contaminants such as residual etchant used in the etching process and dust in the air adhere to the side surfaces of the separation groove 11 and these contaminants are also removed by plasma cleaning. Further, since the separation groove 11 is formed by etching, its side surface is a curved surface. Accordingly, ions entering from above are reflected by the side surface of the separation groove 11, so that one ion collides with the side surface of the separation groove 11 several times. From this, on the side surface of the separation groove 11, the effect of cleaning the surface by ions is great, so that organic and inorganic contaminants attached to the side surface of the separation groove 11 are removed.

また、各導電パターン２１は、１枚の金属箔である導電箔１０に浅い分離溝１１を形成することによりパターン化されおり、一体に連結されている。従って、各導電パターン２１は、電気的にも一体化した導電箔１０の状態で保持されているので、プラズマの影響下に晒されても各導電パターンによる電位差の発生は抑制される。このことから、半導体素子２２Ａが電圧破壊し易いＣＭＯＳ等であっても、半導体素子２２Ａに与えるダメージを最小に抑制することができる。   In addition, each conductive pattern 21 is patterned by forming a shallow separation groove 11 in the conductive foil 10 that is a single metal foil, and is integrally connected. Therefore, since each conductive pattern 21 is held in the state of the electrically conductive foil 10 that is electrically integrated, generation of a potential difference due to each conductive pattern is suppressed even when exposed to the influence of plasma. For this reason, even if the semiconductor element 22A is a CMOS or the like that is susceptible to voltage breakdown, damage to the semiconductor element 22A can be minimized.

更に、プラズマ洗浄により、分離溝１１の側面は粗化される。従って、後の工程で形成される封止樹脂２８と分離溝１１の側面との密着性は向上される。ここで、分離溝１１の側面は導電パターン２１側面であるので、導電パターン２１と封止樹脂２８との密着性は向上し、導電パターン２１の剥離等を防止することができる。   Further, the side surface of the separation groove 11 is roughened by plasma cleaning. Therefore, the adhesion between the sealing resin 28 formed in a later step and the side surface of the separation groove 11 is improved. Here, since the side surface of the separation groove 11 is the side surface of the conductive pattern 21, adhesion between the conductive pattern 21 and the sealing resin 28 is improved, and peeling of the conductive pattern 21 can be prevented.

更にまた、プラズマ洗浄により、導電パターン２１は加熱されるが、導電パターン２１は導電箔１０として一体に成っているので、導電パターン２１の局所的な熱膨張や変形は防止される。従って、導電パターン２１の膨張や変形による金属細線２５の折れ曲がりや断線を抑止することができる。   Furthermore, although the conductive pattern 21 is heated by the plasma cleaning, since the conductive pattern 21 is integrally formed as the conductive foil 10, local thermal expansion and deformation of the conductive pattern 21 are prevented. Therefore, bending or disconnection of the fine metal wire 25 due to expansion or deformation of the conductive pattern 21 can be suppressed.

更に、プラズマ洗浄行うためのガスに酸素を混入させることにより、導電箔１０の表面を酸化させることができる。このように表面を酸化させることにより、封止樹脂２８と導電パターン２１との密着力を更に向上させることができる。   Furthermore, the surface of the conductive foil 10 can be oxidized by mixing oxygen into the gas for plasma cleaning. By oxidizing the surface in this way, the adhesion between the sealing resin 28 and the conductive pattern 21 can be further improved.

図５（Ｃ）を参照して、以上の本工程の説明では、回路素子２２が実装された導電箔１０に対してプラズマ照射を行ったが、回路素子２２の実装を行う前に導電箔１０に対してプラズマ照射を行うことも可能である。回路素子２２が実装されていない状態でプラズマ照射を行うことにより、導電箔１０の表面全域に渡ってプラズマの照射を行うことができる。即ち、図示されたような状態では、プラズマ照射を行う導電箔１０の表面および分離溝１１と、上段電極３１との間にプラズマ照射を遮断するものがない。このことから、導電箔１０の表面および分離溝１１は全面的にプラズマ照射が行われ、それらの表面の汚染物質の除去および表面の粗化が行われる。   With reference to FIG. 5C, in the above description of this process, plasma irradiation was performed on the conductive foil 10 on which the circuit element 22 was mounted. However, before the circuit element 22 was mounted, the conductive foil 10 was It is also possible to irradiate with plasma. By performing plasma irradiation in a state where the circuit element 22 is not mounted, it is possible to perform plasma irradiation over the entire surface of the conductive foil 10. In other words, in the state shown in the figure, there is nothing that blocks the plasma irradiation between the surface of the conductive foil 10 that performs plasma irradiation and the separation groove 11 and the upper electrode 31. Thus, the surface of the conductive foil 10 and the separation groove 11 are entirely irradiated with plasma, and contaminants on the surface are removed and the surface is roughened.

本発明の第４の工程は、図６を参照して、回路素子２２を被覆し、分離溝１１に封止樹脂２８が充填されるように封止樹脂２８による封止を行うことにある。   The fourth step of the present invention is to perform sealing with the sealing resin 28 so as to cover the circuit element 22 and fill the separation groove 11 with the sealing resin 28 with reference to FIG.

図６（Ａ）を参照して、樹脂封止が行われた後の状態を説明する。封止樹脂２８は回路素子２２および複数の導電パターン２１を被覆し、導電パターン２１間の分離溝１１には封止樹脂２８が充填されて各導電パターン２１の側面の湾曲構造と嵌合して強固に結合する。そして封止樹脂２８により導電パターン２１が支持されている。また本工程では、エポキシ樹脂等の熱硬化性樹脂を用いてトランスファーモールドを行うことができる。本工程によるメリットは、封止樹脂２８を被覆するまでは、導電パターン２１となる導電箔１０が支持基板となることである。そのため、構成材料を極力省いて作業できるメリットを有し、コストの低下も実現できる。   With reference to FIG. 6 (A), the state after resin sealing is performed is demonstrated. The sealing resin 28 covers the circuit elements 22 and the plurality of conductive patterns 21, and the separation grooves 11 between the conductive patterns 21 are filled with the sealing resin 28 and are fitted to the curved structures on the side surfaces of the respective conductive patterns 21. Bond firmly. The conductive pattern 21 is supported by the sealing resin 28. In this step, transfer molding can be performed using a thermosetting resin such as an epoxy resin. The merit by this process is that the conductive foil 10 which becomes the conductive pattern 21 becomes a support substrate until the sealing resin 28 is covered. Therefore, there is a merit that the work can be performed with the constituent materials omitted as much as possible, and the cost can be reduced.

次に図７を参照して、分離溝１１を設けていない厚み部分の導電箔１０を除去することにより、各導電パターン２１を電気的に分離する。具体的には、分離溝１１を設けていない厚み部分の導電箔１０のブロック１２の少なくとも導電パターン２１を設けた領域を除去する。本工程では、図７に示すように封止樹脂２８が露出するまで、導電箔１０の裏面を全面的にエッチングを行う。その結果、封止樹脂２８に導電パターン２１の裏面が露出する構造となる。   Next, referring to FIG. 7, each conductive pattern 21 is electrically separated by removing the thickness of the conductive foil 10 not provided with the separation groove 11. Specifically, at least the region provided with the conductive pattern 21 of the block 12 of the conductive foil 10 in the thickness portion where the separation groove 11 is not provided is removed. In this step, the entire back surface of the conductive foil 10 is etched until the sealing resin 28 is exposed as shown in FIG. As a result, the back surface of the conductive pattern 21 is exposed to the sealing resin 28.

本発明の第５の工程は、図８に示す如く、ブロック１２の封止樹脂２８を各搭載部１５毎にダイシングにより分離することにある。   The fifth step of the present invention is to separate the sealing resin 28 of the block 12 by dicing for each mounting portion 15 as shown in FIG.

本工程では、粘着シートに貼り付けられた複数個のブロック１２をダイシング装置の載置台に真空で吸着させ、ダイシングブレード４１で各搭載部１５間のダイシングライン４０に沿って分離溝１１の封止樹脂２８をダイシングし、個別の回路装置に分離する。   In this step, the plurality of blocks 12 attached to the pressure-sensitive adhesive sheet are vacuum-adsorbed to the mounting table of the dicing apparatus, and the dicing blade 41 seals the separation grooves 11 along the dicing lines 40 between the mounting portions 15. The resin 28 is diced and separated into individual circuit devices.

図９を参照して、上記のような工程で製造される回路装置の構成を説明する。同図に示す回路装置は、導電パターン２１と、導電パターン２１上に固着された回路素子２２と、半導体素子２２Ａと導電パターン２１とを電気的に接続する金属細線２５と、導電パターン２１の裏面を露出させて全体の支持および封止を行う封止樹脂２８とから構成されている。また、封止樹脂２８の裏面から露出する導電パターン２１はレジスト２６で被覆され、所望の箇所には半田等のロウ材から成る外部電極２７が形成されている。   With reference to FIG. 9, the structure of the circuit device manufactured by the above steps will be described. The circuit device shown in FIG. 1 includes a conductive pattern 21, a circuit element 22 fixed on the conductive pattern 21, a metal wire 25 that electrically connects the semiconductor element 22 </ b> A and the conductive pattern 21, and a back surface of the conductive pattern 21. And a sealing resin 28 that supports and seals the whole. The conductive pattern 21 exposed from the back surface of the sealing resin 28 is covered with a resist 26, and external electrodes 27 made of a brazing material such as solder are formed at desired locations.

本発明の回路装置の製造方法によると、以下に示すような効果を奏することができる。   According to the circuit device manufacturing method of the present invention, the following effects can be obtained.

第１に、導電パターン２１を分離する分離溝１１が形成された導電箔１０の表面にプラズマの照射を行うので、表面に付着した汚染物質の除去および表面の粗化を行うことができる。このことから、導電パターン２１と封止樹脂２８との密着を向上させることができる。   First, since the surface of the conductive foil 10 on which the separation groove 11 for separating the conductive pattern 21 is formed is irradiated with plasma, contaminants attached to the surface can be removed and the surface can be roughened. For this reason, the adhesion between the conductive pattern 21 and the sealing resin 28 can be improved.

第２に、プラズマ照射を回路素子２２の実装を行う前に行うことにより、導電箔１０の表面および分離溝１１に全面的にプラズマ照射を行うことが可能となり、汚染物質の除去および表面粗化の効果を更に向上させることができる。   Second, by performing plasma irradiation before mounting the circuit element 22, it is possible to perform plasma irradiation on the entire surface of the conductive foil 10 and the separation groove 11, thereby removing contaminants and surface roughening. This effect can be further improved.

第３に、回路素子２２の実装を行った後にプラズマ照射を行うことも可能である。導電パターン２１が導電箔１０として電気的にも一体化された状態でプラズマ洗浄を行うので、プラズマの影響により導電パターン２１に局所的な電位差が発生するのを抑制することができる。従って、プラズマの影響で発生した電位差により半導体素子２２Ａに与えるダメージを抑制することができる。また、金属細線２５および回路素子２２の表面の洗浄および粗化を行うこともできる。   Third, it is also possible to perform plasma irradiation after the circuit element 22 is mounted. Since the plasma cleaning is performed in a state where the conductive pattern 21 is electrically integrated as the conductive foil 10, it is possible to suppress the occurrence of a local potential difference in the conductive pattern 21 due to the influence of plasma. Therefore, damage to the semiconductor element 22A due to the potential difference generated by the influence of plasma can be suppressed. Moreover, the surface of the metal fine wire 25 and the circuit element 22 can be cleaned and roughened.

第４に、導電箔１０の上方から進入するイオンが、分離溝１１の側面で反射するので、プラズマ照射による汚染物除去の効果を更に向上させることができる。   Fourth, since ions entering from above the conductive foil 10 are reflected by the side surfaces of the separation groove 11, the effect of removing contaminants by plasma irradiation can be further improved.

第５に、プラズマにより分離溝１１の側面を粗化させることができるので、封止樹脂２８と導電パターン２１との密着性を更に向上させることができる。   Fifth, since the side surface of the separation groove 11 can be roughened by plasma, the adhesion between the sealing resin 28 and the conductive pattern 21 can be further improved.

第６に、分離溝１１の表面の付着物をプラズマ照射により除去できることから、分離溝１１に充填されて裏面に露出する封止樹脂２８の露出面に付着物が除去しない。従って、分離溝１１から露出する封止樹脂２８とレジスト２６との付着強度を強くすることができる。   Sixth, since the deposit on the surface of the separation groove 11 can be removed by plasma irradiation, the deposit is not removed on the exposed surface of the sealing resin 28 that is filled in the separation groove 11 and exposed on the back surface. Accordingly, the adhesion strength between the sealing resin 28 exposed from the separation groove 11 and the resist 26 can be increased.

尚、上記した実施の形態に含まれる本願発明は以下のものもある。   The present invention included in the above-described embodiments includes the following.

本発明は、導電箔に表面から分離溝を形成して底部で一体に連結された導電パターンを形成する工程と、前記導電パターンの所望の箇所に回路素子を実装する工程と、前記回路素子を被覆し且つ前記分離溝に充填されるように樹脂層で封止する工程とを有し、前記導電箔の表面にプラズマを照射する。導電箔の表面にプラズマを照射することにより、導電箔の表面に付着した汚染物質を除去することが可能となり、更に、導電箔の表面を粗化して絶縁性樹脂との密着を向上させることが可能となる。   The present invention includes a step of forming a separation pattern on the conductive foil from the surface and forming a conductive pattern integrally connected at the bottom, a step of mounting a circuit element at a desired location of the conductive pattern, and the circuit element Covering and sealing with a resin layer so as to fill the separation groove, and irradiating the surface of the conductive foil with plasma. By irradiating the surface of the conductive foil with plasma, it becomes possible to remove contaminants adhering to the surface of the conductive foil, and further, the surface of the conductive foil can be roughened to improve the adhesion with the insulating resin. It becomes possible.

更に本発明は、前記回路素子を実装する工程に先行して、前記プラズマの照射を行う。このように導電箔上に回路素子が実装されていない状態でプラズマ照射を行うことにより、導電箔全域に渡ってプラズマ照射を行うことができる。従って、回路素子が載置される予定の導電箔および分離溝の領域にプラズマ照射を行うことが可能となる。   In the present invention, the plasma irradiation is performed prior to the step of mounting the circuit element. Thus, by performing plasma irradiation in a state where no circuit element is mounted on the conductive foil, it is possible to perform plasma irradiation over the entire conductive foil. Accordingly, it is possible to perform plasma irradiation on the conductive foil and separation groove regions where circuit elements are to be placed.

更に、本発明は、導電箔に表面から分離溝を形成して底部で一体に連結された導電パターンを形成する工程と、前記導電パターンの所望の箇所に回路素子を実装する工程と、前記導電箔表面に前記回路素子を含めてプラズマを照射する工程と、前記回路素子を被覆し且つ前記分離溝に充填されるように樹脂層で封止する工程とを有する。本発明の導電パターンは、底部で連結されているので、プラズマを照射する工程に於いて局所的な電位差が発生せず、半導体素子等の回路素子が破壊されるのを抑制することができる。また、導電パターンが導電箔として一体に成っているので、プラズマ照射を行う工程で加熱されることによる変形が少ない。従って、回路素子と導電パターンとを接続する金属細線の変形・断線を抑制することができる。   Furthermore, the present invention includes a step of forming a separation groove on the conductive foil from the surface and forming a conductive pattern integrally connected at the bottom, a step of mounting a circuit element at a desired location of the conductive pattern, and the conductive There are a step of irradiating the foil surface with the plasma including the circuit element, and a step of covering the circuit element and sealing with a resin layer so as to fill the separation groove. Since the conductive patterns of the present invention are connected at the bottom, a local potential difference does not occur in the plasma irradiation step, and it is possible to suppress the destruction of circuit elements such as semiconductor elements. Moreover, since the conductive pattern is integrally formed as a conductive foil, there is little deformation due to heating in the process of plasma irradiation. Therefore, deformation and disconnection of the fine metal wire connecting the circuit element and the conductive pattern can be suppressed.

更に本発明は、前記プラズマにより、前記分離溝の表面に付着した汚染物質を除去する。照射されたプラズマは分離溝表面で反射するので、反射されたプラズマにより、その洗浄の効果は更に向上される。また、プラズマ照射により導電箔の表面は粗化され、導電パターンと絶縁性樹脂との密着性は向上される。   Furthermore, the present invention removes contaminants attached to the surface of the separation groove by the plasma. Since the irradiated plasma is reflected on the surface of the separation groove, the cleaning effect is further improved by the reflected plasma. Moreover, the surface of the conductive foil is roughened by plasma irradiation, and the adhesion between the conductive pattern and the insulating resin is improved.

本発明では、導電箔の表面にプラズマを照射することにより導電箔表面の洗浄および粗化を行うことができる。更に、プラズマを用いて導電性材料の表面に付着した汚染物質を除去する際に発生する半導体素子の破壊等の問題を解決することができる。   In the present invention, the surface of the conductive foil can be cleaned and roughened by irradiating the surface of the conductive foil with plasma. Furthermore, it is possible to solve problems such as destruction of a semiconductor element that occur when removing contaminants attached to the surface of the conductive material using plasma.

本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。It is sectional drawing (A) and a top view (B) explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。It is sectional drawing (A) and a top view (B) explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図（Ａ）、断面図（Ｂ）、断面図（Ｃ）である。It is sectional drawing (A), sectional drawing (B), and sectional drawing (C) explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図（Ａ）、平面図（Ｂ）である。It is sectional drawing (A) and a top view (B) explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. 本発明の回路装置の製造方法を説明する平面図である。It is a top view explaining the manufacturing method of the circuit device of this invention. 本発明の回路装置の製造方法を説明する断面図である。It is sectional drawing explaining the manufacturing method of the circuit apparatus of this invention. 従来の回路装置の製造方法を説明する断面図（Ａ）−（Ｄ）である。It is sectional drawing (A)-(D) explaining the manufacturing method of the conventional circuit device. 従来の回路装置の製造方法を説明する平面図（Ａ）、断面図（Ｂ）である。It is the top view (A) and sectional drawing (B) explaining the manufacturing method of the conventional circuit device.

符号の説明Explanation of symbols

１０ 導電箔
１１ 分離溝
１２ ブロック
２２Ａ 半導体素子
２２Ｂ チップ部品
２５ 金属細線
３０ プラズマ洗浄機
３１ 上段電極
３２ 下段電極
４０ ダイシングライン
４１ ブレード
DESCRIPTION OF SYMBOLS 10 Conductive foil 11 Separation groove 12 Block 22A Semiconductor element 22B Chip component 25 Metal thin wire 30 Plasma cleaning machine 31 Upper electrode 32 Lower electrode 40 Dicing line 41 Blade

Claims (12)

表面から分離溝が形成されることにより凸状の導電パターンが設けられた導電箔を導電部材の材料として用いる回路装置の製造方法に於いて、
前記導電箔の上方から前記分離溝を含む前記導電箔の表面にプラズマを照射して、前記分離溝の側面を粗化することを特徴とする回路装置の製造方法。 In a method of manufacturing a circuit device using a conductive foil provided with a convex conductive pattern by forming a separation groove from the surface as a material of a conductive member,
A method of manufacturing a circuit device, wherein the surface of the conductive foil including the separation groove is irradiated with plasma from above the conductive foil to roughen a side surface of the separation groove. 前記プラズマは、前記分離溝の側面に直に照射され、湾曲面である前記分離溝の側面で前記プラズマのイオンを反射させることを特徴とする請求項１記載の回路装置の製造方法。   The method of manufacturing a circuit device according to claim 1, wherein the plasma is directly irradiated on a side surface of the separation groove, and ions of the plasma are reflected on a side surface of the separation groove which is a curved surface. 前記プラズマの照射により、前記分離溝の側面に付着した汚染物質を除去することを特徴とする請求項１記載の回路装置の製造方法。   2. The method of manufacturing a circuit device according to claim 1, wherein contaminants adhering to a side surface of the separation groove are removed by the plasma irradiation. 前記イオンは、前記分離溝の側面に複数回衝突することを特徴とする請求項１記載の回路装置の製造方法。   The method of manufacturing a circuit device according to claim 1, wherein the ions collide with a side surface of the separation groove a plurality of times. 前記分離溝の断面は、上端部が内側にオーバーハングする湾曲形状であることを特徴とする請求項１記載の回路装置の製造方法。   2. The method of manufacturing a circuit device according to claim 1, wherein the cross section of the separation groove has a curved shape in which an upper end portion overhangs inward. 導電箔に表面から分離溝を形成して凸状の導電パターンを形成する工程と、
前記導電パターンに回路素子を電気的に接続する工程と、
前記導電箔の上方から前記分離溝を含む前記導電箔の表面にプラズマを照射して、前記分離溝の側面を粗化する工程と、
前記回路素子を被覆し且つ前記分離溝に充填されるように封止樹脂で封止する工程とを具備することを特徴とする回路装置の製造方法。 Forming a separation groove from the surface of the conductive foil to form a convex conductive pattern;
Electrically connecting a circuit element to the conductive pattern;
Irradiating plasma on the surface of the conductive foil including the separation groove from above the conductive foil to roughen the side surface of the separation groove;
Covering the circuit element and sealing with a sealing resin so as to fill the separation groove. 前記プラズマを照射する工程では、前記分離溝の側面に前記プラズマのイオンが直に照射され、湾曲面である前記分離溝の側面で前記プラズマのイオンを反射させることを特徴とする請求項６記載の回路装置の製造方法。   7. The plasma irradiating step includes directly irradiating the side surface of the separation groove with the plasma ions to reflect the plasma ion on the side surface of the separation groove which is a curved surface. Circuit device manufacturing method. 前記封止樹脂で封止する工程では、粗化された前記分離溝の側面に前記封止樹脂を密着させることを特徴とする請求項６記載の回路装置の製造方法。   The method for manufacturing a circuit device according to claim 6, wherein in the step of sealing with the sealing resin, the sealing resin is brought into close contact with the roughened side surface of the separation groove. 前記プラズマを照射する工程では、前記イオンは、前記分離溝の側面に複数回衝突することを特徴とする請求項６記載の回路装置の製造方法。   The method of manufacturing a circuit device according to claim 6, wherein in the step of irradiating the plasma, the ions collide with a side surface of the separation groove a plurality of times. 前記導電箔の裏面に前記封止樹脂が露出するまで、前記導電箔の裏面を除去することにより、前記各導電パターンを電気的に分離する工程を更に具備することを特徴とする請求項６記載の回路装置の製造方法。   7. The method of claim 6, further comprising the step of electrically separating the conductive patterns by removing the back surface of the conductive foil until the sealing resin is exposed on the back surface of the conductive foil. Circuit device manufacturing method. 前記分離溝の断面は、上端部が内側にオーバーハングする湾曲形状であることを特徴とする請求項６記載の回路装置の製造方法。   The method of manufacturing a circuit device according to claim 6, wherein a cross section of the separation groove has a curved shape with an upper end overhanging inward. 前記プラズマの照射により、前記分離溝の側面に付着した汚染物質を除去することを特徴とする請求項６記載の回路装置の製造方法。   The method of manufacturing a circuit device according to claim 6, wherein contaminants attached to a side surface of the separation groove are removed by the plasma irradiation.
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JP2017034078A (en) * 2015-07-31 2017-02-09 大分デバイステクノロジー株式会社 Semiconductor component manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017034078A (en) * 2015-07-31 2017-02-09 大分デバイステクノロジー株式会社 Semiconductor component manufacturing method

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