JP2006270109A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of designing a semiconductor integrated circuit which hardly causes timing error in the flip-flop even when production variations occur. <P>SOLUTION: In the method of designing the semiconductor integrated circuit, first, the type of a logic cell which can exist on the clock path is specified (S301). Next, the type of a logically equivalent cell for clock is specified corresponding to the type of a cell for non-clock (S302). Next, all clock paths are extracted from the semiconductor integrated circuit which should be designed (S303). And a step judges whether each logic cell is a cell for clock or a cell for non-clock, about all logic cells that exist on the extracted clock paths (S304). Then, the logic cell which is judged to be a cell for non-clock in the step S304, is replaced with the cell for clock specified corresponding to the type of the logic cell in the step S302 (S306). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that operates in synchronization with a clock signal and a design method thereof.

  Many semiconductor integrated circuits including a logic circuit operate in synchronization with an externally supplied clock signal or an internally generated clock signal based on an externally supplied signal. In general, a semiconductor integrated circuit includes a plurality of flip-flops and a circuit that generates a clock signal supplied to each flip-flop based on a given clock signal (hereinafter referred to as a clock circuit). In order for the semiconductor integrated circuit to operate correctly, it is necessary to correctly supply a clock signal to each flip-flop. In order to reduce the power consumption of the semiconductor integrated circuit, it is effective to stop the supply of the clock signal to the circuit block that is not operated. For this reason, the configuration of the clock circuit and the method for supplying the clock signal are recognized as important issues in the design of the semiconductor integrated circuit.

  When analyzing a clock circuit, paying attention to a path through which a clock signal flows (hereinafter referred to as a clock path) and a logic cell existing on the clock path in the clock circuit, and analyzing that part as a clock tree, Widely done. In this clock tree analysis, the time until a given clock signal reaches each flip-flop is calculated. After that, based on the analysis result of the clock tree, a buffer is added to the clock circuit so that the clock skew (the difference in time until the given clock signal reaches each flip-flop) becomes smaller than the predetermined allowable value. Alternatively, a process of deleting, a process of correcting the layout result, and the like are performed.

Various techniques are conventionally known for supplying a clock signal in a semiconductor integrated circuit. Among these, as a technique having relevance to the present invention, for example, there are those described in Patent Documents 1 to 3. Patent Document 1 describes an all-parallel A / D converter in which every other 1-bit comparator is laid out in the reverse direction. Patent Document 2 describes an inverter that can change a threshold voltage. Patent Document 3 describes that a clock signal is wired using the lowermost layer of a multilayer wiring layer.
Japanese Patent Laid-Open No. 62-190747 JP-A-4-284020 JP 2000-68380 A JP 2002-110802 A JP-A-9-74138 JP-A-2-110672 Japanese Patent Laid-Open No. 62-190747

  However, with the progress of circuit miniaturization and voltage reduction, a higher level of technology is required for supplying clock signals in semiconductor integrated circuits. For example, as the miniaturization progresses, the size of the transistors constituting the logic cell included in the clock circuit is reduced, so that the delay time of the clock circuit is more susceptible to manufacturing variations than in the past. In addition, as the miniaturization progresses, the scale of the clock circuit is increased, so that it takes more time for clock tree analysis and clock circuit design change than before. As the circuit scale of the clock circuit increases with the progress of miniaturization and voltage reduction, the delay time per logic cell stage included in the clock circuit decreases. It is necessary to set an appropriate design margin than before. In addition, recently, a circuit design that takes into account the delay time variation due to aging degradation is also performed, but since the clock signal is one of the most frequently changing signals, the delay time variation due to the aging degradation of the clock signal. It is necessary to design a semiconductor integrated circuit after correctly evaluating the above.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit having characteristics superior to those of the prior art in supplying a clock signal, and a method for designing such a semiconductor integrated circuit.

  The present invention is a method for designing a semiconductor integrated circuit that designates the types of logic cells that can exist on a clock path and determines whether or not the logic cells that exist on the clock path are the designated type of logic cells. . In particular, the type of logic cell that can exist on the clock path is specified in correspondence with the type of logic cell that cannot exist on the clock path, and it exists on the clock path that cannot exist on the clock path based on the above determination result. A type of logic cell may be replaced with a corresponding type of logic cell.

  According to the present invention, it is possible to easily verify that a logic cell existing on a clock path is a logic cell having a certain characteristic (for example, a logic cell resistant to process fluctuation). In addition, by specifying the types of logic cells that can exist on the clock path corresponding to the types of logic cells that cannot exist on the clock path, and replacing the logic cells that exist on the clock path, certain characteristics can be obtained. The clock circuit can be changed so that only logic cells that have it are on the clock path.

  Hereinafter, first to seventh embodiments of the present invention will be described with reference to the drawings. In each of the embodiments, in order to facilitate understanding of the invention, a description will be made by extracting and explaining main circuits necessary for understanding of the invention among circuits included in the semiconductor integrated circuit.

(First embodiment)
In the first embodiment of the present invention, a semiconductor integrated circuit in which logic cells included in a clock circuit are configured by transistors having a uniform size will be described. FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit shown in FIG. 1 includes a first clock circuit 11, a second clock circuit 12, a first flip-flop 13, a combinational circuit 14, and a second flip-flop 15. Both the first and second flip-flops 13 and 15 operate in synchronization with the applied clock signal CK. More specifically, the first clock circuit 11 generates the first clock signal CK1 based on the clock signal CK, and the first flip-flop 13 operates in synchronization with the first clock signal CK1. The second clock circuit 12 and the second flip-flop 15 operate in the same manner. The combinational circuit 14 generates a data input signal supplied to the second flip-flop 15 based on values stored in the first flip-flop 13 and other flip-flops (not shown).

  Each circuit included in the semiconductor integrated circuit includes one or more logic cells, and each logic cell includes one or more transistors. FIG. 2 is a layout diagram of a transistor. When viewed at the layout level, the transistor is formed at a location where the diffusion region 21 and the polysilicon region 22 overlap as shown in FIG. The characteristics of the transistor are determined by the size of the overlapping region between the diffusion region 21 and the polysilicon region 22 (channel width W and channel length L).

  As shown in FIG. 1, the first clock circuit 11 includes a logic cell 16, and the second clock circuit 12 includes a logic cell 17. In the semiconductor integrated circuit according to the present embodiment, the logic cell 16 included in the first clock circuit 11 and the logic cell 17 included in the second clock circuit 12 are configured by transistors having a uniform size. It is characterized by. The logic cell 16 and the logic cell 17 are typically configured by transistors having a uniform channel width W, but may be configured by transistors having a uniform channel width W and channel length L.

Hereinafter, in the semiconductor integrated circuit according to the present embodiment, the logic cell 16 included in the first clock circuit 11 and the logic cell 17 included in the second clock circuit 12 are configured by transistors having a uniform channel width W. The effect by being done is explained. In FIG. 1, the period of the clock signal CK is T, the delay time of the first clock circuit 11 is t1, the delay time of the second clock circuit 12 is t2, the delay time of the combinational circuit 14 and the first flip-flop 13 The sum of the delay time from the clock signal to the data output signal is td, and the setup time and hold time of the second flip-flop 15 are ts and th, respectively. In this case, in order for the second flip-flop 15 to operate correctly in synchronization with the second clock signal CK2, the setup margin Ms shown in the following equation (1) and the hold margin Mh shown in the following equation (2) are , Both are required to be positive values greater than or equal to a predetermined value (see FIG. 3).
Ms = (t2-t1) + T-td-ts (1)
Mh = (t1-t2) + td-th (2)

  FIG. 4 is a diagram showing the relationship between the fluctuation amount of the channel width W and the fluctuation amount of the delay time for the transistors included in the semiconductor integrated circuit. FIG. 4A is a diagram showing a relationship regarding transistors included in a conventional semiconductor integrated circuit, and FIG. 4B is a diagram showing a relationship regarding transistors included in the semiconductor integrated circuit according to the present embodiment. It is.

  Here, first, it is assumed that a semiconductor integrated circuit having the same configuration as that of FIG. 1 is designed and manufactured using a conventional method. In a semiconductor integrated circuit according to a conventional technique, a logic cell included in a clock circuit is composed of transistors whose channel widths W are not unified. The design value of the channel width of the transistors constituting the logic cell 16 included in the first clock circuit 11 is W1, and the design value of the channel width of the transistors constituting the logic cell 17 included in the second clock circuit 12 is W2. In this case, it is assumed that W1 is larger than W2 and that in the manufactured semiconductor integrated circuit, the channel width of each transistor varies by ΔW from the design value due to manufacturing variations. In this case, the channel width of the manufactured transistor is (W1 + ΔW) in the logic cell 16 included in the first clock circuit 11, and (W2 + ΔW) in the logic cell 17 included in the second clock circuit 12, but W1. Is greater than W2, the variation rate of the channel width due to manufacturing variation is larger in the transistor included in the logic cell 17 than in the transistor included in the logic cell 16.

  For this reason, in the semiconductor integrated circuit according to the conventional method, when manufacturing variation occurs, the delay time t2 of the second clock circuit 12 varies more greatly than the delay time t1 of the first clock circuit 11 (FIG. 4). (See (a)). Therefore, when the measured value of the channel width becomes larger than the design value (that is, when ΔW is positive), the delay time t2 of the second clock circuit 12 is the delay time of the first clock circuit 11. It decreases more than t1. For this reason, the value of (t2-t1) in the above equation (1) becomes small, and the setup margin in the second flip-flop 15 becomes insufficient. On the other hand, when the actual channel width is smaller than the design value (that is, when ΔW is negative), the delay time t2 of the second clock circuit 12 is the delay time t1 of the first clock circuit 11. Increase more than. For this reason, the value of (t1-t2) in the above equation (2) becomes small, and the hold margin in the second flip-flop 15 becomes insufficient. As described above, when the logic cell included in the clock circuit includes transistors whose channel widths are not uniform, a timing error is likely to occur in the second flip-flop 15 due to manufacturing variations of the semiconductor integrated circuit.

  On the other hand, in the semiconductor integrated circuit according to the present embodiment, the logic cell included in the clock circuit is composed of transistors with a uniform channel width W. That is, the design value W1 of the channel width of the transistors constituting the logic cell 16 included in the first clock circuit 11 and the design value W2 of the channel width of the transistors constituting the logic cell 17 included in the second clock circuit 12 Always takes the same value. For this reason, even when manufacturing variation occurs, the delay time t1 of the first clock circuit 11 and the delay time t2 of the second clock circuit 12 increase or decrease by the same time (see FIG. 4B). ). Therefore, even if manufacturing variation occurs, the value of (t2-t1) in the above equation (1) and the value of (t1-t2) in the above equation (2) do not change from the design values. 15, the timing error is unlikely to occur.

  Therefore, according to the semiconductor integrated circuit according to the present embodiment, it is possible to obtain a semiconductor integrated circuit in which a timing error is unlikely to occur even when manufacturing variations occur. A semiconductor integrated circuit in which the logic cells included in the clock circuit are constituted by transistors having the same channel width W and channel length L also has the same effect.

  For the semiconductor integrated circuit according to the present embodiment, the following modifications can be configured. In the semiconductor integrated circuit according to this modification, in addition to the logic cells included in the clock circuit being configured by transistors having a uniform size, the logic cells included in the clock circuit are unified into a rectangular shape. It is characterized by comprising a transistor having a diffusion region 23 (FIG. 5A).

  Hereinafter, the effect of the semiconductor integrated circuit according to the present modification will be described with reference to FIG. FIG. 5B is a layout diagram of a transistor having a non-rectangular diffusion region 24. When a semiconductor integrated circuit including the transistor shown in FIG. 5B is manufactured, as shown in FIG. 5C, 270 degrees out of 360 degrees around the recessed vertex P of the diffusion area 24 is included in the diffusion area. An unnecessary diffusion region 25 (hatched region) is formed in a portion around the vertex) where a diffusion region should not be originally formed. Depending on the size and shape of the unnecessary diffusion region 25, the channel width W of the transistor may be affected, and the delay time of the circuit including the transistor may be affected.

  Therefore, for example, the logic cell 16 included in the first clock circuit 11 is configured by a transistor (FIG. 5A) having a rectangular diffusion region 23, and the logic cell included in the second clock circuit 12. 17 is constituted by a transistor (FIG. 5B) having a diffusion region 24 having a concave apex P, due to the influence of an unnecessary diffusion region 25 (FIG. 5C) formed during manufacturing, The difference between the delay time t1 of the first clock circuit 11 and the delay time t2 of the second clock circuit 12 may be different from the design value. As a result, the temporal relationship to be established between the delay time t1 of the first clock circuit 11 and the delay time t2 of the second clock circuit 12 is not satisfied, and the second flip-flop 15 or the like performs timing. Error is likely to occur.

  On the other hand, in the semiconductor integrated circuit according to this modification, the logic cell included in the clock circuit is configured by a transistor (FIG. 5A) having the diffusion region 23 unified in a rectangular shape. In the diffusion region having such a feature, the recessed vertex P as shown in FIG. 5C does not exist. Therefore, the unnecessary diffusion region 25 is not formed around the recessed vertex P. For this reason, the delay time t1 of the first clock circuit 11 and the delay time t2 of the second clock circuit 12 increase or decrease by the same time even when manufacturing variations occur. Therefore, according to the semiconductor integrated circuit according to the present modification, it is possible to obtain a semiconductor integrated circuit in which a timing error is less likely to occur than in the semiconductor integrated circuit according to the first embodiment.

(Second Embodiment)
In the second embodiment of the present invention, a method of designing a semiconductor integrated circuit that operates under a different operating condition using a circuit block that operates under a certain operating condition will be described. First, a method of designing a semiconductor integrated circuit (FIG. 6) that operates at a different threshold voltage using a circuit block that operates at a certain threshold voltage will be described. The semiconductor integrated circuit 30 shown in FIG. 6 includes a first half clock circuit 31, a circuit block 32, a second second half clock circuit 35, and a second flip-flop 36, and a certain threshold voltage (hereinafter referred to as a second threshold voltage VT2). ). The circuit block 32 includes a first second half clock circuit 33 and a first flip-flop 34, and originally operates at a threshold voltage different from the second threshold voltage VT2 (hereinafter referred to as the first threshold voltage VT1). It was designed as follows.

  In FIG. 6, each of the first and second flip-flops 34 and 36 operates in synchronization with a given clock signal CK. More specifically, the first half clock circuit 31 and the first second half clock circuit 33 generate a first clock signal CK1 based on the clock signal CK, and the first flip-flop 34 is synchronized with the first clock signal CK1. Works. The second second half clock circuit 35 and the second flip-flop 36 operate in the same manner.

  FIG. 7 is a flowchart showing a method for designing a semiconductor integrated circuit according to the present embodiment. Before executing the procedure shown in FIG. 7, as a logic cell used in the clock circuit, a logic cell (hereinafter referred to as a first clock cell) operating at a first threshold voltage V1, and a second threshold voltage. A logic cell (hereinafter referred to as a second clock cell) operating at V2 is prepared. At this time, between the first clock cell and the second clock cell, the same type of logic cell is set such that the input capacitance, the cell specific delay, and the driving capability are equal. In other words, the input capacity of the first clock cell is equal to the input capacity of the second clock cell, and the cell specific delay of the first clock cell is equal to the cell specific delay of the second clock cell. The driving capability of the first clock cell is set equal to the driving capability of the second clock cell. Note that the first clock cell and the second clock cell may be the same type of logic cell or may have different cell sizes.

  After the first and second clock cells having the above characteristics are prepared, the procedure shown in FIG. 7 is executed. First, the circuit block 32 that operates at the first threshold voltage VT1 is designed (step S101). At this time, the clock circuit included in the circuit block 32 (which later becomes the first second-half clock circuit 33) is designed using the first clock cell. The circuit block 32 may be, for example, a circuit designed as an IP (Intellectual Property) core for use in another semiconductor integrated circuit.

  Next, for the circuit block 32 designed in step S101, the first clock cell included in the clock circuit is replaced with a second clock cell of the same type (step S102). The clock circuit after the logic cell replacement becomes the first second half clock circuit 33. As a result, the circuit block 32 including the first second half clock circuit 33 is obtained. Next, the semiconductor integrated circuit 30 including the circuit block 32 obtained in step S102 and operating as a whole with the second threshold voltage VT2 is designed (step S103).

  Hereinafter, an effect when the semiconductor integrated circuit 30 is designed using the design method according to the present embodiment will be described. Here, unlike the design method according to the present embodiment, when designing the circuit block 32 that operates at the first threshold voltage VT1, the clock circuit included in the circuit block 32 does not have the above characteristics. Assume that the design is made using logic cells. When the semiconductor integrated circuit 30 including the clock circuit designed in this way as the first second half clock circuit 33 is designed, the designed semiconductor integrated circuit 30 is originally designed to operate at the first threshold voltage VT1. Clock skew due to the difference in threshold voltage is likely to occur between the first flip-flop 34 and the second flip-flop 36 newly designed to operate at the second threshold voltage VT2. . Therefore, in order to suppress this clock skew, the delay time t1 of the first second-half clock circuit 33 is changed when the circuit is changed to make the threshold voltage coincide with the semiconductor integrated circuit 30 after the circuit block 32 is incorporated. Is not changed by changing the threshold voltage (change from the first threshold voltage VT1 to the second threshold voltage VT2), it becomes necessary to adjust the skew of the clock signal again.

  In contrast, in the design method according to the present embodiment, as described above, the first clock cell included in the first second half clock circuit 33 and the second clock included in the second second half clock circuit 35 are used. As long as the types of clock cells are the same, they have the same input capacity, the same cell specific delay, and the same drive capability. For this reason, the delay time t1 of the first second half clock circuit 33 does not change before and after the threshold voltage is changed. Therefore, a clock skew greater than the design value does not occur between the first flip-flop 34 and the second flip-flop 36. Therefore, according to the design method of the semiconductor integrated circuit according to the present embodiment, the threshold voltages of the clock signals can be made to coincide with each other without adjusting the skew of the clock signals again for the semiconductor integrated circuit incorporating the circuit block.

  In the present embodiment, the method of designing a semiconductor integrated circuit that operates at a different threshold voltage using a circuit block that operates at a certain threshold voltage has been described so far. However, the circuit block and the semiconductor integrated circuit including the circuit block are described. A design method similar to the above-described method can be applied even when other operating conditions such as a power supply voltage differ from the circuit. For example, in order to design a semiconductor integrated circuit that operates at the second power supply voltage V2 using a circuit block that operates at the first power supply voltage V1, the first clock for operating at the first power supply voltage V1 is used. For the cell and the second clock cell operating at the second power supply voltage V2, the same procedure as in FIG. 7 may be executed after matching the input capacitance, the cell specific delay, and the driving capability. According to this design method, even when the power supply voltage of the circuit block differs from the power supply voltage of the semiconductor integrated circuit including the circuit block, the clock signal skew adjustment is not performed again for the semiconductor integrated circuit incorporating the circuit block. The power supply voltages of the signals can be matched.

(Third embodiment)
In the third embodiment of the present invention, a method for designing a semiconductor integrated circuit in consideration of a delay time variation of a clock signal accompanying the aging of a transistor will be described. In general, a transistor deteriorates according to the length of a period during which a predetermined signal voltage is applied. For this reason, the delay time of the circuit constituted by the transistors becomes longer as time elapses. In many clock signals, the length of the period when the signal is at the high level is the same as the length of the period when the signal is at the low level. Therefore, if the number of times the clock signal changes to a predetermined value (hereinafter referred to as the number of toggles) is counted, the length of the period during which the clock signal is the predetermined value can be obtained, and this is used to input the clock signal. It is possible to predict in advance how much the deterioration of the transistor included in the logic cell to be progressed.

  FIG. 8 is a flowchart showing a method for designing a semiconductor integrated circuit according to the present embodiment. The procedure shown in FIG. 8 is executed on the semiconductor integrated circuit before the timing adjustment after the logic level design is completed. In the procedure shown in FIG. 8, first, the service life of the semiconductor integrated circuit to be designed is determined (step S201). The service life is determined to a value such as 3 years or 10 years based on the specifications of the semiconductor integrated circuit, operating conditions, or the like.

A semiconductor integrated circuit to be designed includes a plurality of flip-flops. Therefore, next, the number of toggles within the service life determined in step S201 is obtained for the clock signal supplied to each flip-flop (step S202). The toggle count TC of the clock signal supplied to a certain flip-flop FX is calculated by the following equation (3), for example.
TC = TX × FR × α (3)
However, in the above equation (3), TX is the service life determined in step S201, FR is the frequency of the given clock signal CK, α is the clock signal supplied to the flip-flop FX when the clock signal CK changes. It represents the probability of changing (hereinafter referred to as toggle probability). The toggle probability α is calculated or estimated based on the specifications and operating conditions of the semiconductor integrated circuit. The toggle probability α can also be obtained, for example, by logic simulation.

  When obtaining the number of toggles of the clock signal, only a change from a low level to a high level of the signal may be counted as one toggle, or only a change in the reverse direction of the signal may be counted as one toggle. The change in each direction of the signal may be counted as one toggle. Hereinafter, for example, only a change from a low level to a high level of a signal is counted as one toggle.

  Next, for the clock signal supplied to each flip-flop, based on the number of toggles obtained in step S202, the amount of delay variation when the service life has elapsed is obtained (step S203). As for the clock signal, if the length of the period in which the signal is low and the length of the period in which the signal is high are the same, the transistor included in the logic cell to which the clock signal is input From the characteristics, the relationship between the number of toggles of the input signal and the variation rate of the delay time can be obtained (see FIG. 10 described later). Therefore, in step S203, the amount of delay variation when the service life has elapsed can be obtained based on the number of toggles obtained in step S202 and the relationship between the number of toggles in each transistor and the delay variation rate.

  Next, a pair of flip-flops is selected in order from the semiconductor integrated circuit to be designed, and for each pair, the delay variation obtained for the clock signal supplied to one flip-flop and the clock supplied to the other flip-flop The difference from the delay variation obtained for the signal is obtained (step S204). Next, the obtained difference in delay variation is set as a timing constraint between the selected flip-flop pairs as a design margin for absorbing delay time variation due to aging (step S205). Note that in steps S204 and S205, the delay variation difference may be obtained only for the flip-flop pair to which the timing constraint has already been added, and the obtained difference may be set as the timing constraint.

  Next, the timing adjustment is performed for the circuit that supplies the clock signal and the data input signal to the flip-flop according to the timing constraint after setting the design margin as described above (step S206). In step S206, a process for adding or deleting a buffer or the like to the clock circuit, a process for redesigning a circuit for generating a data input signal, or a layout result is corrected so that the clock skew is smaller than a predetermined allowable value. Processing is performed.

  Details of the case where the procedure shown in FIG. 8 is applied to the semiconductor integrated circuit including the clock circuit shown in FIG. 9 will be described. The clock circuit shown in FIG. 9 includes a first clock circuit 41, a first flip-flop 42, a second clock circuit 43, and a second flip-flop 44. Both the first and second flip-flops 42 and 44 operate in synchronization with the applied clock signal CK. More specifically, the first clock circuit 41 includes two buffers, and generates a first clock signal CK1 that changes at the same frequency as the clock signal CK based on the clock signal CK. The first flip-flop 42 operates in synchronization with the first clock signal CK1. The second clock circuit 43 includes an AND gate 45 and a buffer, and generates a second clock signal CK2 that changes less frequently than the clock signal CK based on the clock signal CK. The second flip-flop 44 operates in synchronization with the second clock signal CK2. The AND gate 45 receives the clock signal CK and the clock enable signal CEN. In the following, it is assumed that the frequency of the clock signal CK is 100 MHz, and the clock enable signal CEN is at a high level at a rate of 1 cycle per 10 cycles of the clock signal CK.

The service life of the semiconductor integrated circuit including the clock circuit shown in FIG. 9 is determined to be, for example, 10 years (step S201). Since 10 years corresponds to about 3.15 × 10 ⁸ seconds, the number of times TC1 of the first clock signal CK1 is toggled to 3.15 × 10 ¹⁶ times from the following equation (4). Since the toggle probability α of the second clock signal CK2 is 1/10, the 10-year toggle count TC2 of the second clock signal CK2 is 3.15 × 10 ¹⁵ times from the following equation (5). (Step S202).
TC1 ≒ (3.15 × 10 ⁸ ) × (100 × 10 ⁶ ) × 1 = 3.15 × 10 ¹⁶ (4)
TC2 ≒ (3.15 × 10 ⁸ ) × (100 × 10 ⁶ ) × 1/10 = 3.15 × 10 ¹⁵ (5)

As shown in FIG. 10, the delay time of the transistors constituting the logic cell included in the clock circuit shown in FIG. 9 varies according to the number of toggles of the input signal. The horizontal axis in FIG. 10 represents the number of toggles of the input signal, and the vertical axis represents the variation rate of the delay time. Since the 10-year toggle count TC1 of the first clock signal CK1 is 3.15 × 10 ¹⁶ times, according to FIG. 10, the delay variation after 10 years of the first clock signal CK1 is 5%. . On the other hand, the 10-year toggle count TC2 of the second clock signal CK2 is 3.15 × 10 ¹⁵ times, and therefore, according to FIG. 10, the delay variation after 10 years of the second clock signal CK2 is 2%. It is. In other words, when the service life of 10 years has elapsed, the delay time t1 of the first clock signal CK1 increases by 5% from the beginning, whereas the delay time t2 of the second clock signal CK2 increases by 2% from the beginning. Increase (step S203). Therefore, the difference between the delay variation amount of the first clock signal CK1 and the delay variation amount of the second clock signal CK2 is 3% (step S204).

  Therefore, the obtained delay fluctuation amount of 3% is set as a timing constraint between the first flip-flop 42 and the second flip-flop 44 as a design margin for absorbing the delay time fluctuation accompanying the aging deterioration ( Step S205). Then, according to the timing constraint after setting the design margin of 3%, timing adjustment is performed for the circuit that supplies the clock signal and the data input signal to the first and second flip-flops 42 and 44 (step S206).

  In the following, the effect of designing a semiconductor integrated circuit including the clock circuit shown in FIG. 9 using the design method according to the present embodiment will be described. In the conventional method, when setting the design margin to absorb the delay time variation due to aging deterioration in the timing constraint between the flip-flops, the worst value of the delay variation amount of the clock signal supplied to each flip-flop is set. Is done. For this reason, the timing constraint between the first flip-flop 42 and the second flip-flop 44 includes a variation rate 5% of the delay time t1 of the first clock signal CK1 and a delay of the second clock signal CK2. The worst value of 5% with the fluctuation rate of 2% at time t2 is set as the design margin.

  On the other hand, in the design method according to the present embodiment, when setting a design margin for absorbing delay time variation due to aging deterioration in the timing constraint between flip-flops, the clock signal supplied to each flip-flop The difference in delay variation is set. For this reason, the timing constraint between the first flip-flop 42 and the second flip-flop 44 includes a variation rate 5% of the delay time t1 of the first clock signal CK1 and a delay of the second clock signal CK. A design margin of 3%, which is a difference from the fluctuation rate 2% of the time t2, is set.

  In an actual semiconductor integrated circuit, when the lifetime of 10 years has elapsed and the delay time t1 of the first clock signal CK1 has increased by 5%, the delay time t2 of the second clock signal CK2 has also increased by 2%. It has become. Therefore, the timing constraint between the first flip-flop 42 that operates in synchronization with the first clock signal CK1 and the second flip-flop 44 that operates in synchronization with the second clock signal CK2 includes a delay. It is sufficient to set not the worst value (5%) of the fluctuation amount but the difference (3%) in the delay fluctuation amount as a design margin for absorbing the delay time fluctuation accompanying the aging deterioration. If a semiconductor integrated circuit is designed after setting this difference in delay variation as a design margin for absorbing delay time variation due to deterioration over time, the designed semiconductor integrated circuit will operate correctly within its service life. I can guarantee that.

  Therefore, according to the design method of the semiconductor integrated circuit according to the present embodiment, the design margin can be set more accurately than in the past, so that the variation in the delay time of the clock signal accompanying the aging of the transistor is taken into consideration. Therefore, the circuit scale can be reduced as compared with the prior art.

(Fourth embodiment)
In the fourth embodiment of the present invention, a semiconductor integrated circuit having a function of counting the number of toggles of a clock signal will be described. FIG. 11 is a diagram showing a configuration of the semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit shown in FIG. 11 includes a first half clock circuit 51, first to third second half clock circuits 52a to 52c, first to third circuit blocks 53a to 53c, and first to third toggle counting circuits 54a to 54a. c, a decoder 55, and first to third toggle count storage registers 56a to 56c. Each of the first to third circuit blocks 53a to 53c operates in synchronization with a given clock signal CK. More specifically, the first half clock circuit 51 and the first second half clock circuit 52a generate a first clock signal CK1 based on the clock signal CK, and the first circuit block 53a generates the first clock signal CK1. Operates synchronously. The second and third latter half clock circuits 52b and 52c and the second and third circuit blocks 53b and 53c operate in the same manner.

  The first to third toggle counting circuits 54a to 54c count the number of toggles of the first to third clock signals CK1 to CK3, respectively. Here, the change from the low level to the high level of the signal is counted as one toggle. The decoder 55 decodes the code signal CODE, thereby outputting the enable signals EN1 to EN3 of the first to third toggle count storage registers 56a to 56c. The first to third toggle count storage registers 56a to 56c read the toggle counts TC1 to TC1 from the first to third toggle count circuits 54a to 54c when receiving the enable signals EN1 to EN3, respectively. And the stored number of toggles is output in accordance with the timing specification of the data bus DBUS.

  The number of toggles output to the data bus DBUS is output outside the semiconductor integrated circuit. Therefore, for example, the data bus DBUS is connected to an external input / output terminal (not shown) of the semiconductor integrated circuit in the toggle count output mode. Alternatively, the number of toggles output to the data bus DBUS may be temporarily stored in a register connected to the data bus DBUS and output to the outside of the semiconductor integrated circuit via the register. As described above, the toggle times TC1 to TC1 counted by the first to third toggle counting circuits 54a to 54c by the operations of the decoder 55, the first to third toggle count storage registers 56a to 56c, the data bus DBUS, etc. Is output to the outside of the semiconductor integrated circuit.

  FIG. 12 is a diagram showing another configuration of the semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit shown in FIG. 12 includes a first half clock circuit 51, first to third second half clock circuits 52a to 52c, first to third circuit blocks 53a to 53c, and first to third toggle counting circuits 54a to 54a. c, a decoder 55, a selector 57, and a toggle count storage register 58. Among the constituent elements shown in FIG. 12, the same constituent elements as those in FIG. 11 are denoted by the same reference numerals and description thereof is omitted. Based on the enable signals EN1 to EN3 output from the decoder 55, the selector 57 reads and outputs the number of toggles from any one of the first to third toggle counting circuits 54a to 54c. The toggle count storage register 58 stores therein the toggle count output from the selector 57 and outputs the stored toggle count according to the timing specification of the data bus DBUS.

  The effects of the semiconductor integrated circuit according to this embodiment having the configuration shown in FIG. 11 or FIG. 12 will be described below. The semiconductor integrated circuit according to the present embodiment is mounted on an evaluation board of a certain system, for example. This evaluation board executes actual application software under the actual operating environment of the system. Thereby, the actual operation of the system is reproduced using the evaluation board.

  As described above, the semiconductor integrated circuit according to the present embodiment has a mechanism for counting the number of toggles of the clock signal supplied to each circuit block and outputting the counted number of toggles to the outside of the semiconductor integrated circuit. Therefore, when the system operation is reproduced using the evaluation board, the probability that the clock signal changes in the actual operating environment by obtaining the number of times of toggle of the clock signal supplied to each circuit block (toggle rate α) Can be obtained in a shorter time and with higher accuracy than logic simulation.

  As already described in the third embodiment, if the service life of the semiconductor integrated circuit is determined and the toggle rate α of the clock signal included in the semiconductor integrated circuit is obtained, the delay variation amount of the clock circuit when the service time has elapsed can be obtained. Can be sought. Therefore, when designing a new semiconductor integrated circuit having the same function as the semiconductor integrated circuit according to the present embodiment as an improved version (or as a design target circuit for the evaluation circuit), the obtained delay variation amount is taken into consideration. A clock circuit can be designed. Accordingly, it is possible to design a new semiconductor integrated circuit in which a timing error is unlikely to occur, considering the delay time variation of the clock signal accompanying the aging of the transistor more accurately.

(Fifth embodiment)
In the fifth embodiment of the present invention, a semiconductor integrated circuit having a function of adjusting the number of toggles of a clock signal will be described. FIG. 13 is a diagram showing a configuration of the semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit shown in FIG. 13 includes a first half clock circuit 51, first to third second half clock circuits 52a to 52c, first to third circuit blocks 53a to 53c, and first to third toggle counting circuits 54a to 54a. c, and a toggle adjustment circuit 59. Among the constituent elements shown in FIG. 13, the same constituent elements as those in FIG.

  The toggle adjustment circuit 59 includes first to third clock signals CK1 to CK3 output from the first to third latter half clock circuits 52a to 52c, an adjustment clock signal CK0, a mode selection signal MODE, and first to first clock signals. The toggle times TC1 to TC3 counted by the 3 toggle counters 54a to 54c are input. The toggle adjustment circuit 59 generates clock signals ck1 to ck3 to be supplied to the first to third circuit blocks 53a to 53c based on these input signals.

  FIG. 14 is a diagram showing a detailed configuration of the toggle adjustment circuit 59. The toggle adjustment circuit 59 includes a comparison circuit 61 and first to third selectors 62a to 62c. The comparison circuit 61 obtains select signals S1 to S3 of the first to third selectors 62a to 62c based on the toggle times TC1 to TC3. More specifically, when the maximum value of the number of toggles TC1 to TC1 is M, the comparison circuit 61 sets the first value of the integer i from 1 to 3 when the i-th toggle number TCi is the maximum value M. the selector 62j of i (j = a if i = 1, j = b if i = 2, j = c if i = 3) is set to a high level, otherwise Set the signal to low level.

  As shown in FIG. 15, the first selector 62a outputs one of the first clock signal CK1, the adjustment clock CK0, and the fixed value low level based on the mode selection signal MODE and the selection signal S1. More specifically, the first selector 62a outputs the first clock signal CK1 when the mode selection signal MODE is at the low level (indicating the normal operation mode), and the mode selection signal MODE is at the high level ( When the select signal S1 is at a low level, the adjustment clock CK0 is output, the mode selection signal MODE is at a high level, and the select signal S1 is at a high level. , Output a fixed low level. The second and third selectors 62b and 62c operate in the same manner.

  The toggle adjustment circuit 59 configured in this manner outputs the first to third clock signals CK1 to CK3 to the first to third circuit blocks 53a to 53c in the normal operation mode, respectively. In the adjustment mode, the toggle adjustment circuit 59 selects a circuit block to which a clock signal with a relatively small number of toggles is supplied from the first to third circuit blocks 53a to 53c, and selects the selected circuit block. Output the adjustment clock signal CK0.

  FIG. 16 is a diagram showing a usage pattern of the semiconductor integrated circuit according to the present embodiment. In FIG. 16, the semiconductor integrated circuit 70 is supplied with a clock signal CK generated by a crystal resonator 71 and a clock generation circuit 72. The AND gate 73 receives a clock signal CK and a mode selection signal MODE. The logical product of the clock signal CK and the mode selection signal MODE becomes the adjustment clock signal CK0. The clock generation circuit 72 and the AND gate 73 may be provided inside the semiconductor integrated circuit 70.

  The mode selection signal MODE is set to a low level during normal operation of the system by hardware or software constituting the system, and is set to a high level when the normal operation of the system is not performed, such as during standby or charging of the system. Set to When the mode selection signal MODE is at the low level, the adjustment clock signal CK0 is fixed at the low level, and the first to third selectors 62a to 62c (FIG. 14) included in the toggle adjustment circuit 59 are the first To select and output the third clock signals CK1 to CK3. In this case, the first to third circuit blocks 53a to 53c (FIG. 13) operate in synchronization with the first to third clock signals CK1 to CK3, respectively.

  On the other hand, when the mode selection signal MODE is at the high level, the adjustment clock signal CK0 changes in the same manner as the clock signal CK, and the first to third selectors 62a to 62c are adjusted to the adjustment clock signal CK0 or fixed. Outputs the value (low level). The toggle adjustment circuit 59 is supplied with a clock signal TCi whose toggle count TCi does not match the maximum value M (where j = 1a if i = 1, j = b if i = 2, If i = 3, the adjusted clock signal CK0 is supplied for j = c). Therefore, the number of toggles TC1 to TC1 of the clock signals ck1 to ck3 supplied to the first to third circuit blocks 53a to 53c is brought close to the maximum value M by appropriately setting the mode selection signal MODE to a high level. be able to.

  The transistors constituting the logic cells included in the first to third circuit blocks 53a to 53c are deteriorated according to the number of toggle times TCi of the clock signal supplied to each circuit block. Therefore, if the toggle times TC1 to TC1 of the clock signals ck1 to ck3 supplied to the first to third circuit blocks 53a to c are close to each other, the circuits included in the first to third circuit blocks 53a to 53c. The delay time varies in the same way with time.

  Therefore, by appropriately setting the mode selection signal MODE to the high level, the delay time of the circuits included in the first to third circuit blocks 53a to 53c can be similarly changed over time. Therefore, even after the semiconductor integrated circuit is incorporated into the system, by adjusting the number of toggles of each clock signal, a clock signal that changes at a different frequency is supplied, causing a difference in the degree of aging of the transistor, resulting in a timing error. It can be prevented that the service life of the semiconductor integrated circuit is shortened. This effect is particularly noticeable in a semiconductor integrated circuit having a function of stopping the supply of a clock signal in units of circuit blocks in order to reduce power consumption.

(Sixth embodiment)
In the sixth embodiment of the present invention, a method for verifying or changing a clock circuit included in a semiconductor integrated circuit will be described. FIG. 17 is a flowchart showing a method for designing a semiconductor integrated circuit according to the present embodiment. The procedure shown in FIG. 17 is executed for the semiconductor integrated circuit before the timing adjustment after the logic level design is completed.

  In the procedure shown in FIG. 17, first, among all the types of logic cells that can be used when designing a semiconductor integrated circuit, the types of logic cells that can exist on the clock path are designated (step S301). Hereinafter, the type of logic cell specified in step S301 is referred to as a clock cell, and the other logic cells are referred to as non-clock cells. In step S301, only a logic cell that is resistant to process fluctuation is selectively designated as a clock cell among all the logic cells. Next, a logically equivalent clock cell type is designated corresponding to the non-clock cell type (step S302).

  Next, all clock paths are extracted from the semiconductor integrated circuit to be designed (step S303). Next, with respect to all the logic cells existing on the extracted clock path, it is determined whether the logic cell is a clock cell or a non-clock cell (step S304). Next, various pieces of information related to the logic cell determined as the non-clock cell in step S304 are obtained (step S305). The information obtained in step S305 is referred to in the subsequent design. Next, the logic cell determined as the non-clock cell in step S304 is replaced with the clock cell designated in accordance with the type of the logic cell in step S302 (step S306).

  Therefore, according to the semiconductor integrated circuit design method according to the present embodiment, the semiconductor integrated circuit includes only logic cells having certain characteristics (for example, logic cells that are resistant to process fluctuations) on the clock path. The clock circuit to be changed can be changed.

  Note that if steps S302 and S306 are deleted from the flowchart shown in FIG. 17, the flowchart shown in FIG. 18 is obtained. According to the procedure shown in FIG. 18, it is possible to easily verify that the logic cell existing on the clock path is a logic cell having a certain characteristic (for example, a logic cell that is resistant to process fluctuation).

(Seventh embodiment)
In the seventh embodiment of the present invention, a method for designing a clock circuit in consideration of the characteristics of the clock path will be described. First, a method for designing a clock circuit in consideration of a difference in the number of stages of logic cells existing on the clock path will be described. FIG. 19 is a flowchart showing a method for designing a semiconductor integrated circuit according to this embodiment. The procedure shown in FIG. 19 is executed for the semiconductor integrated circuit before the timing adjustment after the logic level design is completed.

  In the procedure shown in FIG. 19, first, a clock path reaching each flip-flop is extracted from a semiconductor integrated circuit to be designed (step S401). Next, as the characteristics of each extracted clock path, the number of stages of logic cells existing on each clock path is obtained (step S402). Next, a pair of flip-flops is selected in order from the semiconductor integrated circuit to be designed, and for each pair, the number of logic cell stages present on the clock path leading to one flip-flop and the clock path leading to the other flip-flop The difference from the number of logic cell stages existing in is obtained (step S403).

  Next, the time corresponding to the obtained difference is set as a timing constraint between the selected flip-flop pair as a design margin for absorbing the clock path difference (step S404). In step S404, as the design margin, for example, a time proportional to the difference obtained in step S403 may be set, or a time obtained by applying a predetermined function to the obtained difference may be set. In steps S403 and S404, only for flip-flop pairs to which timing constraints have already been added, the difference in the number of stages of logic cells existing on the clock path is obtained, and the time corresponding to the obtained difference is used as the timing constraint. It may be set.

  Next, timing adjustment is performed for the circuit that supplies the clock signal and the data input signal to the flip-flop according to the timing constraint after setting the design margin as described above (step S405). In step S405, a process of adding or deleting a buffer or the like to the clock circuit, a process of redesigning a circuit that generates a data input signal, or a layout result is corrected so that the clock skew is smaller than a predetermined allowable value. Processing is performed.

  The details when the procedure shown in FIG. 19 is applied to the semiconductor integrated circuit including the clock circuit shown in FIG. 20 will be described. The clock circuit shown in FIG. 20 includes a first clock circuit 81, a first flip-flop 82, a second clock circuit 83, and a second flip-flop 84. The first and second flip-flops 82 and 84 operate in synchronization with the applied clock signal CK. More specifically, the first clock circuit 81 generates the first clock signal CK1 based on the clock signal CK, and the first flip-flop 82 operates in synchronization with the first clock signal CK1. The second clock circuit 83 and the second flip-flop 84 operate in the same manner.

  Hereinafter, a path from the supply point of the clock signal CK to the first flip-flop 82 via the first clock circuit 81 is referred to as a first clock path, and the second clock circuit from the supply point of the clock signal CK. A path that reaches the second flip-flop 84 via 83 is referred to as a second clock path. As shown in FIG. 20, there are four logic cells on the first clock path and five logic cells on the second clock path. In FIG. 20, characters such as A, B, and C attached to the logic cell indicate the type of the logic cell.

  Since the number of logic cells existing on the first clock path is 4 and the number of logic cells existing on the second clock path is 5 (step S402), the difference between the two is 1 ( Step S403). Here, if a design margin of 50 picoseconds per stage difference is set, the design margin in this case is 50 picoseconds. Therefore, the obtained value of 50 picoseconds is set as a timing constraint between the first flip-flop 82 and the second flip-flop 84 as a design margin for absorbing the clock path difference (step S404). Next, timing adjustment is performed for the clock circuit that supplies the clock signal and the data input signal to the first and second flip-flops 82 and 84 in accordance with the timing constraint after setting the design margin of 50 picoseconds (step S405). ).

  Hereinafter, an effect of designing a semiconductor integrated circuit including the clock circuit shown in FIG. 20 using the design method according to the present embodiment will be described. Conventionally, it has not been known to set a design margin for absorbing the number of stages of logic cells existing on a clock path as a timing constraint between flip-flops. In general, if there is a difference in the number of stages of logic cells between clock paths, there is a difference in the constituent factors of the delay time between the clock paths, and in the manufactured semiconductor integrated circuit, the delay time varies between the clock paths. It becomes easy. For this reason, in a semiconductor integrated circuit according to a conventional method, a timing error is likely to occur due to manufacturing variations.

  In contrast, in the design method according to the present embodiment, a design margin for absorbing the number of stages of logic cells existing on the clock path is set in the timing constraint between the flip-flops. For this reason, there is a difference in the number of logic cells between the clock paths, and even if there are differences in the constituent factors of the delay time between the clock paths, the differences are absorbed by the set design margin. Therefore, in the manufactured semiconductor integrated circuit, the delay time hardly varies between clock paths. Therefore, according to the method for designing a semiconductor integrated circuit according to the present embodiment, a semiconductor integrated circuit in which a timing error is unlikely to occur can be obtained.

  About the design method of the semiconductor integrated circuit which concerns on this embodiment, the modification shown below can be comprised. As a first modification, the number of logic cells existing on the clock path can be used as the characteristic of the clock path. In order to execute the design method according to the first modification, in step S402 shown in FIG. 19, the characteristics of each clock path exist on the clock path instead of the number of logic elements existing on the clock path. In step S403, the difference in the number of logic cells is obtained, and in step S404, the time corresponding to the obtained difference is set as a design margin.

Details of the case where the method according to the first modification is applied to a semiconductor integrated circuit including the clock circuit shown in FIG. 20 will be described. One type A, B, C, and D logic cells each exist on the first clock path, and three types A, B, and D logic cells each exist on the second clock path. Since there are one and one, the difference in the number of each logic cell type is two for type A and one for type C. Here, assuming that design margins of 1.0%, 1.1%, 1.2%, and 1.3% are set for each logic cell of types A, B, C, and D, respectively, The design margin MG is 3.2% from the following equation (6).
MG = 1.0 × 2 + 1.2 × 1 = 3.2 (6)
Therefore, the timing adjustment of the circuits that supply signals to the first and second flip-flops 82 and 84 is performed in accordance with the timing constraint in which the obtained value of 3.2% is set as the design margin for absorbing the clock path difference. Is called.

  As a second modification, the type of wiring and delay time existing on the clock path can be used as the characteristics of the clock path. FIG. 21 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second modification of the present embodiment. In the flowchart shown in FIG. 21, steps S401 and S405 are the same as those shown in the flowchart shown in FIG.

According to the procedure shown in FIG. 21, after extracting clock paths (step S401), the type of wiring of each clock path is obtained as the characteristics of each extracted clock path (step S412). Next, a pair of flip-flops is selected in order from the semiconductor integrated circuit to be designed, and for each pair, a set of wirings existing on the clock path leading to one flip-flop and a clock path leading to the other flip-flop For a set of existing wirings, a partial margin mg defined by the following equation (7) is obtained, and a sum MGS of two partial margins is obtained (step S413).
mg = Σ (di × mi) (7)
In the above equation (7), di and mi are the delay time and the wiring margin of the i-th wiring existing on the clock path, respectively, and the symbol Σ represents that the sum is obtained for one clock path. The wiring margin mi is determined according to the type of wiring, for example, 0.8 for a double-width wiring, 0.4 for a double-width wiring, 0.1 for a triple-width wiring, and the like.

  Next, the sum MGS of the obtained partial margins is set as a timing margin between the pair of flip-flops selected in step S413 as a design margin for absorbing the clock path difference (step S414), and the circuit timing is set. Adjustment is performed (step S405).

  Details of a case where the method according to the second modification is applied to a semiconductor integrated circuit including the clock circuit shown in FIG. 22 will be described. FIG. 22 is a diagram showing the clock circuit shown in FIG. 20 together with the delay time and the width of the wiring existing on each clock path. In FIG. 22, the symbol d ** (* is a single character number) attached to the wiring represents the delay time of each wiring, and the symbols W1 to W3 represent the wiring having a width of 1 to 3 times (step S412).

Here, when the wiring margin mi is determined to be 0.8 for the single-width wiring, 0.4 for the double-width wiring, and 0.1 for the triple-width wiring, as illustrated, the first and second clocks The partial margins mg1 and mg2 of the path are as shown in the following expressions (8) and (9), respectively, and the sum MGS is as shown in the following expression (10) (step S413).
mg1 = (d11 + d12) × 0.1 + d13 × 0.4 + (d14 + d15) × 0.8 (8)
mg2 = (d21 + d22) × 0.1 + (d23 + d24) × 0.4 + (d25 + d26) × 0.8 (9)
MGS = (d11 + d12 + d21 + d22) × 0.1 + (d13 + d23 + d24) × 0.4
+ (D14 + d15 + d25 + d26) × 0.8 (10)
Therefore, the timing adjustment of the circuit that supplies the clock signal and the data input signal to the first and second flip-flops 82 and 84 is designed to absorb the difference between the clock paths using the value calculated by the above equation (10). This is performed according to the timing constraint set as the margin.

  In addition to the above, as the characteristics of the clock path, the pitch of the wiring existing on the clock path, the presence or absence of a shield, and the like may be considered. Further, it is arbitrary how to obtain the design margin based on the obtained characteristics of the clock path. Each of the semiconductor integrated circuit design methods according to these modifications has the same effects as the design method shown in FIG.

  Since the semiconductor integrated circuit and the design method thereof according to the present invention have characteristics superior to those of the prior art with respect to the supply of the clock signal, the semiconductor integrated circuit mainly constituted by the logic circuit, the semiconductor including both the logic circuit and the memory circuit The present invention can be used for various semiconductor integrated circuits such as integrated circuits and design methods thereof.

The figure which shows the structure of the semiconductor integrated circuit which concerns on the 1st Embodiment of this invention. Transistor layout diagram Diagram showing flip-flop setup and hold margins The figure for demonstrating the effect of the semiconductor integrated circuit which concerns on the 1st Embodiment of this invention The figure for demonstrating the effect of the semiconductor integrated circuit which concerns on the modification of the 1st Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit designed by the design method of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. 7 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention. 7 is a flowchart showing a method for designing a semiconductor integrated circuit according to the third embodiment of the present invention. The figure which shows the clock circuit designed by the design method of the semiconductor integrated circuit concerning the 3rd Embodiment of this invention The figure which shows the relationship between the frequency | count of toggle in a transistor, and the variation rate of delay time The figure which shows the structure of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. The figure which shows the other structure of the semiconductor integrated circuit based on the 4th Embodiment of this invention. The figure which shows the structure of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. The figure which shows the detailed structure of the toggle adjustment circuit of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. Table showing the input / output relationship of the selectors included in the toggle adjustment circuit of the semiconductor integrated circuit according to the fifth embodiment of the present invention The figure which shows the usage type of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention Flowchart showing a method for designing a semiconductor integrated circuit according to the sixth embodiment of the present invention. 10 is a flowchart showing a method for designing a semiconductor integrated circuit according to a modification of the sixth embodiment of the present invention. Flowchart showing a method for designing a semiconductor integrated circuit according to the seventh embodiment of the present invention. The figure which shows the clock circuit designed by the design method of the semiconductor integrated circuit concerning the 7th Embodiment of this invention Flowchart showing a method for designing a semiconductor integrated circuit according to a second modification of the seventh embodiment of the present invention. The figure which shows the clock circuit designed by the design method of the semiconductor integrated circuit which concerns on the 2nd modification of the 7th Embodiment of this invention

Explanation of symbols

11, 12, 31, 33, 35, 41, 43, 51, 52, 81, 83 ... Clock circuits 13, 15, 34, 36, 42, 44, 82, 84 ... Flip-flops 14 ... Combination circuits 16, 17 ... Logic cells 21, 23, 24 ... Diffusion region 22 ... Polysilicon region 25 ... Unnecessary diffusion region 30, 70 ... Semiconductor integrated circuit 32, 53 ... Circuit block 45, 73 ... AND gate 54 ... Toggle counting circuit 55 ... Decoder 56, 58 ... Toggle count storage registers 57 and 62 ... Selector 59 ... Toggle adjustment circuit 61 ... Comparison circuit 71 ... Crystal oscillator 72 ... Clock generation circuit CK, CK1 to CK3, ck1 to ck3 ... Clock signals CEN, CEN2, CEN3 ... Clock enable Signals TC1 to TC3 ... Toggle count DBUS ... Data buses EN1 to EN3 ... Enable signal CK0 ... Control Clock signal MODE ... mode selection signal S1~S3 ... selection control signal

Claims (2)

A method of designing a semiconductor integrated circuit that operates in synchronization with a clock signal,
Specifying the types of logic cells that can exist on the clock path;
A method for designing a semiconductor integrated circuit, comprising: for each clock path included in the semiconductor integrated circuit, determining whether or not a logic cell existing on the clock path is a specified type of logic cell. Designating a type of logic cell that is logically equivalent to the logic cell and can exist on the clock path, corresponding to the type of logic cell that cannot exist on the clock path;
Based on the determination result, for each clock path included in the semiconductor integrated circuit, a type of logic cell that exists on the clock path and cannot exist on the clock path is placed on the clock path corresponding to the type of the logic cell. The method for designing a semiconductor integrated circuit according to claim 1, further comprising a step of replacing with a logic cell of a kind that can exist.

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