JP2006269724A - Ceramic device - Google Patents

Ceramic device Download PDF

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Publication number
JP2006269724A
JP2006269724A JP2005085475A JP2005085475A JP2006269724A JP 2006269724 A JP2006269724 A JP 2006269724A JP 2005085475 A JP2005085475 A JP 2005085475A JP 2005085475 A JP2005085475 A JP 2005085475A JP 2006269724 A JP2006269724 A JP 2006269724A
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Japan
Prior art keywords
ceramic
ceramic substrate
ceramic device
terminal electrodes
insulating particles
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JP2005085475A
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Japanese (ja)
Inventor
Hiroshi Kagata
博司 加賀田
Ichiro Kameyama
一郎 亀山
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005085475A priority Critical patent/JP2006269724A/en
Publication of JP2006269724A publication Critical patent/JP2006269724A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To improve an isolation characteristic in a ceramic device which is mainly used for high frequency use. <P>SOLUTION: The device is provided with a ceramic substrate 1, inner electrodes 2 which are disposed in the ceramic substrate 1 and form a prescribed circuit, and terminal electrodes 3 which are electrically connected to the inner electrodes 2 on the outer surface of the ceramic substrate 1. The surface of the ceramic substrate 1 positioned between the terminal electrodes 3 is made rough. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、主に高周波用途で使用されるセラミックデバイスに関するものである。   The present invention relates to a ceramic device mainly used for high frequency applications.

セラミックデバイスは、通常、多数個取り用のセラミックグリーンシートに所定の内部電極を形成したものを準備し、このセラミックグリーンシートを適宜積層し、この積層体を焼成した後に小片化するものである。   In general, a ceramic device is prepared by preparing a plurality of ceramic green sheets for which a predetermined number of internal electrodes are formed, laminating the ceramic green sheets as appropriate, and firing the laminated body.

そして、この焼結体の小片化にあたっては、通常、焼結体をダイシングなどの切断手法により分割する方法や、焼結体に予め溝を形成しておきこの溝を用いて分割する方法が用いられている。   In order to reduce the size of the sintered body, generally, a method of dividing the sintered body by a cutting method such as dicing, or a method of forming a groove in the sintered body in advance and dividing the sintered body using the groove is used. It has been.

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献１が知られている。
特開平７−９９２６３号公報 As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP-A-7-99263

しかしながら、これらの方法では分割後に得られたセラミックデバイスの分割面、つまり、セラミックデバイスの側面においてはセラミック基体が露出した平坦面となり、このセラミック基体が露出した部分に内部電極と電気的に接続された外部接続用の端子電極を設けた場合、セラミック基体の表面が平坦面であることから、隣接する端子電極間に微少電流が流れやすくなってしまい、セラミックデバイスのアイソレーション特性が劣化してしまうという問題が生じていた。   However, in these methods, the divided surface of the ceramic device obtained after the division, that is, the flat surface on which the ceramic substrate is exposed on the side surface of the ceramic device is electrically connected to the internal electrode at the exposed portion of the ceramic substrate. When the terminal electrode for external connection is provided, since the surface of the ceramic substrate is flat, a minute current easily flows between the adjacent terminal electrodes, and the isolation characteristics of the ceramic device deteriorate. There was a problem.

そこで、本発明はこのような問題を解決し、セラミックデバイスのアイソレーション特性を向上させることを目的とする。   Therefore, the present invention aims to solve such problems and improve the isolation characteristics of the ceramic device.

この目的を達成するために本発明は、セラミックデバイスを形成するセラミック基体における端子電極間に位置する領域を粗面化した構成としたのである。   In order to achieve this object, the present invention has a structure in which the region located between the terminal electrodes in the ceramic substrate forming the ceramic device is roughened.

この構成により、セラミックデバイスを回路基板に実装した際のアイソレーション特性を向上させることが出来るのである。   With this configuration, the isolation characteristics when the ceramic device is mounted on the circuit board can be improved.

以下、本発明における一実施形態について図面を用いて説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図１は、本発明のセラミックデバイスにおける断面を示した模式図であり、ブロック状のセラミック基体１の内部において、回路形成に必要となるインダクタやコンデンサやストリップラインなどの回路素子を適宜形成する内部電極２が三次元的に形成され高周波フィルタや高周波スイッチなどの高周波回路が形成され、セラミックデバイスの実装面となる下面には内部電極２と電気的に接続された端子電極３が適宜設けられている。   FIG. 1 is a schematic view showing a cross section of a ceramic device according to the present invention. Inside a block-like ceramic substrate 1, an inside for appropriately forming circuit elements such as inductors, capacitors and strip lines necessary for circuit formation is shown. The electrode 2 is formed three-dimensionally to form a high-frequency circuit such as a high-frequency filter or a high-frequency switch, and a terminal electrode 3 electrically connected to the internal electrode 2 is appropriately provided on the lower surface serving as a ceramic device mounting surface. Yes.

セラミック基体１を形成する材料としては、誘電体、磁性体、或いはそれらの複合体や、種々の誘電率を持つ誘電体を複合させる場合などが挙げられるが、特に限定されるものではない。   Examples of the material for forming the ceramic substrate 1 include, but are not limited to, dielectrics, magnetic bodies, composites thereof, and composites having various dielectric constants.

内部電極２や端子電極３を形成する材料としては、Ａｇ、Ｃｕ、Ｐｔ、Ａｕ、Ｐｄ、Ｎｉ、Ｗ、Ｍｏあるいはそれらの合金などが挙げられるが、特に限定されるものではない。   Examples of the material for forming the internal electrode 2 and the terminal electrode 3 include, but are not limited to, Ag, Cu, Pt, Au, Pd, Ni, W, Mo, or alloys thereof.

また、セラミック基体１の内部において高周波回路を形成する上で内部電極２として形成しにくい回路素子については、必要に応じてセラミック基体１の上面にチップ部品４として実装される。なお、実装されるチップ部品４としては、半導体、ＳＡＷデバイス、コンデンサ、インダクタ、抵抗などが挙げられ、特に図示はしていないがチップ部品４は必要に応じて樹脂あるいはキャップにより覆うものである。   Further, a circuit element that is difficult to form as the internal electrode 2 when forming a high-frequency circuit inside the ceramic substrate 1 is mounted on the upper surface of the ceramic substrate 1 as a chip component 4 as necessary. The chip component 4 to be mounted includes a semiconductor, a SAW device, a capacitor, an inductor, a resistor, and the like. Although not particularly illustrated, the chip component 4 is covered with a resin or a cap as necessary.

そして、このセラミックデバイスにおいては隣接する端子電極３間に位置するセラミック基体１の表面領域を粗面化した構成とし、セラミックデバイスのアイソレーション特性を向上させている。   In this ceramic device, the surface region of the ceramic substrate 1 located between the adjacent terminal electrodes 3 is roughened to improve the isolation characteristics of the ceramic device.

すなわち、セラミックデバイスにおけるアイソレーション特性の劣化は先にも述べたように、端子電極３間においてセラミック基体１の表面を介して流れる微少電流により影響を受けるもので、この端子電極３間に位置するセラミック基体１の領域を粗面化することにより、図２に示されるように電流経路５の直線性が損なわれ抵抗成分が高くなりその分抵抗成分が高まることになり、結果としてセラミックデバイスのアイソレーション特性を向上させることが出来るのである。   That is, the deterioration of the isolation characteristic in the ceramic device is affected by a minute current flowing between the terminal electrodes 3 through the surface of the ceramic substrate 1 as described above, and is located between the terminal electrodes 3. By roughening the region of the ceramic substrate 1, as shown in FIG. 2, the linearity of the current path 5 is impaired, the resistance component is increased, and the resistance component is increased accordingly. As a result, the isolation of the ceramic device is increased. Can improve the vibration characteristics.

また、このようにセラミック基体１の表面を粗面化するにあたっては、端子電極３間に位置するセラミック基体１の表面に絶縁性粒子６を付着させることにより容易に粗面化することができ、この絶縁性粒子６としては、アルミナ、ジルコニア、マグネシアなどが挙げられるが、特にセラミック基体１に含まれる成分で構成すれば、セラミック基体１との密着強度が強くなり絶縁性粒子６の脱落を防止できるのである。   Further, in roughening the surface of the ceramic substrate 1 in this way, it can be easily roughened by attaching insulating particles 6 to the surface of the ceramic substrate 1 located between the terminal electrodes 3. Examples of the insulating particles 6 include alumina, zirconia, and magnesia. Particularly, when the insulating particles 6 are composed of components included in the ceramic substrate 1, the adhesion strength with the ceramic substrate 1 is increased and the insulating particles 6 are prevented from falling off. It can be done.

なお、上述した一実施形態においては端子電極３がセラミックデバイスの実装面に設けられたランドグリッドアレイの構造を挙げて説明したが、端子電極３がセラミックデバイスの側面に設けられた構造であったとしても、その端子電極３間に位置するセラミックデバイスの側面領域を絶縁性粒子６などで粗面化することで同様の効果を奏することが出来るのである。   In the embodiment described above, the structure of the land grid array in which the terminal electrode 3 is provided on the mounting surface of the ceramic device has been described. However, the terminal electrode 3 is provided on the side surface of the ceramic device. However, the same effect can be obtained by roughening the side surface region of the ceramic device located between the terminal electrodes 3 with the insulating particles 6 or the like.

本発明は、主に高周波用途で使用されるセラミックデバイスに関するものであり、セラミックデバイスにおけるアイソレーション特性を向上させることができるという効果を有し、特に携帯電話などの移動体通信用のモジュールとして有効である。   The present invention relates to a ceramic device mainly used for high-frequency applications, and has an effect of improving the isolation characteristics in the ceramic device, and is particularly effective as a module for mobile communication such as a mobile phone. It is.

本発明の一実施形態におけるセラミックデバイスの模式図The schematic diagram of the ceramic device in one Embodiment of this invention 同セラミックデバイスの端子電極３間における電流経路を示す模式図Schematic diagram showing the current path between the terminal electrodes 3 of the ceramic device

符号の説明Explanation of symbols

１ セラミック基体
２ 内部電極
３ 端子電極
６ 絶縁性粒子 DESCRIPTION OF SYMBOLS 1 Ceramic base body 2 Internal electrode 3 Terminal electrode 6 Insulating particle

Claims (3)

セラミック基体と、このセラミック基体の内部に設けられ所定の回路を形成する内部電極と、前記セラミック基体の外表面において前記内部電極と電気的に接続された端子電極とを有し、前記端子電極間に位置する前記セラミック基体の表面を粗面化したことを特徴とするセラミックデバイス。 A ceramic base; an internal electrode provided inside the ceramic base to form a predetermined circuit; and a terminal electrode electrically connected to the internal electrode on an outer surface of the ceramic base; A ceramic device characterized by roughening the surface of the ceramic substrate located on the surface. 端子電極間に位置するセラミック基体の表面に絶縁性粒子を付着させたことを特徴とする請求項１に記載のセラミックデバイス。 2. The ceramic device according to claim 1, wherein insulating particles are attached to the surface of the ceramic substrate located between the terminal electrodes. 絶縁性粒子をセラミック基体を形成する材料を主原料として形成したことを特徴とする請求項２に記載のセラミックデバイス。 The ceramic device according to claim 2, wherein the insulating particles are formed using a material for forming the ceramic substrate as a main raw material.
JP2005085475A 2005-03-24 2005-03-24 Ceramic device Pending JP2006269724A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917693A (en) * 1995-06-30 1997-01-17 Murata Mfg Co Ltd Electronic parts
JP2001195965A (en) * 2000-01-07 2001-07-19 Mitsubishi Electric Corp Circuit breaker

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917693A (en) * 1995-06-30 1997-01-17 Murata Mfg Co Ltd Electronic parts
JP2001195965A (en) * 2000-01-07 2001-07-19 Mitsubishi Electric Corp Circuit breaker

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