JP2006269519A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a stable seal ring structure by preventing occurrence of particles due to an etching residue in a semiconductor device, and also to provide its manufacturing method. <P>SOLUTION: The semiconductor device consists of an interior element region of chip where elements are arranged on a semiconductor substrate; and a peripheral region of chip which consists of an annular seal ring 2 formed on the semiconductor substrate so as to surround the interior element region of chip. The seal ring 2 consists of an annular metal wall 14(b) formed by embedding an annular groove with metal; an annular silicon nitride film 15(b) which, is wider than the metal wall 14(b), and covers the top face of the metal wall; and an annular metal pad layer 16(b) which covers the top face of the silicon nitride film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a seal ring provided around a chip in order to prevent moisture and moisture from penetrating into a chip internal element region.

  Conventionally, when a wafer is diced in a semiconductor device manufacturing process, there is a problem that moisture in the air or dicing permeates from the diced cross section of the chip, and the performance of the internal elements deteriorates. Therefore, in order to prevent moisture and moisture from penetrating into the chip internal element region, there is a technique that surrounds the chip internal element region by arranging a film structure, which is normally called a seal ring, that does not penetrate moisture in an annular shape around the chip peripheral region. (For example, refer to Patent Document 1).

  By the way, development of an integrated circuit using an MIM capacitor is progressing with the recent enhancement of functions and speed of semiconductor integrated circuit devices. A conventional semiconductor device equipped with this MIM capacitor, including a seal ring, is shown in FIGS.

  32 is a plan view including a seal ring in the peripheral region of the chip in the conventional semiconductor device, FIG. 33 is an enlarged view of a portion XXXIII in FIG. 32, and FIG. 34 is a sectional view taken along XXXIV-XXXIV in FIG.

32 to 34, 101 is a scribe line, 102 is a seal ring, 103 is an MIM capacitor, 104 is a silicon substrate, 105 is a P ⁺ diffusion layer, 106 is a field oxide film, 107 is an interlayer insulating film, and 108 is a first insulating film. An annular wall, 109 (a) is a first layer wiring, 109 (b) is a first annular pad, 110 is an interlayer insulating film, 111 is a second annular wall, 112 (a) is a second layer wiring, 112 ( b) is a second annular pad; 113 is an interlayer insulating film; 114 (a) is a via hole; 114 (b) is a third annular wall; 115 is a silicon nitride film; 116 (a) is a third layer wiring; (B) is a third annular pad, and 117 is a silicon nitride protective film.

  35 is a plan view including a seal ring in the peripheral region of a chip in another conventional semiconductor device, FIG. 36 is an enlarged view of a portion XXXVI in FIG. 35, and FIG. 37 is a sectional view along XXXVII-XXXVII in FIG.

  35 to 37, reference numeral 118 denotes a metal for the MIM upper electrode, and other parts that are the same as those in FIGS. 32 to 34 are given the same reference numerals.

32 to 37, the MIM capacitor 103 is formed in the chip internal element region, and the annular walls 108, 111, 114 (b) and the annular pad 109 (b) are formed in the peripheral region of the chip. 112 (b) and 116 (b) are formed repeatedly and surround the chip internal element region. The laminated structure of the annular walls 108, 111, 114 (b) and the annular pads 109 (b), 112 (b), 116 (b) is a seal for preventing the penetration of moisture and moisture into the chip internal element region. Make up the ring.
JP-A-8-37289

  However, in the semiconductor device shown in FIGS. 32 to 37, since the plug of the seal ring 102 is formed in a groove shape so as to surround the chip internal element region, the volume of the plug is larger than that of the cylindrical via hole portion. Large, the amount of embedded conductive film such as tungsten is insufficient, and depressions are likely to occur.

  Therefore, when forming the MIM capacitor, the capacitor dielectric film 115 such as a silicon nitride film deposited on the recesses of the second annular pad 112 (b) and the third annular wall 114 (b) of the seal ring 102 and the electrode In the etching process for removing the metal film 118, a silicon nitride film residue 115 ′ and a metal residue 118 ′ for the MIM upper electrode are generated in the recessed portion, which becomes a particle source.

  Therefore, an object of the present invention is to provide a stable seal ring structure by preventing generation of particles due to etching residues.

  A first semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A semiconductor device comprising a chip peripheral region, wherein the seal ring covers an annular metal wall formed by embedding metal in an annular groove and a top surface of the metal wall wider than the width of the metal wall. An annular silicon nitride film and an annular metal pad layer covering the upper surface of the silicon nitride film are provided.

  A second semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A semiconductor device including a chip peripheral region, wherein the seal ring is formed to be electrically connected to an annular first metal wall formed by embedding a metal in an annular groove and the first metal wall. A ring-shaped first metal pad layer, a ring-shaped silicon nitride film formed on and in contact with the first metal pad layer and having a width wider than the width of the first metal wall, and on the silicon nitride film An annular second metal pad layer formed in contact with and wider than the width of the first metal wall, and the second metal pad layer is interposed between the first metal wall and the second metal pad layer via the annular second metal wall. Formed higher than 2 metal pad layers It is electrically connected to the annular third metal pad layer.

  A third semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring formed on the semiconductor substrate so as to surround the chip internal element region. A semiconductor device including a chip peripheral region, wherein the seal ring is formed to be electrically connected to an annular first metal wall formed by embedding a metal in an annular groove and the first metal wall. A ring-shaped first metal pad layer, a ring-shaped high-dielectric film formed on the first metal pad layer and having a width wider than the width of the first metal wall, and the high-dielectric film An annular second metal pad layer that is in contact with and formed wider than the first metal wall, and the width of the first metal pad layer is equal to the width of the second metal pad layer. More widely formed, the first metal pad layer is a ring. It is electrically connected to the annular third metal pad layer formed at a position higher than the second metal pad layer through the second metal wall.

  A fourth semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A semiconductor device including a chip peripheral region, wherein the seal ring is formed between an annular metal wall formed by embedding a metal in an annular groove provided in an insulating film, and the groove and the metal wall. An annular metal layer formed so as to extend on the insulating film at the upper end of the groove, and formed on the metal layer so as to cover the upper surface of the metal wall with a width narrower than the metal layer and wider than the metal wall. An annular high dielectric film and an annular metal pad layer covering the high dielectric film, wherein the metal wall is electrically connected to the metal pad layer through the metal layer. To do.

  A fifth semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A semiconductor device comprising a chip peripheral region, wherein the seal ring is formed to be electrically connected to an annular first metal wall formed by embedding a metal in an annular groove. A ring-shaped first metal pad layer, and an upper surface of the first metal pad layer in contact with the first metal pad layer and narrower than the first metal pad layer and wider than the first metal wall. An annular high-dielectric film formed so as to cover; and an annular second metal pad layer covering the high-dielectric film, wherein the first metal pad layer and the second metal pad layer are in contact with each other. The second metal pad. The conductive layer is electrically connected to the annular third metal pad layer formed at a position higher than the second metal pad layer via the annular second metal wall.

  According to the semiconductor device of the present invention, the upper surface of the annular metal wall or metal pad layer in which the depression is generated is covered with the silicon nitride film, the high dielectric film, or the metal pad layer, so that the annular metal wall or metal pad layer is covered. It is possible to prevent the generation of etching residue in the dents and realize a stable seal ring structure.

  A first method of manufacturing a semiconductor device according to the present invention includes a chip internal element region in which elements are arranged on a semiconductor substrate, and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A method of manufacturing a semiconductor device comprising a chip peripheral region, comprising: forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the chip peripheral region; and A step of forming an annular metal wall by embedding metal in the groove; a step of depositing a silicon nitride film on the entire surface of the semiconductor substrate; and etching the silicon nitride film to extend the chip peripheral region beyond the width of the metal wall Forming a ring-shaped silicon nitride film with a predetermined width; depositing a wiring film on the entire surface of the semiconductor substrate; and etching the wiring film to form the silicon nitride in the chip peripheral region. Characterized in that it comprises a step of forming an annular metal pad layer on the membrane.

  According to a second method of manufacturing a semiconductor device of the present invention, a chip internal element region formed by disposing elements on a semiconductor substrate and an annular seal ring surrounding the chip internal element region are formed on the semiconductor substrate. A method of manufacturing a semiconductor device comprising a chip peripheral region, comprising: forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the chip peripheral region; and A step of embedding a metal in the groove to form an annular metal wall, a step of depositing a first wiring film on the entire surface of the semiconductor substrate, a silicon nitride film, and then a second wiring film; Etching the second wiring film to form an annular second metal pad layer having a width expanded from the width of the metal wall in the peripheral area of the chip; and etching the silicon nitride film to form the chip Zhou Forming a ring-shaped silicon nitride film in a region with a width expanded from the width of the metal wall; and etching the first wiring film to form a ring-shaped ring with a width expanded from the width of the metal wall in the chip peripheral region. Forming a first metal pad layer.

  The etching of the silicon nitride film and the etching of the first wiring film may be performed simultaneously.

  According to a third method of manufacturing a semiconductor device of the present invention, a chip internal element region formed by disposing elements on a semiconductor substrate and an annular seal ring surrounding the chip internal element region are formed on the semiconductor substrate. A method of manufacturing a semiconductor device comprising a chip peripheral region, comprising: a step of forming a first insulating film on the semiconductor substrate; and a first annular film on the first insulating film in the chip peripheral region. A step of forming a groove; a step of embedding a metal in the first annular groove to form an annular first metal wall; and depositing a first wiring film on the entire surface of the semiconductor substrate; And then depositing a second wiring film, and etching the second wiring film to form a second annular ring having a width expanded from the width of the first metal wall in the chip peripheral region. Forming a metal pad layer and the high dielectric film; Etching to form an annular high dielectric film in the chip peripheral region with a width expanded from the width of the first metal wall; and etching the first wiring film to form the first peripheral region in the chip peripheral region. Forming an annular first metal pad layer that is wider than the width of one metal wall and wider than the width of the second metal pad layer; and a second insulating film on the semiconductor substrate Forming a second annular groove in the second insulating film on the first metal pad layer away from the second metal pad layer in the peripheral area of the chip, and A step of embedding a metal in the second annular groove to form an annular second metal wall; a step of depositing a third wiring film on the entire surface of the semiconductor substrate; and etching the third wiring film to A third metal wall on the second metal wall in the peripheral area of the chip; Characterized in that it comprises a step of forming a Tarupaddo layer.

  The etching of the high dielectric film and the etching of the first wiring film may be performed simultaneously.

  According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and an annular seal ring surrounding the chip internal element region and formed on the semiconductor substrate. A method of manufacturing a semiconductor device comprising a chip peripheral region, comprising: forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the chip peripheral region; and Forming a metal from the inside of the trench over the insulating film, embedding the metal in the annular trench to form an annular metal wall, depositing a high dielectric film on the entire surface of the semiconductor substrate, and Etching the dielectric film to form an annular high dielectric film with a width expanded from the width of the metal wall in the peripheral area of the chip; depositing a wiring film on the entire surface of the semiconductor substrate; and the wiring film Ethen Forming an annular metal pad layer on the high dielectric film in the peripheral area of the chip, and forming an annular metal layer so as to extend on the insulating film at the upper end of the groove by etching the metal And a step of performing.

  According to a fifth aspect of the present invention, there is provided a fifth method of manufacturing a semiconductor device, comprising: a chip internal element region in which elements are arranged on a semiconductor substrate; and an annular seal ring that surrounds the chip internal element region and is formed on the semiconductor substrate. A method of manufacturing a semiconductor device comprising a chip peripheral region, comprising: a step of forming a first insulating film on the semiconductor substrate; and a first annular film on the first insulating film in the chip peripheral region. A step of forming a groove; a step of embedding a metal in the first annular groove to form an annular first metal wall; and depositing a first wiring film on the entire surface of the semiconductor substrate; A step of etching the high-dielectric film to form an annular high-dielectric film with a width that is larger than the width of the first metal wall in the chip peripheral region, and the entire surface of the semiconductor substrate. Depositing a second wiring film; and Etching the second wiring film to form an annular second metal pad layer having a width expanded from the width of the first metal wall in the chip peripheral region; and etching the first wiring film Forming an annular first metal pad layer in the chip peripheral region with a width expanded from the width of the first metal wall; forming a second insulating film on the semiconductor substrate; and the chip Forming a second annular groove in the second insulating film on the second metal pad layer in the peripheral region; and embedding a metal in the second annular groove to form an annular second metal wall A step of forming, a step of depositing a third wiring film on the entire surface of the semiconductor substrate, and a third metal pad layer on the second metal wall in the chip peripheral region by etching the third wiring film. Forming the step.

  According to the method for manufacturing a semiconductor device of the present invention, since the silicon nitride film, the high dielectric film, and the metal pad layer that cover the upper surface of the annular metal wall and the metal pad layer in which the depression is generated are not removed by etching, Etching residues are prevented from being generated in the recesses of the metal wall and metal pad layer, and a stable seal ring structure can be realized.

  Further, the number of manufacturing steps can be reduced by simultaneously performing the etching of the silicon nitride film or the high dielectric film and the etching of the first wiring film.

  According to the semiconductor device and the method of manufacturing the same of the present invention, the ring-shaped metal wall and the silicon nitride film covering the upper surface of the metal pad layer, the high dielectric film, and the metal pad layer are not removed by etching. Etching residue does not occur in the metal wall or the recessed portion of the metal pad layer, and generation of particles due to the etching residue can be prevented, and a stable seal ring structure can be realized.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a plan view showing a semiconductor device, FIG. 2 is an enlarged view of a portion II in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III in FIG.

  1 to 3, 1 is a scribe line, 2 is a seal ring, and 3 is an MIM capacity. An MIM capacitor 3 is formed in the chip internal element region, and annular walls 8, 11, 14 (b) and annular pads 9 (b), 12 (b), 16 (b) are formed repeatedly in the chip peripheral region. Further, an annular silicon nitride film 15 (b) wider than the annular wall 14 (b) is formed in contact with the upper portion of the annular wall 14 (b). The structure of the chip peripheral region constitutes a seal ring 2 that surrounds the chip internal element region and prevents the penetration of moisture and moisture into the chip internal element region. Claims 1 and 6 correspond to the first embodiment. In Claims 1 and 6, the annular metal wall is the annular wall 14 (b), the annular silicon nitride film is the silicon nitride film 15 (b), and the annular wall is annular. The metal pad layer corresponds to the annular pad 16 (b).

  Since the plug of the seal ring 2 is formed in a groove shape so as to surround the chip internal element region, the volume is larger than that of the cylindrical via hole, the amount of filling of the conductive film such as tungsten is insufficient, and the depression is not formed. Likely to happen. By disposing the silicon nitride film 15 (b) formed in the recess on the annular wall 14 (b) as a seal ring, it is possible to prevent etching residue from being generated in the recess when the silicon nitride film is removed. In addition, a stable seal ring structure is realized.

  The above configuration is also effective in the case where the silicon nitride film is formed in contact with the upper portion of the annular wall 8 or the annular wall 11.

  Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 6 are cross-sectional views showing manufacturing steps in the III-III cross section of FIG.

First, the manufacturing process shown in FIG. 4 will be described. A field oxide film 6 is formed on the silicon substrate 4 by thermal oxidation. Thereafter, an element such as a transistor is formed in the chip internal element region through a desired semiconductor formation process, and the P ⁺ diffusion layer 5 is formed. Then, after depositing the interlayer insulating film 7, heat treatment is performed at 850 ° C. in an N ₂ atmosphere for about 60 minutes. In this embodiment, the interlayer insulating film 7 is formed by depositing a 700 nm-thickness silicon oxide film containing boron (4.5 wt%) and phosphorus (5 wt%) on a 100 nm-thick silicon oxide film. did.

  Next, in the chip internal element region, a contact hole (not shown) is formed when it is electrically connected to the silicon substrate 4 through the interlayer insulating film 7. At this time, a first annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the contact hole and the first annular groove to form a contact plug (not shown) and a first annular wall 8.

  Next, after depositing the first wiring film, the first layer wiring 9 (a) and the first annular pad 9 (b) are formed simultaneously by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form the interlayer insulating film 10.

  Next, in the chip internal element region, a first via hole (not shown) is formed through the interlayer insulating film 10 to be electrically connected to the first layer wiring 9 (a). At this time, a second annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the first via hole and the second annular groove to form a via plug (not shown) and the second annular wall 11.

  Next, after depositing the second wiring film, the second layer wiring 12 (a) and the second annular pad 12 (b) are simultaneously formed by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form an interlayer insulating film 13.

  Next, in the chip internal element region, a second via hole is formed through the interlayer insulating film 13 to be electrically connected to the second layer wiring 12 (a). At this time, a third annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the second via hole and the third annular groove to form a via plug 14 (a) and a third annular wall 14 (b).

  As a method for embedding tungsten, a method of etching tungsten as it is after depositing it on the entire surface by the CVD method was used.

  Next, as shown in FIG. 5, the interlayer insulating film 13 is opened by etching using a photoresist as a mask in a portion where the MIM capacitor 3 is formed in the chip internal element region. Subsequently, a silicon nitride film serving as a dielectric film of the MIM capacitor 3 is deposited by CVD, and a silicon nitride film 15 (a) and an annular silicon nitride film 15 (b) are simultaneously formed by etching using a photoresist as a mask. To do.

  Next, as shown in FIG. 6, after the third wiring film is deposited, the third-layer wiring 16 (a) and the third annular pad 16 (b) are simultaneously formed by etching using a photoresist as a mask. To do. Finally, a silicon nitride protective film 17 is deposited on the entire surface as a protective film.

  According to the semiconductor device configured as described above and the method of manufacturing the same, the upper surface of the third annular wall 14 (b) where the recess is generated is covered with the silicon nitride film 15 (b), and the portion is not removed by etching. Etching residue does not occur in the recessed portion of the third annular wall 14 (b), and generation of particles due to the etching residue can be prevented, thereby realizing a stable seal ring structure.

  In addition, the silicon nitride film 15 (b) covering the depression of the third annular wall 14 (b) can be formed simultaneously with the silicon nitride film 15 (a) serving as a dielectric film, and etching residues can be reduced without increasing the number of manufacturing steps. Occurrence can be prevented.

(Second Embodiment)
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 7 is a plan view showing the semiconductor device, FIG. 8 is an enlarged view of a portion VIII in FIG. 7, and FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG.

  7 to 9, an MIM capacitor 3 is formed in the chip internal element region, and annular walls 8, 11, 14 (b) and annular pads 9 (b), 12 (b), 16 ( b) is repeatedly formed, and an annular silicon nitride film 15 (b) wider than the annular wall 11 is formed in contact with the upper part of the annular pad 12 (b), and then an annular metal 18 (b) wider than the annular wall 11 is formed. ) In contact with the upper portion of the silicon nitride film 15 (b). The structure of the chip peripheral region constitutes a seal ring 2 that surrounds the chip internal element region and prevents the penetration of moisture and moisture into the chip internal element region. Claims 2, 7, and 8 correspond to the second embodiment. In Claims 2, 7, and 8, the annular first metal wall is the annular wall 11, and the annular first metal pad layer is the annular pad. 12 (b), the annular silicon nitride film is the silicon nitride film 15 (b), the annular second metal pad layer is the annular metal 18 (b), and the annular second metal wall is the annular wall 14 (b). The annular third metal pad layer corresponds to the annular pad 16 (b).

  Since the plug of the seal ring 2 is formed in a groove shape so as to surround the chip internal element region, the volume is larger than that of the cylindrical via hole, the amount of filling of the conductive film such as tungsten is insufficient, and the depression is not formed. Likely to happen. By disposing the silicon nitride film 15 (b) and the metal 18 (b) formed in the depression on the annular pad 12 (b) as a seal ring, the metal and silicon nitride film are removed when the metal and the silicon nitride film are removed. Etching residue is prevented from being generated, and a stable seal ring structure is realized.

  Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 10 to 13 are cross-sectional views showing manufacturing steps in the IX-IX cross section of FIG.

First, the manufacturing process shown in FIG. 10 will be described. A field oxide film 6 is formed on the silicon substrate 4 by thermal oxidation. Thereafter, an element such as a transistor is formed in the chip internal element region through a desired semiconductor formation process, and the P ⁺ diffusion layer 5 is formed. Then, after depositing the interlayer insulating film 7, heat treatment is performed at 850 ° C. in an N ₂ atmosphere for about 60 minutes. In this embodiment, the interlayer insulating film 7 is formed by depositing a 700 nm-thickness silicon oxide film containing boron (4.5 wt%) and phosphorus (5 wt%) on a 100 nm-thick silicon oxide film. did.

  Next, in the chip internal element region, a contact hole (not shown) is formed when it is electrically connected to the silicon substrate 4 through the interlayer insulating film 7. At this time, a first annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the contact hole and the first annular groove to form a contact plug (not shown) and a first annular wall 8.

  Next, after depositing the first wiring film, the first layer wiring 9 (a) and the first annular pad 9 (b) are formed simultaneously by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form the interlayer insulating film 10.

  Next, in the chip internal element region, a first via hole (not shown) is formed through the interlayer insulating film 10 to be electrically connected to the first layer wiring 9 (a). At this time, a second annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the first via hole and the second annular groove to form a via plug (not shown) and the second annular wall 11.

  Next, a second-layer wiring film 12 is deposited to obtain the structure shown in FIG.

  Next, as shown in FIG. 11, after a silicon nitride film is deposited on the entire surface, a metal for the upper electrode of the MIM capacitor 3 is deposited on the entire surface.

  Next, the metal for the upper electrode of the MIM capacitor 3 is etched by etching using a photoresist as a mask to form the MIM upper electrode metal 18 (a), and at the same time, the annular metal 18 (b) is formed. Next, the silicon nitride film is etched by etching using a photoresist as a mask to form a silicon nitride film 15 (a) and an annular silicon nitride film 15 (b). The shape processing of the silicon nitride film 15 (a) and the annular silicon nitride film 15 (b) may be combined with the shape processing of the second layer wiring and the second annular pad. More simply, the silicon nitride film 15 (a) and the annular silicon nitride film 15 (b) may be formed simultaneously by etching the second layer wiring and the second annular pad.

  Next, as shown in FIG. 12, the second layer wiring 12 (a) and the second annular pad 12 (b) are formed. Subsequently, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form an interlayer insulating film 13.

  Next, in the chip internal element region, a second via hole is formed through the interlayer insulating film 13 to be electrically connected to the second layer wiring 12 (a). At this time, a third annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the second via hole and the third annular groove to form a via plug 14 (a) and a third annular wall 14 (b).

  As a method for embedding tungsten, a method of etching tungsten as it is after depositing it on the entire surface by the CVD method was used.

  Next, as shown in FIG. 13, after the third wiring film is deposited, the third-layer wiring 16 (a) and the third annular pad 16 (b) are simultaneously formed by etching using a photoresist as a mask. To do. Finally, a silicon nitride protective film 17 is deposited on the entire surface as a protective film.

  According to the semiconductor device configured as described above and the method of manufacturing the same, the upper surface of the second annular pad 12 (b) where the recess is generated is covered with the silicon nitride film 15 (b) and the annular metal 18 (b). Since this portion is not removed by etching, no etching residue is generated in the recess of the second annular pad 12 (b), and generation of particles due to the etching residue is prevented, thereby realizing a stable seal ring structure. Can do.

  Further, the silicon nitride film 15 (b) and the annular metal 18 (b) covering the recess of the second annular pad 12 (b) are replaced with the silicon nitride film 15 (a) serving as a dielectric film and the MIM upper electrode metal 18 ( It can be formed simultaneously with a), and the generation of etching residues can be prevented without increasing the number of manufacturing steps.

  Furthermore, the number of manufacturing steps can be reduced by simultaneously etching the silicon nitride film 15 and etching the wiring film 18.

(Third embodiment)
A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 14 is a plan view showing the semiconductor device, FIG. 15 is an enlarged view of a portion XV in FIG. 14, and FIG. 16 is a cross-sectional view along XVI-XVI in FIG.

  14 to 16, an MIM capacitor 3 is formed in the chip internal element region, and annular walls 8 and 11 and annular pads 9 (b) and 12 (b) are formed repeatedly in the chip peripheral region. An annular silicon oxynitride film 19 (b) wider than 11 is formed in contact with the top of the annular pad 12 (b), and then an annular metal 18 (b) wider than the annular wall 11 is formed in the silicon oxynitride film 19 (b ) In contact with the top. Further, the annular wall 14 (b) is formed away from the metal 18 (b) and the silicon oxynitride film 19 (b), and the annular wall 14 (b) is connected to the annular pad 12 (b). The pad 12 (b) is electrically connected to the annular pad 16 (b) through the annular wall 14 (b). Even in the case of a film having a higher hygroscopicity than the silicon nitride film, such as the annular silicon oxynitride film 19 (b), the structure of the chip peripheral region surrounds the chip internal element region and leads to the chip internal element region. The seal ring 2 for preventing the penetration of moisture and moisture can be formed. Claims 3, 9, and 10 correspond to the third embodiment. In Claims 3, 9, and 10, the annular first metal wall is the annular wall 11, and the annular first metal pad layer is the annular pad. 12 (b), an annular high dielectric film is an annular silicon oxynitride film 19 (b), an annular second metal pad layer is an annular metal 18 (b), and an annular second metal wall is an annular wall 14 (b), the annular third metal pad layer corresponds to the annular pad 16 (b).

  Since the plug of the seal ring 2 is formed in a groove shape so as to surround the chip internal element region, the volume is larger than that of the cylindrical via hole, the amount of filling of the conductive film such as tungsten is insufficient, and the depression is not formed. Likely to happen. When the silicon oxynitride film 19 (b) and the metal 18 (b) formed in the depression on the annular pad 12 (b) are arranged as a seal ring, the depression is obtained when the metal and the silicon oxynitride film are removed. Etching residue is prevented from occurring in the part, and a stable seal ring structure is realized.

  Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 17 and 18 are cross-sectional views showing manufacturing steps in the XVI-XVI cross section of FIG.

  First, the structure shown in FIG. 10 and then the structure shown in FIG. 11 are obtained by a method similar to the description of the manufacturing process of the second embodiment.

  Next, as shown in FIG. 17, the second layer wiring 12 (a) and the second annular pad 12 (b) are formed. At this time, the second annular pad 12 (b) is formed so as to be wider than the annular metal 18 (b).

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form an interlayer insulating film 13.

  Next, in the chip internal element region, a second via hole is formed through the interlayer insulating film 13 to be electrically connected to the second layer wiring 12 (a). At this time, a third annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the second via hole and the third annular groove to form a via plug 14 (a) and a third annular wall 14 (b). At this time, the third annular wall 14 (b) is connected to the second annular pad 12 (b).

  Next, as shown in FIG. 18, after the third wiring film is deposited, the third layer wiring 16 (a) and the third annular pad 16 (b) are simultaneously formed by etching using a photoresist as a mask. To do. Finally, a silicon nitride protective film 17 is deposited on the entire surface as a protective film.

  According to the semiconductor device configured as described above and the manufacturing method thereof, the upper surface of the second annular pad 12 (b) in which the recess is generated is covered with the silicon oxynitride film 19 (b) and the annular metal 18 (b). Since this portion is not removed by etching, no etching residue is generated in the recessed portion of the second annular pad 12 (b), and generation of particles caused by the etching residue is prevented, thereby realizing a stable seal ring structure. be able to.

  Further, the silicon oxynitride film 19 (b) and the annular metal 18 (b) covering the recess of the second annular pad 12 (b) are replaced with the silicon oxynitride film 19 (a) and the MIM upper electrode metal that serve as a dielectric film. 18 (a) can be formed at the same time, and the generation of etching residues can be prevented without increasing the number of manufacturing steps.

  Further, the number of manufacturing steps can be reduced by simultaneously performing the etching of the silicon oxynitride film 19 and the etching of the wiring film 18.

  Furthermore, since the third annular pad 16 (b) and the second annular pad 12 (b) are electrically connected, it is also effective in a seal ring in a manufacturing process for forming a dielectric film having a higher hygroscopicity than the silicon nitride film. .

(Fourth embodiment)
A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 19 is a plan view showing the semiconductor device, FIG. 20 is an enlarged view of a portion XX in FIG. 19, and FIG. 21 is a cross-sectional view along XXI-XXI in FIG.

  19 to 21, an MIM capacitor 3 is formed in the chip internal element region, and annular walls 8, 11, 14 (b) and annular pads 9 (b), 12 (b), 16 ( b) is formed repeatedly. Further, an annular metal 20 (b) formed extending from the side surface of the annular wall 14 (b), and is in contact with the metal 20 (b) and is narrower than the metal 20 (b) than the annular wall 14 (b). A wide annular silicon oxynitride film 19 (b) is formed, and the annular pad 16 (b) is formed wider than the silicon oxynitride film 19 (b). Thereby, the annular wall 14 (b) is electrically connected to the annular pad 16 (b) via the annular metal 20 (b). Even in the case of a film having a higher hygroscopicity than the silicon nitride film, such as the annular silicon oxynitride film 19 (b), the structure of the chip peripheral region surrounds the chip internal element region and leads to the chip internal element region. The seal ring 2 for preventing the penetration of moisture and moisture can be formed. Claims 4 and 11 correspond to the fourth embodiment, and the annular metal wall in claims 4 and 11 is the annular wall 14 (b), the annular metal layer is the annular metal 20 (b), and the annular The high dielectric film corresponds to the annular silicon oxynitride film 19 (b), and the annular metal pad layer corresponds to the annular pad 16 (b).

  Since the plug of the seal ring 2 is formed in a groove shape so as to surround the chip internal element region, the volume is larger than that of the cylindrical via hole, the amount of filling of the conductive film such as tungsten is insufficient, and the depression is not formed. Likely to happen. When the silicon oxynitride film 19 (b) is removed by disposing the silicon oxynitride film 19 (b) formed in the depression on the annular wall 14 (b) as a seal ring, an etching residue is left in the depression. Is prevented, and a stable seal ring structure is realized.

  The above configuration is also effective in the case where the silicon oxynitride film is formed in contact with the upper portion of the annular wall 8 or the annular wall 11.

  Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 22 to 24 are cross-sectional views showing manufacturing steps in the XXI-XXI cross section of FIG.

First, the manufacturing process shown in FIG. 22 will be described. A field oxide film 6 is formed on the silicon substrate 4 by thermal oxidation. Thereafter, an element such as a transistor is formed in the chip internal element region through a desired semiconductor formation process, and the P ⁺ diffusion layer 5 is formed. Then, after depositing the interlayer insulating film 7, heat treatment is performed at 850 ° C. in an N ₂ atmosphere for about 60 minutes. In this embodiment, the interlayer insulating film 7 is formed by depositing a 700 nm-thickness silicon oxide film containing boron (4.5 wt%) and phosphorus (5 wt%) on a 100 nm-thick silicon oxide film. did.

  Next, in the chip internal element region, a contact hole (not shown) is formed when it is electrically connected to the silicon substrate 4 through the interlayer insulating film 7. At this time, a first annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the contact hole and the first annular groove to form a contact plug (not shown) and a first annular wall 8.

  Next, after depositing the first wiring film, the first layer wiring 9 (a) and the first annular pad 9 (b) are formed simultaneously by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form the interlayer insulating film 10.

  Next, in the chip internal element region, a first via hole (not shown) is formed through the interlayer insulating film 10 to be electrically connected to the first layer wiring 9 (a). At this time, a second annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the first via hole and the second annular groove to form a via plug (not shown) and the second annular wall 11.

  Next, after depositing the second wiring film, the second layer wiring 12 (a) and the second annular pad 12 (b) are simultaneously formed by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form an interlayer insulating film 13.

  Next, in the chip internal element region, a second via hole is formed through the interlayer insulating film 13 to be electrically connected to the second layer wiring 12 (a). At this time, a third annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the second via hole and the third annular groove to form a via plug 14 (a) and a third annular wall 14 (b).

  As a method for embedding tungsten, a method of etching tungsten as it is after depositing it on the entire surface by the CVD method was used. At the end of this etching, the Ti and TiN films 20 grown before growing tungsten were left on the entire surface.

  Next, the Ti and TiN films in the region of the MIM capacitor 3 are etched by etching using a photoresist as a mask.

  Next, as shown in FIG. 23, in the region of the MIM capacitor 3, the interlayer insulating film 13 is etched and opened by etching using a photoresist as a mask. Subsequently, a silicon oxynitride film serving as a dielectric film of the MIM capacitor 3 is deposited by the CVD method, and the silicon oxynitride film 19 (a) and the annular silicon oxynitride film 19 (b) are etched by using a photoresist as a mask. Are formed at the same time.

  Next, as shown in FIG. 24, after the third wiring film is deposited, the third-layer wiring 16 (a), the third annular pad 16 (b), Ti, A metal 20 (a) and an annular metal 20 (b) made of TiN are formed simultaneously. Finally, a silicon nitride protective film 17 is deposited on the entire surface as a protective film.

  According to the semiconductor device configured as described above and the manufacturing method thereof, the upper surface of the third annular wall 14 (b) in which the depression is generated is covered with the silicon oxynitride film 19 (b), and the portion is not removed by etching. Therefore, no etching residue is generated in the recessed portion of the third annular wall 14 (b), and generation of particles due to the etching residue can be prevented, and a stable seal ring structure can be realized.

  Further, the silicon oxynitride film 19 (b) covering the depression of the third annular wall 14 (b) can be formed simultaneously with the silicon oxynitride film 19 (a) serving as a dielectric film, and etching is performed without increasing the number of manufacturing steps. Generation of residue can be prevented.

(Fifth embodiment)
A semiconductor device according to the fifth embodiment of the present invention will be described below with reference to FIGS. 25 is a plan view showing the semiconductor device, FIG. 26 is an enlarged view of the XXVI portion of FIG. 25, and FIG. 27 is a sectional view taken along the line XXVII-XXVII of FIG.

  25 to 27, the MIM capacitor 3 is formed in the chip internal element region, and the annular walls 8, 11, 14 (b) and the annular pads 9 (b), 12 (b), 16 ( b) is formed repeatedly. Further, an annular silicon oxynitride film 19 (b) wider than the annular wall 11 is formed in contact with the upper portion of the annular pad 12 (b), and subsequently wider than the annular wall 11 and the annular silicon oxynitride film 19 (b). An annular metal 18 (b) is formed in contact with the upper portion of the silicon oxynitride film 19 (b). Thereby, the annular pad 12 (b) is electrically connected to the annular wall 14 (b) through the annular metal 18 (b). Even in the case of a film having a higher hygroscopicity than the silicon nitride film, such as the annular silicon oxynitride film 19 (b), the structure of the chip peripheral region surrounds the chip internal element region and leads to the chip internal element region. The seal ring 2 for preventing the penetration of moisture and moisture can be formed. In addition, Claims 5 and 12 correspond to the fifth embodiment, and the annular first metal wall in Claims 5 and 12 is the annular wall 11, and the annular first metal pad layer is the annular pad 12 (b). The annular high dielectric film is an annular silicon oxynitride film 19 (b), the annular second metal pad layer is an annular metal 18 (b), and the annular second metal wall is an annular wall 14 (b). The annular third metal pad layer corresponds to the annular pad 16 (b).

  Since the plug of the seal ring 2 is formed in a groove shape so as to surround the chip internal element region, the volume is larger than that of the cylindrical via hole, the amount of filling of the conductive film such as tungsten is insufficient, and the depression is not formed. Likely to happen. When the silicon oxynitride film 19 (b) and the metal 18 (b) formed in the depression on the annular pad 12 (b) are arranged as a seal ring, the depression is obtained when the metal and the silicon oxynitride film are removed. Etching residue is prevented from occurring in the part, and a stable seal ring structure is realized.

  Next, a method for fabricating a semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIGS. 28 to 31 are cross-sectional views showing manufacturing steps in the XXVII-XXVII cross-section of FIG.

First, the manufacturing process shown in FIG. 28 will be described. A field oxide film 6 is formed on the silicon substrate 4 by thermal oxidation. Thereafter, an element such as a transistor is formed in the chip internal element region through a desired semiconductor formation process, and the P ⁺ diffusion layer 5 is formed. Then, after depositing the interlayer insulating film 7, heat treatment is performed at 850 ° C. in an N ₂ atmosphere for about 60 minutes. In this embodiment, the interlayer insulating film 7 is formed by depositing a 700 nm-thickness silicon oxide film containing boron (4.5 wt%) and phosphorus (5 wt%) on a 100 nm-thick silicon oxide film. did.

  Next, in the chip internal element region, a contact hole (not shown) is formed when it is electrically connected to the silicon substrate 4 through the interlayer insulating film 7. At this time, a first annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the contact hole and the first annular groove to form a contact plug (not shown) and a first annular wall 8.

  Next, after depositing the first wiring film, the first layer wiring 9 (a) and the first annular pad 9 (b) are formed simultaneously by etching using a photoresist as a mask.

  Next, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form the interlayer insulating film 10.

  Next, in the chip internal element region, a first via hole (not shown) is formed through the interlayer insulating film 10 to be electrically connected to the first layer wiring 9 (a). At this time, a second annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the first via hole and the second annular groove to form a via plug (not shown) and the second annular wall 11.

  Next, a second wiring film is deposited to obtain the structure shown in FIG.

  Next, as shown in FIG. 29, after the silicon oxynitride film is deposited on the entire surface, the silicon oxynitride film is etched by etching using a photoresist as a mask, so that the silicon oxynitride film 19 (a) is circular. The silicon oxynitride film 19 (b) is formed.

  Subsequently, after depositing MIM upper electrode metal on the entire surface, the MIM upper electrode metal 18 (a) is formed by etching the MIM upper electrode metal by etching using a photoresist as a mask.

  Next, as shown in FIG. 30, the second layer wiring 12 (a), the second annular pad 12 (b), and the annular metal 18 (b) are formed by etching using a photoresist as a mask.

  Subsequently, after depositing a silicon oxide insulating film by the P-CVD method, a planarization process is performed by a resist etch back method or CMP to form an interlayer insulating film 13.

  Next, in the chip internal element region, a second via hole is formed through the interlayer insulating film 13 to be electrically connected to the second layer wiring 12 (a). At this time, a third annular groove is formed in the seal ring 2 in the chip peripheral region so as to surround the chip internal element region. Then, tungsten is buried in both the second via hole and the third annular groove to form a via plug 14 (a) and a third annular wall 14 (b).

  As a method for embedding tungsten, a method of etching tungsten as it is after depositing it on the entire surface by the CVD method was used.

  Next, as shown in FIG. 31, after the third wiring film is deposited, the third layer wiring 16 (a) and the third annular pad 16 (b) are simultaneously formed by etching using a photoresist as a mask. To do. Finally, a silicon nitride protective film 17 is deposited on the entire surface as a protective film.

  According to the semiconductor device configured as described above and the manufacturing method thereof, the upper surface of the second annular pad 12 (b) in which the recess is generated is covered with the silicon oxynitride film 19 (b) and the annular metal 18 (b). Since this portion is not removed by etching, no etching residue is generated in the recessed portion of the second annular pad 12 (b), and generation of particles caused by the etching residue is prevented, thereby realizing a stable seal ring structure. be able to.

  Further, the silicon oxynitride film 19 (b) and the annular metal 18 (b) covering the recess of the second annular pad 12 (b) are replaced with the silicon oxynitride film 19 (a) and the MIM upper electrode metal that serve as a dielectric film. 18 (a) can be formed at the same time, and the generation of etching residues can be prevented without increasing the number of manufacturing steps.

  In the first to fifth embodiments, the example in which the MIM capacitor 3 is provided in the chip internal element region has been described. However, the element provided in the chip internal element region is not limited to the capacitor.

  INDUSTRIAL APPLICABILITY The present invention is useful for a semiconductor device or the like that is an integrated circuit using an MIM capacitor and has a seal ring that prevents the penetration of moisture and moisture into the chip internal region.

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. Enlarged view of part II in Fig. 1 III-III sectional view of Fig. 1 Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The top view which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. Enlarged view of part VIII in Figure 7 IX-IX cross section of FIG. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. The top view which shows the semiconductor device which concerns on the 3rd Embodiment of this invention. Enlarged view of XV part in Fig. 14 XVI-XVI cross section of Fig. 14 Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. A top view showing a semiconductor device concerning a 4th embodiment of the present invention. Enlarged view of part XX in Figure 19 XXI-XXI cross section of Figure 19 Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. A top view showing a semiconductor device concerning a 5th embodiment of the present invention. Enlarged view of the XXVI part in Figure 25 XXVII-XXVII sectional view of FIG. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. Plan view showing a conventional semiconductor device Enlarged view of XXXIII part in Fig. 32 XXXIV-XXXIV sectional view of Fig. 32 The top view which shows the semiconductor device of another prior art example XXXVI part enlarged view of FIG. XXXVII-XXXVII sectional view of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Scribe line 2 Seal ring 3 MIM capacity 4 Silicon substrate 5 P ⁺ diffusion layer 6 Field oxide film 7 Interlayer insulating film 8 1st annular wall (annular metal wall)
9 (a) First layer wiring 9 (b) First annular pad (annular metal pad layer)
10 Interlayer insulating film 11 Second annular wall (annular metal wall)
12 Second-layer wiring film 12 (a) Second-layer wiring 12 (b) Second annular pad (annular metal pad layer)
13 Interlayer insulating film 14 (a) Via plug 14 (b) Third annular wall (annular metal wall)
15 (a) Silicon nitride film (capacitor dielectric film)
15 (b) Silicon nitride film 16 (a) Third layer wiring 16 (b) Third annular pad (annular metal pad layer)
17 Silicon nitride protective film 18 (a) MIM upper electrode metal 18 (b) Ring metal (ring metal pad layer)
19 (a) Silicon oxynitride film (capacitor dielectric film)
19 (b) Silicon oxynitride film (high dielectric film)
20 Ti, TiN film 20 (a) Metal 20 (b) Annular metal (annular metal layer)

Claims (12)

A semiconductor device comprising a chip internal element region in which elements are arranged on a semiconductor substrate, and a chip peripheral region that surrounds the chip internal element region and forms an annular seal ring on the semiconductor substrate. ,
The seal ring includes an annular metal wall formed by embedding metal in an annular groove, an annular silicon nitride film covering the upper surface of the metal wall with a width wider than the width of the metal wall, and an upper surface of the silicon nitride film And a ring-shaped metal pad layer covering the substrate. A semiconductor device comprising a chip internal element region in which elements are arranged on a semiconductor substrate, and a chip peripheral region that surrounds the chip internal element region and forms an annular seal ring on the semiconductor substrate. ,
The seal ring includes an annular first metal wall formed by embedding a metal in an annular groove, and an annular first metal pad layer formed so as to be conductive on the first metal wall; An annular silicon nitride film formed on the first metal pad layer and in contact with the first metal wall; and a width wider than the width of the first metal wall on the silicon nitride film. An annular second metal pad layer formed of
The second metal pad layer is electrically connected to an annular third metal pad layer formed at a position higher than the second metal pad layer through an annular second metal wall. A semiconductor device. A semiconductor device comprising a chip internal element region in which elements are arranged on a semiconductor substrate, and a chip peripheral region that surrounds the chip internal element region and forms an annular seal ring on the semiconductor substrate. ,
The seal ring includes an annular first metal wall formed by embedding a metal in an annular groove, and an annular first metal pad layer formed so as to be conductive on the first metal wall; An annular high dielectric film formed on the first metal pad layer in contact with the first metal wall and wider than the first metal wall; and on the high dielectric film, in contact with the first metal wall. An annular second metal pad layer formed in a wide width,
A width of the first metal pad layer is formed wider than a width of the second metal pad layer, and the first metal pad layer is interposed between the second metal pad layer via an annular second metal wall. A semiconductor device, wherein the semiconductor device is electrically connected to an annular third metal pad layer formed at a position higher than the pad layer. A semiconductor device comprising a chip internal element region in which elements are arranged on a semiconductor substrate, and a chip peripheral region that surrounds the chip internal element region and forms an annular seal ring on the semiconductor substrate. ,
The seal ring is formed between an annular metal wall formed by embedding a metal in an annular groove provided in the insulating film, and is formed between the groove and the metal wall and extends on the insulating film at an upper end of the groove. An annular metal layer formed on the metal layer, and an annular high dielectric film formed on the metal layer so as to cover the upper surface of the metal wall with a width narrower than the metal layer and wider than the metal wall, and the high dielectric An annular metal pad layer covering the membrane,
The semiconductor device, wherein the metal wall is electrically connected to the metal pad layer through the metal layer. A semiconductor device comprising a chip internal element region in which elements are arranged on a semiconductor substrate, and a chip peripheral region that surrounds the chip internal element region and forms an annular seal ring on the semiconductor substrate. ,
The seal ring includes an annular first metal wall formed by embedding metal in an annular groove, and an annular first metal pad layer formed so as to be conductive on the first metal wall; An annular high dielectric film formed on and in contact with the first metal pad layer and covering the upper surface of the first metal pad layer with a width narrower than the first metal pad layer and wider than the first metal wall; An annular second metal pad layer covering the high dielectric film,
The first metal pad layer and the second metal pad layer are in contact and conductive,
The second metal pad layer is electrically connected to an annular third metal pad layer formed at a position higher than the second metal pad layer through an annular second metal wall. A semiconductor device. A method for manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and a chip peripheral region surrounding the chip internal element region and forming an annular seal ring on the semiconductor substrate. Because
Forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the peripheral area of the chip; embedding a metal in the annular groove to form an annular metal wall; and the semiconductor Depositing a silicon nitride film on the entire surface of the substrate; etching the silicon nitride film to form an annular silicon nitride film with a width expanded from the width of the metal wall in the chip peripheral region; and A method of manufacturing a semiconductor device, comprising: depositing a wiring film on the substrate; and etching the wiring film to form an annular metal pad layer on the silicon nitride film in the chip peripheral region. A method for manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and a chip peripheral region surrounding the chip internal element region and forming an annular seal ring on the semiconductor substrate. Because
Forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the peripheral area of the chip; embedding a metal in the annular groove to form an annular metal wall; and the semiconductor After depositing a first wiring film on the entire surface of the substrate, a silicon nitride film is deposited, and then a second wiring film is deposited; and the second wiring film is etched to form the metal in the chip peripheral region. Forming an annular second metal pad layer having a width expanded from the width of the wall; and etching the silicon nitride film to form an annular silicon nitride film having a width expanded from the width of the metal wall in the chip peripheral region And a step of etching the first wiring film to form an annular first metal pad layer having a width expanded from the width of the metal wall in the chip peripheral region. Semiconductor device Manufacturing method.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching of the silicon nitride film and the etching of the first wiring film are performed simultaneously. A method for manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and a chip peripheral region surrounding the chip internal element region and forming an annular seal ring on the semiconductor substrate. Because
Forming a first insulating film on the semiconductor substrate; forming a first annular groove in the first insulating film in the chip peripheral region; and embedding metal in the first annular groove. Forming a ring-shaped first metal wall; depositing a first wiring film on the entire surface of the semiconductor substrate; depositing a high dielectric film; and subsequently depositing a second wiring film; Etching the second wiring film to form an annular second metal pad layer having a width expanded from the width of the first metal wall in the chip peripheral region; and etching the high dielectric film Forming a ring-shaped high-dielectric film with a width expanded from the width of the first metal wall in the chip peripheral region; and etching the first wiring film to form the first metal in the chip peripheral region. More wide than the wall and more than the width of the second metal pad layer Forming an annular first metal pad layer arranged in a wide area; forming a second insulating film on the semiconductor substrate; and separating the second metal pad layer in the peripheral area of the chip from the second metal pad layer. Forming a second annular groove in the second insulating film on one metal pad layer; and embedding a metal in the second annular groove to form an annular second metal wall; Depositing a third wiring film on the entire surface of the semiconductor substrate; etching the third wiring film to form a third metal pad layer on the second metal wall in the chip peripheral region; A method for manufacturing a semiconductor device, comprising:   10. The method of manufacturing a semiconductor device according to claim 9, wherein the etching of the high dielectric film and the etching of the first wiring film are performed simultaneously. A method for manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and a chip peripheral region surrounding the chip internal element region and forming an annular seal ring on the semiconductor substrate. Because
Forming an insulating film on the semiconductor substrate; forming an annular groove in the insulating film in the peripheral area of the chip; and forming a metal over the insulating film from within the annular groove; Forming a ring-shaped metal wall by embedding metal in the substrate, depositing a high dielectric film on the entire surface of the semiconductor substrate, and etching the high dielectric film to form a peripheral region of the chip from the width of the metal wall Forming an annular high dielectric film with an expanded width; depositing a wiring film on the entire surface of the semiconductor substrate; etching the wiring film to form an annular high dielectric film on the chip peripheral region; A method of manufacturing a semiconductor device, comprising: forming a metal pad layer; and etching the metal to form an annular metal layer so as to extend on the insulating film at an upper end of the groove. A method for manufacturing a semiconductor device, comprising: a chip internal element region formed by disposing elements on a semiconductor substrate; and a chip peripheral region surrounding the chip internal element region and forming an annular seal ring on the semiconductor substrate. Because
Forming a first insulating film on the semiconductor substrate; forming a first annular groove in the first insulating film in the chip peripheral region; and embedding metal in the first annular groove. Forming a first annular metal wall; depositing a first dielectric film on the entire surface of the semiconductor substrate; and depositing a high dielectric film; and etching the high dielectric film to surround the chip Forming a ring-shaped high dielectric film in a region with a width expanded from the width of the first metal wall; depositing a second wiring film on the entire surface of the semiconductor substrate; and Etching to form an annular second metal pad layer having a width expanded from the width of the first metal wall in the chip peripheral region; and etching the first wiring film in the chip peripheral region. An annular first meta with a width expanded from the width of the first metal wall. A step of forming a pad layer; a step of forming a second insulating film on the semiconductor substrate; and a second annular film on the second insulating film on the second metal pad layer in the peripheral area of the chip. A step of forming a groove, a step of embedding a metal in the second annular groove to form an annular second metal wall, a step of depositing a third wiring film on the entire surface of the semiconductor substrate, and the third And etching the wiring film to form a third metal pad layer on the second metal wall in the chip peripheral region.

Images