JP2006269456A - Mulitlayer printed wiring board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a highly dense multilayer printed wiring board by reducing complication of processes and cost raise due to increases in times of perforation and plating, and stabilizing interlayer alignment accuracy in a sequential laminate method. <P>SOLUTION: Pins 30, 31 are formed on vias 10, 12 of a sub-assembly wiring board 1. These pins 30, 31 are inserted into vias 11, 13 of an opposing sub-assembly 2, and the pins are positioned, and thus, a substrate excellent in interlayer alignment accuracy of the sub-assembly wiring boards 1, 2 can be manufactured. The use of a material excellent in electric conductivity for the pins can electrically connect the two pairs of vias 10, 11 and 12, 13 which oppose each other. Also, the pins can improve hermetical performance and change thermal conductivity of the substrate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multilayer printed wiring board and a manufacturing method thereof, and more particularly to a multilayer printed wiring board suitable for laminating at least two subassembly wiring boards by a sequential lamination method and a manufacturing method thereof.

  A printed wiring board is generally formed by forming a conductor pattern on a copper-clad laminate, glass epoxy material, etc., and then laminating those laminates, outer layer copper foil, prepreg, etc. and simultaneously applying pressure under heating. Laminate. In order to electrically connect signals and power between different layers, vias that penetrate the entire multilayer printed wiring board are processed, but in this manufacturing method, via processing is also performed on layers that do not require interlayer connection. There existed a subject that the wiring space of the whole multilayer printed wiring board did not increase.

  In order to solve this problem, printed wiring boards have been devised in which non-through vias (also referred to as blind vias) are processed to connect only necessary layers. One of them is a manufacturing method called a sequential laminating method in which a plurality of subassembly wiring boards are produced in advance and then laminated together.

  This sequential lamination method will be described with reference to FIGS. Reference numerals 7 and 8 in the figure are sub-assembly wiring boards manufactured in advance by laminating, drilling and plating, respectively, and these two sheets are laminated to face each other via the prepreg 23 (see FIG. 5). . In this laminated wiring board 9 (see FIG. 6), 7 conductor layers can be connected by vias 40, 8 conductor layers can be connected by vias 41, and 7 and 8 conductor layers can be connected by through vias 42 and 43. (See FIG. 7).

"Printo Banjuku", written by Masaru Kobayashi, published by Nippon Printed Circuit Industry, 1998, 1st edition, 4th edition, pages 77-81

  In the sequential lamination method, in order to process the vias 40 and 41, drilling and plating are performed in the state of the subassembly wiring boards 7 and 8 in FIG. 5, and in order to process the through vias 42 and 43 in FIG. Drilling and plating are performed in the state 9 shown in FIG. For this reason, the number of times of lamination / drilling / plating increases, the manufacturing process becomes complicated, and the cost increases.

  In addition, a dedicated reference hole is used for alignment of the conductor layers of the sub-assembly wiring boards 7 and 8 at the time of lamination, but this method makes it difficult to improve accuracy as the number of layers increases. Stability of deviation accuracy becomes an issue.

  Accordingly, an object of the present invention is to provide a high-density multilayer wiring board that can be manufactured at a low cost and has a stable interlayer misalignment accuracy, and a method for manufacturing the same.

  A method of forming a part of a pin in a via on one surface of two opposing surfaces of a sub-assembly wiring board to be stacked and inserting the remaining portion of the pin into a via of the other sub-assembly wiring board facing when stacked Perform interlayer alignment with. The opposing vias are connected via pins, so if you use pins with excellent electrical conductivity, you can connect the conductors electrically and eliminate the drilling and plating process. .

  Positioning accuracy can be improved by forming pins in vias of sub-assembly wiring boards that are stacked opposite to each other and performing conductor layer alignment by aligning the vias via the pins. Further, by changing the characteristics of the pins, the electrical connection between the layers can be realized only by the pins, and the drilling and plating process after the lamination can be eliminated. Furthermore, it becomes possible to improve the airtightness of the front and back surfaces of the substrate and to change the thermal conductivity.

Features of representative embodiments of the present invention are exemplified below.
(1) A method of manufacturing a multilayer printed wiring board including a step of laminating sub-assembly wiring boards in which vias are formed in advance via a prepreg, and in the step of laminating the sub-assembly wiring boards, Inserting a part of a pin into a via on one surface of a subassembly wiring board to be aligned, and aligning a via of another subassembly wiring board opposite to the via of the subassembly wiring board into which the pin is inserted; And a step of inserting and laminating the remaining portions of the pins into vias of other subassembly wiring boards facing each other.
(2) In the method for manufacturing a multilayer printed wiring board according to (1), the pin is formed of a conductor.
(3) The multilayer printed wiring board of the present invention is manufactured by the method for manufacturing a multilayer printed wiring board according to the above (1) or (2).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<Example 1>
FIG. 1 is a longitudinal sectional view of a multilayer wiring board according to a first embodiment of the present invention, and FIG. 2 is a three-dimensional view.
In FIG. 1, 1 and 2 are sub-assembly wiring boards each having 12 layers, 10 to 15 are through vias provided in the sub-assembly wiring boards 1 and 2, 20 is a prepreg, and 30 and 31 are pins.

  In FIG. 1, a pin 30 is formed in the via 10 and a pin 31 is formed in the via 12 of the subassembly wiring board 1.

  In forming the pins 30 and 31 in the vias 10 and 12, conductor pins of a size that can be press-fitted into the vias are prepared in advance, a part of the pins is press-fitted into the vias, and the other part is inserted into the sub-assembly wiring board 1. Leave outside. In this example, pins are formed on the subassembly wiring board 1 side, but they may be provided on the opposing subassembly wiring board 2 side (see FIG. 2).

  Note that some of the vias provided in the subassembly wiring boards 1 and 2 are disposed at positions facing each other on the facing surfaces.

  When the sub-assembly wiring boards 1 and 2 are stacked, the sub-assembly wiring boards 1 and 2 are stacked with the prepreg 20 serving as an interlayer insulating film interposed therebetween. The conductor layer alignment reference at the time of stacking is the via 10 used as a conductor. In FIG. 1, vias 10 and 11 are positioned by pins 30 and vias 12 and 13 are positioned by pins 31. The vias 14 and 15 are not formed with pins because there are no vias in the subassembly wiring boards facing each other. The press and bonding processes after positioning are the same as conventional ones.

Also in FIG. 2, positioning is performed by matching the pin 30 formed in the via 11 of the subassembly wiring board 2 with the via 10 of the subassembly wiring board 1.
By changing the diameter of the pin 30, it is possible to form vias having various diameters, and to arbitrarily change the length according to the thickness of the subassembly wiring board.

  As a result, the processing of the dedicated reference hole required for conventional conductor layer matching is eliminated. Furthermore, since the conductor layer is aligned with the via 10 and the pin 30, it is possible to manufacture a substrate with reduced pattern deviation.

<Example 2>
FIG. 3 is a longitudinal sectional view of a multilayer wiring board according to Embodiment 2 of the present invention.
3 and 4 in FIG. 3 are sub-assembly wiring boards each composed of 12 layers, 16 and 17 are through vias, 21 is a prepreg, and 32 is a pin.

  In the figure, the manufacturing method for aligning the conductor layers by raising the pins 32 to the vias 16 of the subassembly wiring board 3 and matching the 32 to the vias 17 is the same as that in Example 1, but in Example 2 of the present invention, These pins 32 are applied by changing the electric conductivity.

  The vias 17 of the subassembly wiring board 4 facing the vias 16 of the subassembly wiring board 3 are connected to each other by pins 32 press-fitted into the vias. By making the electrical conductivity of the pin 32 excellent, the via 16 and the via 17 are electrically connected. Further, if the pin 32 is made of an insulator, connection between the two (via 16 and via 17) can be avoided.

  Conventionally, as shown in FIG. 7, through-vias 42 and 43 are required to connect the sub-assembly wiring boards 7 and 8, but any vias can be electrically connected according to the present invention. Is no longer necessary.

<Example 3>
FIG. 4 shows a longitudinal sectional view of a multilayer wiring board in Example 3 of the present invention.
4, 5 and 6 are sub-assembly wiring boards each having 12 layers, 18 and 19 are through vias, 22 is a prepreg, and 33 is a pin.

  In FIG. 4, the manufacturing method of aligning the conductor layer by raising a part of the pin 33 on the via 18 of the subassembly wiring board 5 and aligning the other part of the pin 33 with the via 19 is the same as in the first and second embodiments. However, in the third embodiment of the present invention, the thermal conductivity of these pins 33 is changed and applied.

  In FIG. 4, the via 18 of one subassembly wiring board 5 and the via 19 of the other subassembly wiring board 6 facing each other through the prepreg 22 are connected by pins 33. Conventionally, when operating with a temperature difference between the front surface and the back surface of a printed circuit board, the through via 44 is filled with an insulating resin 50 as shown in FIG. Was maintained.

  In the present invention, since the pin 33 in FIG. 4 is located between the vias 18 and 19, the front and back surfaces can be blocked without resin filling. In addition, it is possible to suppress the heat conduction of the printed wiring board itself by manufacturing the pin with a material having a low thermal conductivity (such as a resin).

It is a schematic longitudinal cross-sectional view of the multilayer wiring board explaining Example 1 of this invention. It is a three-dimensional figure of the multilayer wiring board explaining Example 1 of this invention. It is a longitudinal cross-sectional view explaining the structure of the multilayer wiring board in Example 2 of this invention. It is a longitudinal cross-sectional view explaining the structure of the multilayer wiring board in Example 3 of this invention. It is a longitudinal cross-sectional view of the conventional printed wiring board. It is a longitudinal cross-sectional view of the conventional printed wiring board. It is a longitudinal cross-sectional view which shows the manufacturing method of the conventional printed wiring board. It is a longitudinal cross-sectional view which shows the conventional inflow prevention method of a printed wiring board.

Explanation of symbols

1, 2, 3, 4, 5, 6, 7, 8 ... sub-assembly wiring board,
9 ... multilayer wiring board,
10, 11, 12, 13, 16, 17, 18, 19 ... vias,
20, 21, 22, 23 ... prepreg,
30 ... pin,
40 ... via,
50: Via filling resin or the like.

Claims (3)

  A method of manufacturing a multilayer printed wiring board including a step of laminating sub-assembly wiring boards in which vias have been formed in advance via a prepreg, and in the step of laminating the sub-assembly wiring boards, opposing sub-assemblies Inserting a part of a pin into a via on one surface of the wiring board and aligning a via of another subassembly wiring board opposite to the via of the subassembly wiring board into which the pin is inserted; and the pin A method of manufacturing a multilayer printed wiring board, comprising: inserting the remaining portion into a via of another subassembly wiring board facing each other and laminating.   2. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the pins are formed of a conductor.   The multilayer printed wiring board manufactured by the manufacturing method of the multilayer printed wiring board of Claim 1 or 2.

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