JP2006267661A - Memory control device and image signal processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the phenomenon that image information write to a memory and image information read from the memory pass each other hardly occur. <P>SOLUTION: An input signal processing part includes a dual port memory 21, an effective area determination part 22, a passing determination part 23, and a frame memory control part 24. Input image data is read out synchronously with a signal SCLK asynchronous with an inputted synchronizing signal (ICLK) by the dual port memory 21. The effective area determination part 22 detects an input period of image data to be displayed on a display part 9 and outputs a detection result as input effective information and input line information. The passing determination part 23 determines whether passing will occur with respect to image data read from an input frame memory or not in accordance with signals ICLK and SCLK, scaling factor information, and input determination threshold information and in consideration of a scaling factor. The frame memory control part 24 controls the input frame memory on the basis of signals SCLK and REQ, input effective information, input line information, and a passing determination result. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory control device and an image signal processing device.

Japanese Patent Laid-Open No. 2001-13934 (Patent Document 1) adds a read address amount that progresses during one writing frame to a reading address value at the start of a writing frame, and adds the added value and one writing frame. It describes a means for comparing the address amount to determine the presence or absence of overtaking, and prohibiting writing to the storage device when it is determined that there is overtaking. In addition, there is described a means for performing an address overtaking determination of a storage device from a difference between a read address and a write address and a preset allowable value of an address difference value, and executing or stopping the storage device.
In Japanese Patent Laid-Open No. 2001-83928 (Patent Document 2), a time difference between a reset time of a write address and a reset time of a read address is detected, and the memory of the next write frame is detected based on the detected time difference. It describes a means for determining whether or not overtaking occurs, and canceling writing to the frame memory in the next writing frame if it is determined that it will occur. Also, the time difference between the reset time of the write address and the reset time of the read address is detected, and based on the detected time difference, it is determined whether or not a memory overtaking occurs in the next read frame, and it is determined that it occurs. In this case, a means for reading data for one frame from the same memory area read immediately before in the next read frame is described. Also, the time difference between the reset time of the write address and the reset time of the read address is detected, and based on the detected time difference, it is determined whether or not a memory overtaking occurs in the next read frame, and it is determined that it occurs. In this case, a means for reading data from a memory area that is one order ahead of the memory area in the order in which data is to be read in the next read frame is described.
JP 2001-13934 A JP 2001-83928 A

  An object of the present invention is to provide a novel configuration capable of suitably suppressing overtaking between writing and reading in a configuration for writing and reading information to and from a memory.

The present invention provides a memory control circuit for writing information to a memory in synchronization with a first synchronization signal, and reading information from the memory in synchronization with a second synchronization signal that is asynchronous with the first synchronization signal. A prediction circuit that predicts overtaking between writing and reading information to the memory based on information corresponding to a speed at which the information is read from the memory or information corresponding to a speed at which the information is written to the memory. The memory control circuit performs control for writing information to the memory or reading information from the memory, which is executed when the overtaking is predicted, and control when the overtaking is not predicted. It is a memory control device characterized by avoiding overtaking by making it different.

Further, the present application includes an invention of a memory control device in which the memory control circuit avoids overtaking by not writing information to the memory when the overtaking is predicted. In this configuration, control is performed to write information to the memory when overtaking is not predicted, whereas information is not written to the memory when overtaking is predicted. Control to prevent writing (both active control not to perform writing and passive control not to perform writing) Is equivalent to Specifically, when the overtaking is predicted, if the overtaking is not predicted, information should not be written to the memory during the period when information should be written to the memory, thereby avoiding overtaking. can do. Further, the memory has a plurality of memory units, and the memory control circuit sequentially writes information to the plurality of memory units, and the overtaking in a predetermined memory unit is predicted. In this case, the present application includes an invention of a memory control device that avoids overtaking by reading information from a memory unit in which overtaking does not occur. In this configuration, when the overtaking is not predicted, control is performed to read information from the predetermined memory unit, whereas when overtaking is predicted, a memory other than the predetermined memory unit is controlled. Control for reading information from the unit is performed. Specifically, when overtaking in a predetermined memory unit is predicted, if the overtaking is not predicted, information from the predetermined memory unit should be read out from the predetermined memory unit. Overtaking can be avoided by reading information from a memory unit other than the predetermined memory unit without reading the information. Note that when the present invention is applied to a configuration for storing image signals, each memory unit only needs to be able to store image signals for forming one screen. As the image signal, a luminance signal or a color signal used for forming an image can be adopted. The present application also includes an invention of the memory control device and an image signal processing device having the memory controlled by the memory control device. Further, the present application includes an invention of an image display device including the image signal processing device and a display unit that performs display based on an image signal output from the image signal processing device.

  According to the present invention, it is possible to make it difficult to overtake the writing and reading of information to the memory.

Embodiments of the present invention will be described below.
A preferred example of an image signal processing apparatus including a memory control apparatus will be specifically described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of an image signal processing apparatus including a memory control apparatus of the present invention. In FIG. 1, reference numeral 1 denotes an input frame memory capable of storing input image data over one frame or more, and is configured using a semiconductor memory such as a DRAM (Dynamic Random Access Memory). Reference numeral 3 denotes an output frame memory configured using a semiconductor memory in the same manner as the input frame memory 1 and capable of storing displayed image data over one frame or more. An image processing unit 5 converts input image data into image data to be displayed. The image processing unit 5 converts luminance information and color information included in the input image data into different values, or scaling set by the CPU 8. In accordance with the rate information, resolution conversion processing is performed such that the input image data is enlarged or reduced to image data having another resolution. As a resolution conversion processing method performed by the image processing unit 5, a general method such as a linear interpolation method or a cubic convolution interpolation method is used. Reference numeral 9 denotes a display unit that displays image data processed by the image processing unit 5, and is configured using a cathode ray tube, a liquid crystal panel, a PDP (Plasma Display Panel), or the like. 7 is an output that generates an output vertical synchronization signal (OVS), an output horizontal synchronization signal (OHS), and an output clock signal (OCLK) for displaying on the display unit 9 in accordance with output timing information set by the CPU 8. It is a synchronization signal generator. 6 is an internal for controlling the image processing unit 5, the input frame memory 1, and the output frame memory 3, which are different from the synchronization signal of the input image data and the synchronization signal generated by the output synchronization signal generation unit 7. An internal synchronization signal generator for generating a vertical synchronization signal (SVS), an internal horizontal synchronization signal (SHS), and an internal clock signal (SCLK). 2, by using the input frame memory 1, the input image data is synchronized with the internal synchronization signal generated by the internal synchronization signal generation unit 6 and the data request signal (REQ) output from the image processing unit 5. And an input signal processing unit that serves as a memory control device for the input frame memory 1.

  FIG. 2 shows a configuration example of the input signal processing unit 2. In FIG. 2, reference numeral 21 denotes a dual port memory capable of inputting and outputting data at asynchronous timings. The image data input thereby is synchronized with the input synchronization signal. Data can be read out in synchronization with the internal synchronization signal generated by the signal generator 6. 22 detects a period during which image data to be displayed on the display unit 9 is input according to the synchronization signal input together with the image data and the input effective area information set by the CPU 8, and the input effective information and the input line It is an effective area determination unit that outputs information. Reference numeral 23 denotes an image read from the input frame memory 1 in accordance with the input synchronization signal, the internal synchronization signal generated by the internal synchronization signal generation unit 6, and the scaling rate information and the input determination threshold information set by the CPU 8. An overtaking determination unit that determines whether overtaking occurs in data.

  FIG. 3 shows a configuration example of the overtaking determination unit 23. 231 is an occurrence of overtaking when starting to write image data for one frame to the input frame memory 1 according to the start line information and line range information included in the scaling rate information and the input determination threshold information set by the CPU 8 This is an overtaking range determination unit that outputs read line information from the input frame memory 1 to be output. Reference numeral 232 denotes a horizontal synchronizing signal count unit that counts and outputs the number of times the SHS signal is generated. The count value in the horizontal synchronizing signal count unit 232 is initialized to “0” by the SVS signal. Reference numeral 233 denotes a count value storage unit that holds and outputs the value counted by the horizontal synchronization signal count unit 232 at the timing of the IVS signal. Reference numeral 234 denotes an adder that adds and outputs the value output from the count value storage unit 233 and the offset information included in the input determination threshold information set by the CPU 8. 235 compares the overtaking determination range information output from the overtaking range determination unit 231 with the value output from the count value storage unit 233, and the value output from the count value storage unit 233 is compared with the overtaking range determination unit 231. If it is included in the output value range, it is determined that overtaking occurs in the image data read from the input frame memory 1, and “1” is output. Otherwise, “0” is output. It is the comparison part (1) to do. 236 compares the overtaking range determination information output from the overtaking range determination unit 231 with the value output from the adder 234, and the value output from the adder 234 is a value output from the overtaking range determination unit 231. Is included in the range, the image data read from the input frame memory 1 is judged to be overtaken, and “1” is output. Otherwise, the comparison unit (“0”) is output ( 2). Reference numeral 237 denotes an OR element that calculates and outputs the logical sum of the output from the comparison unit (1) 235 and the output from the comparison unit (2) 236, and whichever of the comparison unit (1) 235 and the comparison unit (2) 236 Thus, when it is determined that overtaking occurs in the image data read from the input frame memory 1, “1” is output, and “0” is output otherwise. According to this example, it is determined whether or not overtaking occurs in the image data read from the input frame memory 1 at the time when writing of one frame of image data into the input frame memory 1 is started. When the input frame memory 1 has a storage area for at least one frame and the overtaking determination unit 23 determines that overtaking occurs, the writing of the input image data to the input frame memory 1 is stopped. To avoid overtaking. This example is described in detail in the first embodiment.

FIG. 4 shows another configuration example of the overtaking determination unit 23. In this example, the IHS signal and the IVS signal are input to the horizontal synchronizing signal count unit 232, and the number of occurrences of the IHS signal is counted and output. The count value in the horizontal synchronization signal count unit 232 is “0” by the IVS signal.
It is initialized to. The count value storage unit 233 receives the SVS signal, and holds the value counted by the horizontal synchronization signal count unit 232 at the timing of the SVS signal. Other configurations are the same as those shown in FIG. According to this example, it is determined whether or not overtaking occurs in the image data read from the input frame memory 1 at the time when reading of the image data for one frame from the input frame memory 1 is started. When the input frame memory 1 has a storage area for a plurality of frames and the overtaking determination unit 23 determines that overtaking occurs, the occurrence of overtaking can be avoided by adjusting the frame read from the input frame memory 1. Yes. This example is described in detail in the second embodiment.

  Returning to FIG. 2, reference numeral 24 denotes an internal synchronization signal generated by the internal synchronization signal generation unit 6, a data request signal (REQ) output from the image processing unit 5, and an input valid output output from the valid area determination unit 22. This is a frame memory control unit that controls the input frame memory 1 based on the information, the input line information, and the overtaking determination result output from the overtaking determination unit 23.

  Returning to FIG. 1, the output 4 outputs the image data processed by the image processing unit 5 in synchronization with the output synchronization signal generated by the output synchronization signal generation unit 7 by using the output frame memory 3. It is a signal processing unit and serves as a memory control device for the output frame memory 3.

  FIG. 5 shows a configuration example of the output signal processing unit 4. Reference numeral 41 denotes a dual-port memory that can input and output data at asynchronous timings. As a result, the image data processed by the image processing unit 5 is output as an output synchronization signal that is asynchronous with the internal synchronization signal. It is possible to read in synchronization with the output synchronization signal generated by the generation unit 7. Reference numeral 42 denotes an effective area determination unit that detects timing for display on the display unit 9 according to the output synchronization signal generated by the output synchronization signal generation unit 7 and the display area information set by the CPU 8. 43 is output in accordance with the internal synchronization signal generated by the internal synchronization signal generation unit 6, the output synchronization signal generated by the output synchronization signal generation unit 7, and the scaling rate information and the output determination threshold information set by the CPU 8. This is an overtaking determination unit that determines whether or not overtaking occurs in image data read from the frame memory 3.

FIG. 6 shows a configuration example of the overtaking determination unit 43. 431 is the occurrence of overtaking when starting to write image data for one frame to the output frame memory 3 in accordance with the start line information and line range information included in the scaling rate information and output determination threshold information set by the CPU 8 This is an overtaking range determination unit that outputs read line information from the output frame memory 3. Reference numeral 432 denotes a horizontal synchronizing signal count unit that counts and outputs the number of occurrences of the OHS signal. The count value in the horizontal synchronization signal count unit 432 is initialized to “0” by the OVS signal. Reference numeral 433 denotes a count value storage unit that holds and outputs the value counted by the horizontal synchronization signal count unit 432 at the timing of the SVS signal. Reference numeral 434 denotes an adder that adds and outputs the value output from the count value storage unit 433 and the offset information included in the output determination threshold information set by the CPU 8. 435 compares the value output from the overtaking range determination unit 431 and the value output from the count value storage unit 433, and the value output from the count value storage unit 433 is output from the overtaking range determination unit 431. If it is included in the value range, it is determined that overtaking occurs in the image data read from the output frame memory 3, and “1” is output, otherwise “0” is output. (1). A value 436 compares the value output from the overtaking range determination unit 431 with the value output from the adder 434, and the value output from the adder 434 falls within the range of values output from the overtaking range determination unit 431. If included, the comparison unit (2) that outputs “1” by judging that overtaking occurs in the image data read from the output frame memory 3 and outputs “0” otherwise. is there. 437 is the output from the comparison unit (1) 435 and the comparison unit (2) 4
36 is an OR element that obtains and outputs the logical sum of the outputs from 36, and in either of the comparison unit (1) 435 and the comparison unit (2) 436, the image data read from the output frame memory 3 is overtaken. If it is determined that it occurs, “1” is output, otherwise “0” is output. According to this example, it is determined whether or not overtaking occurs in the image data read from the input frame memory 1 at the time when writing of image data for one frame to the output frame memory 1 is started. When the output frame memory 3 has a storage area for at least one frame and the overtaking determination unit 43 determines that overtaking occurs, the writing of the input image data to the output frame memory 3 is stopped. To avoid overtaking. This example is described in detail in Example 1.

  FIG. 7 shows another configuration example of the overtaking determination unit 43. In this example, the SHS signal and the SVS signal are input to the horizontal synchronization signal count unit 432, and the number of occurrences of the SHS signal is counted and output. The count value in the horizontal synchronization signal count unit 432 is initialized to “0” by the SVS signal. The count value storage unit 433 receives the OVS signal, and holds the value counted by the horizontal synchronization signal count unit 432 at the timing of the OVS signal. Other configurations are the same as those shown in FIG. According to this example, it is determined whether or not overtaking occurs in the image data read from the output frame memory 3 at the time when reading of image data for one frame from the output frame memory 3 is started. When the output frame memory 3 has a storage area for a plurality of frames and the overtaking determination unit 43 determines that overtaking occurs, the frame read from the output frame memory 3 is adjusted to avoid overtaking. Yes. In addition, about this example, the specific example 2 is explained in full detail.

Returning to FIG. 5, reference numeral 44 denotes an internal synchronization signal generated by the internal synchronization signal generation unit 6, a post-processing data effective signal (ENB) output from the image processing unit 5, and an effective region determination unit 42. The frame memory control unit controls the output frame memory 3 based on the output valid information, the output line information, and the overtaking determination result output from the overtaking determination unit 43.
Returning to FIG. 1 again, reference numeral 8 denotes a CPU (Central Processing Unit) for controlling the entire image signal processing apparatus shown in FIG.

Hereinafter, the present invention will be described in detail with specific examples.
Example 1
In this embodiment, in the configuration example of the image signal processing apparatus shown in FIG. 1, it is assumed that the input frame memory 1 or the output frame memory 3 can store image data for at least one frame. This is an example of avoiding overtaking by stopping writing of image data to the frame memory when predicted.

  In FIG. 1, an image processing unit 5 has a resolution conversion processing function for outputting input image data after enlarging or reducing at a specified magnification, and the image processing unit 5 performs equal magnification processing, enlargement processing, and reduction. Each timing at the time of processing will be described below with reference to FIGS.

FIG. 8 shows the timing when the image processing unit 5 performs the same magnification processing. FIG. 8A shows a state in which image data to be displayed on the display unit 9 is input. In this example, the IVS signal and the IHS signal are expressed as negative logic signals. Image data to be displayed on the display unit 9 is output line by line in synchronization with the output of the IHS signal after the IVSTART period has elapsed after the IVS signal is output, and is output after the IHSTART period has elapsed from the IHS signal. . The information of IVSTART and IHSTART is set as effective input area information from the CPU 8 to the effective area determination unit 22 in the input signal processing unit 2, and the effective area determination unit 22 displays the input image data on the display unit 9. If it is determined that the input image data is read from the dual port memory 21, the input valid information and the input line information are output to the frame memory control unit 24. The frame memory control unit 24 writes the image data read from the dual port memory 21 in the input frame memory 1 according to the input line information by detecting that the input valid information is output from the valid region determination unit 22. FIG. 8B shows a state in which the image data written in the input frame memory 1 is read out and is subjected to equal magnification processing in the image processing unit 5. In this example, the SVS signal and the SHS signal are expressed as negative logic signals, and the REQ signal, the ACT signal, and the ENB signal are expressed as positive logic signals. The image processing unit 5 outputs the REQ signal to the input signal processing unit 2 in synchronization with the output of the SHS signal after the SVSTART period has elapsed after the output of the SVS signal, and requests the output of the image data. The input signal processing unit 2 reads the image data from the input frame memory 1 by detecting that the REQ signal is output from the image processing unit 5, and outputs it together with the ACT signal after the SHSTART period has elapsed after the SHS signal is output. To do. Information on SVSTART and SHSTART is set in the image processing unit 5 as internal processing area information from the CPU 8. The image processing unit 5 performs equal-magnification processing on the image data output from the input signal processing unit 2 together with the ACT signal, and outputs it to the output signal processing unit 4 together with the ENB signal. The output signal processing unit 4 writes the image data output together with the ENB signal into the output frame memory 3 by detecting that the ENB signal is output from the image processing unit 5. FIG. 8C shows a state in which display data read from the output frame memory 3 is output to the display unit 9. In this example, the OVS signal and the OHS signal are expressed as negative logic signals. Display data to be displayed on the display unit 9 is output in line units in synchronization with the output of the OHS signal after the OVSTART period has elapsed after the OVS signal has been output, and is output after the OHSTART period has elapsed from the OHS signal. . The OVSTART and OHSTART information is set as display area information from the CPU 8 in the effective area determination section 42 and the dual port memory 41 in the output signal processing section 4, and the effective area determination section 42 receives the OVS signal and the OVS signal from the OVSTART The timing of outputting image data to be displayed on the display unit 9 is determined by measuring the progress, and is output to the frame memory control unit 44 as output valid information and output line information. The frame memory control unit 44 reads the display data from the output frame memory 3 according to the output line information and writes it to the dual port memory 41 by detecting that the output valid information is output from the valid area determination unit 42. The dual port memory 41 reads the display data written after the OHSTART period set as display area information from the CPU 8 and outputs it to the display unit 9.

  FIG. 9 shows the timing when the image processing unit 5 performs enlargement processing three times. When the image processing unit 5 enlarges the input image data by three times and outputs it, the output data for three lines is generated and output from the input image data for one line, so the REQ signal is the SHS signal. Is issued to the input signal processing unit 2 at a rate of once every time is issued three times.

  FIG. 10 shows the timing when the image processing unit 5 performs the reduction process to 1/3 times. When the input image data is reduced by 1/3 in the image processing unit 5 and output, the output data for one line is generated and output from the input image data for three lines. Every time the SHS signal is issued three times, it is output to the output signal processing unit 4 at a rate of once.

  As described above, the image processing unit 5, the input signal processing unit 2, and the output signal processing unit 4 perform input / output of image data while taking a handshake, so that the image processing unit 5 does not have a frame memory and does not have a frame memory. Resolution conversion processing can be performed at the timing.

The input signal processing unit 2 shown in FIG. 1 outputs the input image data to the image processing unit 5 at the timing explained above by using the input frame memory 1, and the output signal processing unit 4 explained above. The image data output from the image processing unit 5 at the timing is output to the display unit 9 by using the output frame memory 3.

  In the input signal processing unit 2, the input image data is stored in the dual port memory 21 in synchronization with the clock signal (ICLK) input at the same time, and the internal clock signal ( SCLK). As a result, the input image data is synchronized with the SCLK signal. At the same time, the effective area determination unit 22 determines whether the image data input from the input synchronization signal is image data to be displayed on the display unit 9, and image data to be displayed is input. To the frame memory control unit 24 as input valid information and input line information. The frame memory control unit 24 writes the image data read from the dual port memory 21 to the input frame memory 1 in accordance with the input valid information and the input line information output from the valid area determination unit 22. The image data written to the input frame memory 1 is read according to the data request signal (REQ) output from the image processing unit 5 and output to the image processing unit 5. As a result, the input image data is synchronized with the internal synchronization signal. Here, since the synchronization signal input together with the image data and the synchronization signal generated by the internal synchronization signal generation unit 6 are asynchronous, a phenomenon of overtaking occurs in the image data read from the input frame memory 1.

  FIG. 11 is a diagram illustrating how overtaking occurs. In FIG. 11, the frame rate of the input image is Fiv [Hz], the frame rate of the output image is Fov [Hz], and a state when Fiv> Fov is shown. (1) → (2) → (3) → (4) → (5) (The figure is shown in circled numbers in the figure. In the case of updating in units of frames as shown in the figure below, this image is displayed in the frame memory in the period of W0 → W1 → W2 → W3 → W4 in synchronization with the input frame rate Fiv [Hz]. Is written to. The transition of the write address at this time can be expressed as a repetitive waveform such as a sawtooth wave represented by a solid line in FIG. On the other hand, reading from the frame memory is performed in the period of R0 → R1 → R2 from the frame memory in synchronization with the output frame rate Fov [Hz]. The transition of the read address at this time can be expressed as a repetitive waveform such as a sawtooth wave represented by a dotted line in FIG. In this case, the overtaking occurs at the point where the write address and the read address intersect (shown as the overtaking point in the figure), and the output image is overtaken by the update of the input during the reading of one frame, and different frames ( The image is composed of the old frame (2) on the upper side and the new frame (3) on the lower side. To prevent this, as shown in FIG. 11- (B), the frame (3) of the output image is thinned out by stopping the writing of the input image to the frame memory during the overtaking period (W2). Although the frame is lost, the overtaking that the displayed image is divided up and down is avoided.

  Next, how the timing of occurrence of overtaking changes according to the scaling rate will be described with reference to FIGS.

  FIG. 12 shows that the input image data is image data having information of 480 lines, and the internal synchronization signal generation unit 6 generates a synchronization signal at a timing capable of processing 1080 lines, and overtaking occurs at that time. FIG. 12- (A) shows the state when the input image data is subjected to the same-size processing or reduction processing in the image processing unit 5, and FIG. 12- (B) shows the input image. The situation when the data is enlarged three times by the image processing unit 5 is shown.

When the image processing unit 5 performs equal magnification processing or reduction processing, the REQ signal is continuously output from the image processing unit 5 to the input signal processing unit 2 as shown in FIGS. Accordingly, as shown in FIG. 12- (A), 480 lines of image data are input and written into the input frame memory 1 (thin solid line) in the cycle of the IVS signal, and the cycle of the SVS signal is input. The image data for 480 lines input during the period from 1 line to 480 lines of the generated 1080 SHS signals is read (thick solid line). Here, at the time point T1 when the count value (dotted line) of the SHS signal output from the internal synchronization signal generation unit 6 when starting to write the input image data of a new frame becomes M1, the input frame of the input image data as it is When writing to the memory 1 is performed, the write address and the read address intersect to cause overtaking. In such a case, overtaking occurs until the count value of the SHS signal reaches “1080”, that is, output from the internal synchronization signal generation unit 6 when writing of input image data of a new frame is started. Overtaking occurs when the count value of the SHS signal is between M1 and “1080”.

  Next, when the image processing unit 5 performs enlargement processing three times, the REQ signal from the image processing unit 5 to the input signal processing unit 2 at a rate of once every three SHS signals as shown in FIG. Are output. That is, as shown in FIG. 12- (B), the REQ signal for 360 lines is output from the image processing unit 5 with respect to 1080 SHS signals generated by the internal synchronization signal generating unit 6, and the image processing unit 5 Then, image data for 1080 lines is generated and output from image data for 360 lines output from the input signal processing unit 2 in synchronization with the REQ signal. Here, at the time T2 when the count value (broken line) of the SHS signal output from the internal synchronization signal generation unit 6 when starting to write the input image data of a new frame becomes M2, the input frame of the input image data as it is. When writing to the memory 1 is performed, overtaking occurs. In such a case, overtaking occurs until the count value of the SHS signal becomes “0”, that is, output from the internal synchronization signal generation unit 6 when writing of input image data of a new frame is started. Overtaking occurs when the count value of the SHS signal is between “0” and M2.

  As described above, the timing at which overtaking occurs varies depending on the scaling rate. FIG. 13 shows how the timing of overtaking changes according to the scaling rate. When the image processing unit 5 performs equal magnification processing or reduction processing, the count value of the SHS signal output from the internal synchronization signal generation unit 6 at the time when writing of input image data of a new frame is started is changed from M1 to “ Overtaking occurs during the period up to 1080 ″. At this time, the count value of the SHS signal (dotted line in FIG. 12) and the line number read from the input frame memory 1 (thick solid line in FIG. 12) match as shown in FIG. 12- (A). . Next, when enlargement processing is performed by the image processing unit 5, the line number read from the input frame memory 1 is smaller than the count value of the SHS signal in accordance with the enlargement ratio, as shown in FIG. Further, the slope of the line number read from the input frame memory 1 becomes gentler than the slope for counting the SHS signal. Until the slope of the line number read from the input frame memory 1 (thick solid line in FIG. 12) matches the slope of the line number written to the input frame memory 1 (thin solid line in FIG. 12), the upper limit is “1080”. As the enlargement rate increases, the range where overtaking occurs becomes narrower, the enlargement rate further increases, and the slope of the line number read from the input frame memory 1 is gentler than the slope of the line number written to the input frame memory 1. In this case, the range where the overtaking occurs starts with “0” as the starting point.

  In this way, the timing at which overtaking occurs changes according to the scaling rate, so the overtaking determination unit 23 must perform overtaking prediction in consideration of the scaling rate set in the image processing unit 5.

  With reference to FIG. 3, how the overtaking determination unit 23 predicts overtaking will be described. The horizontal synchronization signal counting unit 232 counts the number of occurrences of the SHS signal output from the internal synchronization signal generation unit 6. The count value is initialized to “0” by the SVS signal. The number of occurrences of the SHS signal counted by the horizontal synchronization signal count unit 232 is stored at the timing at which the IVS signal is generated by the count value storage unit 233, and the value stored by the count value storage unit 233 is the comparison unit ( 1) 235, the comparison unit (2) 236, and the adder 234. The comparison unit (1) 235 and the comparison unit (2) 236 detect an overtaking generation range with “1080” as an upper limit, and detect an overtaking generation range with “0” as a starting point. . When the adder 234 detects the overtaking occurrence range starting from “0” in the comparison unit (2) 236, the adder 234 maintains a connection with the detection of the overtaking occurrence range with “1080” as the upper limit. The value “1080” is added to the value output from the count value storage unit 233 so that the starting point “0” is regarded as “1080”, and is output from the count value storage unit 233. The value added to the value is set by the CPU 8 as offset information included in the input determination threshold information. The CPU 8 further sets start line information (S1) and line range information (L1) as overtaking range information at the time of reduction or equal magnification to the overtaking range determining unit 231 as input determination threshold information, and the overtaking range determining unit 231 The overtaking occurrence range is determined according to the scaling rate information set by the CPU 8. FIG. 14 shows how the overtaking range determination unit 231 determines the overtaking occurrence range according to the scaling rate information. First, the range in which overtaking occurs at the time of reduction or equal magnification is set as start line information (S1) and line range information (L1) including lines from M1 to “1080” from the CPU8. Further, when the scaling rate information is set to enlargement processing by the CPU 8, start line information and line range information corresponding to the scaling rate information are obtained. When expanding twice, the range of L1 with S2 as the start line is output as a range where overtaking occurs, and when expanding three times, the range of L1 with S3 as the starting line is output as a range where overtaking occurs To do. In the case of enlarging to 4 times, if the range of L1 having S4 as the start line is set as the range in which overtaking occurs, the lower limit value is larger than “1080”, so here the lower limit value is expanded to 3 times. The range of L2, which is the same as S3, is output as a range where overtaking occurs.

  In this manner, the overtaking determination range information output from the overtaking range determination unit 231 changes according to the scaling rate information set by the CPU 8. The comparison unit (1) 235 determines whether or not the value output from the count value storage unit 233 is within the range of the overtaking determination range information output from the overtaking range determination unit 231. ) 236, it is determined whether or not the value output from the adder 234 is within the range of the overtaking determination range information output from the overtaking range determining unit 231, and any value is determined as the overtaking range determining unit 231. In the case of being within the range of the overtaking determination range information output from the OR element 237, the overtaking detection information is output.

  When the frame memory control unit 24 detects that the overtaking detection information is output from the overtaking determination unit 23, as shown in FIG. 11- (B), the frame memory control unit 24 inputs the image data input in the frame to the input frame memory 1. Stop writing. As a result, it is possible to avoid overtaking in the image data read from the input frame memory 1.

  Returning to FIG. 1, the image data read from the input frame memory 1 is subjected to resolution conversion processing in accordance with the scaling rate information set by the CPU 8 in the image processing unit 5, and the processed image data is ENB. The signal is output to the output signal processing unit 4 together with the signal. In the output signal processing unit 4, image data output together with the ENB signal from the image processing unit 5 is written to the output frame memory 3, and the output frame memory 3 synchronizes with the synchronization signal generated by the output synchronization signal generation unit 7. The image data is read out and output to the display unit 9.

  The output signal processing unit 4 writes the image data output together with the ENB signal from the image processing unit 5 to the output frame memory 3 via the frame memory control unit 44, and outputs the output valid information and the output from the valid area determination unit 42. In accordance with the line information, the image data written to the output frame memory 3 is read and stored in the dual port memory 41. The image data stored in the dual port memory 41 is read out from the OHS signal in synchronization with the output clock signal (OCLK) generated by the output synchronization signal generation unit 7 after the OHSTART period has elapsed, whereby the output frame is output. The image data read from the memory 3 is synchronized with the output synchronization signal. The effective area determination unit 42 determines the timing for reading out the image data to be displayed on the display unit 9 from the output synchronization signal from the output frame memory 3 based on the output synchronization signal, and provides it to the frame memory control unit 44 as output effective information and output line information.

  Here, since the synchronization signal generated by the internal synchronization signal generation unit 6 and the synchronization signal generated by the output synchronization signal generation unit 7 are asynchronous, the image data read from the output frame memory 3 is also overtaken. appear.

  The manner in which overtaking occurs in the image data read from the output frame memory 3 and the timing at which overtaking occurs changes according to the scaling rate will be described with reference to FIGS.

  In FIG. 15, it is assumed that the internal synchronization signal generation unit 6 generates a synchronization signal at a timing capable of processing 1080 lines, and the output synchronization signal generation unit 7 generates a synchronization signal to the display unit 9 having 720 lines. FIG. 15- (A) shows a state where the input image data is subjected to the same-size processing or enlargement processing in the image processing unit 5, and FIG. 15- (B). Shows a state where the input image data is reduced by 2/3 times in the image processing unit 5.

  When the image processing unit 5 performs equal magnification processing or enlargement processing, the ENB signal is continuously output from the image processing unit 5 to the output signal processing unit 4 as shown in FIGS. . Accordingly, as shown in FIG. 15- (A), the image data output from the image processing unit 5 is output 720 during the period from the 1st line to the 720th line of the SHS signal for 1080 lines generated in the cycle of the SVS signal. Image data for lines is written in the output frame memory 3 (thick solid line), and image data for 720 lines is read out in the cycle of the OVS signal (thin solid line). Here, at the time T1 when the line number read from the output frame memory 3 becomes M1 when writing of the image data of a new frame output from the image processing unit 5 is started, the image data is output to the output frame memory 3 as it is. When writing is performed, the write address and the read address intersect to cause overtaking. In such a case, overtaking occurs until the line number read from the output frame memory 3 becomes “0”, that is, when writing of image data of a new frame output from the image processing unit 5 is started. In the meantime, overtaking occurs when the line number read from the output frame memory 3 is between "0" and M1.

Next, when the image processing unit 5 performs the reduction process to 2/3 times, the ENB signal is output from the image processing unit 5 to the output signal processing unit 4 at a rate of two times for three SHS signals. . That is, as shown in FIG. 15- (B), an ENB signal for 720 lines is output from the image processing unit 5 with respect to 1080 SHS signals generated by the internal synchronization signal generating unit 6, and the image processing unit 5 Then, 720 lines of image data are generated from the 1080 lines of image data output from the input signal processing unit 2 in synchronization with the REQ signal and output. Here, at the time T2 when the line number read from the output frame memory 3 becomes M2 when starting to write the image data of a new frame output from the image processing unit 5, the image data is directly output to the output frame memory 3. If this is written, overtaking will occur. In such a case, from the output frame memory 3 until the line number read from the output frame memory 3 becomes “0”, that is, when writing of image data of a new frame output from the image processing unit 5 is started. Overtaking occurs when the line number to be read is between “0” and M2.

  FIG. 16 shows how the timing of overtaking changes according to the scaling rate. When the image processing unit 5 performs equal magnification processing or enlargement processing, the line number read from the output frame memory 3 at the time when writing of image data of a new frame output from the image processing unit 5 is started is “0”. Overtaking occurs between “1” and M1. At this time, the count value of the SHS signal (dotted line in FIG. 15) and the line number written to the output frame memory 3 (thick solid line in FIG. 15) match as shown in FIG. 15- (A). . Next, when the image processing unit 5 performs the reduction process, the line number written to the output frame memory 3 becomes smaller than the count value of the SHS signal according to the reduction ratio, as shown in FIG. 15- (B). In addition, the slope of the line number written to the output frame memory 3 is gentler than the slope of counting the SHS signal. Until the slope of the line number written to the output frame memory 3 (thick solid line in FIG. 15) matches the slope of the line number read from the output frame memory 3 (thin solid line in FIG. 15), the starting point is “0”. As the reduction ratio increases, the range in which overtaking occurs decreases, and the reduction ratio further increases, and the slope of the line number written to the output frame memory 3 is greater than the slope of the line number read from the output frame memory 3. When it becomes moderate, the range in which overtaking occurs with “720” as the upper limit is expanded.

  As described above, since the timing at which overtaking occurs changes according to the scaling rate, the overtaking determination unit 43 must perform overtaking prediction in consideration of the scaling rate set in the image processing unit 5.

With reference to FIG. 6, how the overtaking determination unit 43 predicts overtaking will be described. The horizontal synchronization signal count unit 432 counts the number of occurrences of the OHS signal output from the output synchronization signal generation unit 7. The count value is initialized to “0” by the OVS signal. The number of occurrences of the OHS signal counted by the horizontal synchronization signal counting unit 432 is stored at the timing at which the SVS signal is generated by the count value storage unit 433, and the value stored in the count value storage unit 433 is stored in the comparison unit ( 1) 435, the comparison unit (2) 436, and the adder 434. The comparison unit (1) 435 and the comparison unit (2) 436 detect an overtaking occurrence range with “720” as an upper limit, and detect an overtaking occurrence range with “0” as a starting point. . When the adder 434 detects the overtaking occurrence range starting from “0” in the comparison unit (2) 436, the adder 434 maintains a connection with the detection of the overtaking occurrence range with “720” as the upper limit. The value “720” is added to the value output from the count value storage unit 433 in order to process the starting point “0” as “720”, and is output from the count value storage unit 433. The value added to the value is set as offset information included in the output determination threshold information by the CPU 8. The CPU 8 further sets start line information (S1) and line range information (L1) as overtaking range information at the time of enlargement or equal magnification to the overtaking range determination unit 431 as output determination threshold information, and the overtaking range determination unit 431 The overtaking occurrence range is determined according to the scaling rate information set by the CPU 8. FIG. 17 shows how the overtaking range determination unit 431 determines the overtaking generation range according to the scaling rate information. First, the range in which overtaking occurs during enlargement or equal magnification is set as start line information (S1) and line range information (L1) including lines from “0” to M1 from the CPU 8. Further, when the scaling rate information is set to the reduction process by the CPU 8, start line information and line range information corresponding to the scaling rate information are obtained. In the case of reduction to ½ times, the range of L1 with S2 as the start line is output as a range where overtaking occurs. In case of reduction to 1/3 times, L with S3 as the start line
If the range of 1 is set as the range where overtaking occurs, the upper limit value will interrupt “720”. Therefore, here, the range of L2 where the upper limit value is LMAX larger than “720” is set as the range where overtaking occurs. Output. Similarly, in the case of reduction to 1/4, the upper limit value is set to LMAX, and the range of L3 with S4 as the start line is output as the range in which overtaking occurs.

  In this manner, the overtaking determination range information output from the overtaking range determination unit 431 changes according to the scaling rate information set by the CPU 8. The comparison unit (1) 435 determines whether or not the value output from the count value storage unit 433 is within the range of the overtaking determination range information output from the overtaking range determination unit 431, and the comparison unit (2 ) 436, it is determined whether or not the value output from the adder 434 is within the range of the overtaking determination range information output from the overtaking range determination unit 431, and any of the values is overtaking range determination unit 431. In the case of being within the range of the overtaking determination range information output from the OR element 437, the overtaking detection information is output.

  When the frame memory control unit 44 detects that the overtaking detection information is output from the overtaking determination unit 43, as shown in FIG. 11- (B), the frame memory control unit 44 outputs the image data input in the frame to the output frame memory 3. Stop writing. As a result, it is possible to avoid overtaking in the image data read from the output frame memory 3.

  As the information corresponding to the reading speed from the memory, the scaling rate information described in the above embodiments can be preferably used. That is, when the scaling rate information is set as enlarged, the reading speed of the image data from the input frame memory 1 changes as shown in FIG. In addition to changing the reading speed according to the scaling rate information, when the processing of the image data processed by the image processing unit 5 requires a plurality of clock periods, the reading speed of the image data from the input frame memory 1 is set. It can also be used when changing. That is, single or plural pieces of information indicating some correspondence with the reading speed can be used as information corresponding to the reading speed. Also, the scaling rate information described in the above embodiments can be suitably used as the information corresponding to the writing speed in the memory. That is, when the scaling rate information is set as reduced, the writing speed of image data to the output frame memory 3 changes as shown in FIG. In addition to changing the writing speed according to the scaling rate information, when the processing of the image data processed by the image processing unit 5 requires a plurality of clock periods, the writing speed of the image data to the output frame memory 3 is set. It can also be used when changing. That is, single or plural pieces of information indicating some correspondence with the writing speed can be used as information corresponding to the writing speed.

(Example 2)
The present embodiment assumes that the input frame memory 1 or the output frame memory 3 can store image data for a plurality of frames in the configuration example of the image signal processing apparatus shown in FIG. This is an example of avoiding the occurrence of overtaking by selecting and reading out image data in a frame where no overtaking occurs.

In FIG. 18, it is assumed that the frame memory can store image data for two frames, and the overtaking that occurs in the period (W2) shown in FIG. This shows how it can be avoided. Images input in the order of W0.fwdarw.W1.fwdarw.W3.fwdarw.W4.fwdarw.W5 in synchronization with the input frame rate Fiv [Hz] are alternately written on the A and B planes of the frame memory. The transition of the write address at this time can be expressed as a repetitive waveform such as a sawtooth wave represented by a solid line in FIG. On the other hand, reading from the frame memory is alternately performed from the A and B planes in a period of R0 → R1 → R2 → R3 from the frame memory in synchronization with the output frame rate Fov [Hz]. The transition of the read address at this time can be expressed as a repetitive waveform such as a sawtooth wave represented by a dotted line in FIG. Here, there is a point where the write address and the read address intersect during the period R0. At this time, writing to the frame memory is performed on the A plane, and reading from the frame memory is performed on the B plane. Therefore, no overtaking occurs. Next, when images are read out from the B side of the frame memory in order during the period R2, the writing is also performed on the B side, so the point where the write address and the read address intersect (shown as the overtaking point in the figure). .)), Overtaking occurs, resulting in an image composed of different frames (upper frame is the old frame (2) and lower frame is the new frame (4)). Therefore, as shown in FIG. 18, overtaking is avoided by rereading the image read out during the period R2, not the B side of the frame memory, but the image on the A side that has been read out first. FIG. 18 shows how the overtaking is avoided in the case where the frame memory can store the image data for 2 frames. However, even in the case where the frame memory can store the image data for 3 frames or more, the overtaking is performed. Similarly, it is possible to avoid overtaking by reading out image data in a frame that does not occur.

  In this way, the frame memory can store image data for a plurality of frames, and the occurrence prediction of overtaking is avoided in the case where the overtaking is avoided by selecting and reading out the image data in the frame where no overtaking occurs. In the same manner as in the first embodiment, the overtaking determination unit 23 included in the input signal processing unit 2 or the overtaking determination unit 43 included in the output signal processing unit 4 performs the timing of detecting overtaking. This is different from Example 1.

  In this example, how the timing at which overtaking occurs according to the scaling rate will be described with reference to FIGS.

  FIG. 19 shows that input image data is image data having information of 480 lines, and the internal synchronization signal generation unit 6 generates a synchronization signal at a timing capable of processing 1080 lines, and overtaking occurs at that time. FIG. 19- (A) shows a state in which the input image data is subjected to the same-size processing or reduction processing in the image processing unit 5, and FIG. 19- (B) shows the input image. The situation when the data is enlarged three times by the image processing unit 5 is shown.

  When the image processing unit 5 performs equal magnification processing or reduction processing, the REQ signal is continuously output from the image processing unit 5 to the input signal processing unit 2 as shown in FIGS. Accordingly, as shown in FIG. 19- (A), 480 lines of image data are input and written in the input frame memory 1 (thin solid line) in the cycle of the IVS signal, and the cycle of the SVS signal is input. The image data for 480 lines input during the period from 1 line to 480 lines of the generated 1080 SHS signals is read (thick solid line). Here, when image data is read from the input frame memory 1 as it is at the time T1 when the line number of the image data input when reading the image data of a new frame from the input frame memory 1 is the M1 line, the write address And the read address intersect, and an overtaking occurs. In such a case, the overtaking occurs until the line number of the input image data becomes “0”, that is, the image data input when the image data of a new frame is read from the input frame memory 1. Overtaking occurs between the line numbers “0” and M1.

Next, when the image processing unit 5 performs the enlargement process three times, as shown in FIG. 9, the REQ signal is input from the image processing unit 5 at a rate of once every three SHS signals. Is output for. That is, as shown in FIG. 19- (B), the REQ signal for 360 lines is output from the image processing unit 5 with respect to 1080 SHS signals generated by the internal synchronization signal generating unit 6, and the image processing unit 5 Then, image data for 1080 lines is generated and output from image data for 360 lines output from the input signal processing unit 2 in synchronization with the REQ signal. Here, when the line number of the image data input when reading the image data of a new frame from the input frame memory 1 is the M2 line, if the image data is read from the input frame memory 1 as it is, the overtaking may occur. Will occur. In such a case, overtaking occurs until the line number of the input image data reaches “480”, that is, the image data input when reading out the image data of a new frame from the input frame memory 1. Overtaking occurs when the line number is between M2 and "480".

  That is, in this example as well as in the first embodiment, the timing at which the overtaking occurs changes according to the scaling rate. FIG. 20 shows how the timing at which overtaking occurs changes according to the scaling rate. When the image processing unit 5 performs the same magnification process or the reduction process, the line number of the input image data at the time of starting reading the image data of a new frame from the input frame memory 1 is from “0” to M1. Overtaking occurs during At this time, the count value of the SHS signal (dotted line in FIG. 19) and the line number read from the input frame memory 1 (thick solid line in FIG. 19) match as shown in FIG. 19- (A). . Next, when an enlargement process is performed by the image processing unit 5, the line number read from the input frame memory 1 becomes smaller than the count value of the SHS signal according to the enlargement ratio, as shown in FIG. 19- (B). Further, the slope of the line number read from the input frame memory 1 becomes gentler than the slope for counting the SHS signal. Until the slope of the line number read from the input frame memory 1 (thick solid line in FIG. 19) matches the slope of the line number written to the input frame memory 1 (thin solid line in FIG. 19), the starting point is “0”. As the enlargement ratio increases, the range where the overtaking occurs is narrowed, and the enlargement ratio further increases, and the slope of the line number read from the input frame memory 1 is greater than the slope of the line number written to the input frame memory 1. When it becomes moderate, the range in which overtaking occurs with “480” as the upper limit is expanded.

  As described above, also in this example, the timing at which overtaking occurs changes according to the scaling rate, and the overtaking determination unit 23 performs overtaking prediction in consideration of the scaling rate set in the image processing unit 5. There must be.

Next, with reference to a configuration example of the overtaking determination unit 23 illustrated in FIG. 4, how overtaking is predicted in this example will be described. The horizontal synchronization signal count unit 232 counts the number of occurrences of the IHS signal input together with the image data. The count value is initialized to “0” by the IVS signal. The number of occurrences of the IHS signal counted by the horizontal synchronization signal counting unit 232 is stored at the timing at which the SVS signal is generated by the count value storage unit 233, and the value stored by the count value storage unit 233 is the comparison unit ( 1) 235, the comparison unit (2) 236, and the adder 234. The comparison unit (1) 235 and the comparison unit (2) 236 detect a passing occurrence range having an upper limit of 480, and detect a passing occurrence range starting from “0”. When the adder 234 detects the overtaking occurrence range starting from “0” in the comparison unit (2) 236, the adder 234 maintains a connection with the detection of the overtaking occurrence range with “480” as the upper limit. The value “480” is added to the value output from the count value storage unit 233 in order to process the starting point “0” as “480” and output from the count value storage unit 233. The value added to the value is set by the CPU 8 as offset information included in the input determination threshold information. The CPU 8 further sets start line information (S1) and line range information (L1) as overtaking range information at the time of reduction or equal magnification to the overtaking range determining unit 231 as input determination threshold information, and the overtaking range determining unit 231 The overtaking occurrence range is determined according to the scaling rate information set by the CPU 8. FIG. 21 shows how the overtaking range determination unit 231 determines the overtaking occurrence range according to the scaling rate information. First, the range in which overtaking occurs during reduction or equal magnification is set by the CPU 8 as start line information (S1) and line range information (L1) including lines from “0” to M1. Further, when the scaling rate information is set to enlargement processing, start line information and line range information corresponding to the scaling rate information are obtained. When expanding twice, the range of L1 with S2 as the start line is output as a range where overtaking occurs, and when expanding three times, the range of L1 with S3 as the starting line is output as a range where overtaking occurs To do. In the case of enlarging to 4 times, if the range of L1 with S4 as the start line is set as a range where overtaking occurs, the upper limit value will interrupt “480”, so here the upper limit value is tripled. The range of L2, which is the same value as that when the image is enlarged, is output as a range where overtaking occurs.

  In this manner, the overtaking determination range information output from the overtaking range determination unit 231 changes according to the scaling rate information set by the CPU 8. The comparison unit (1) 235 determines whether or not the value output from the count value storage unit 233 is within the range of the overtaking determination range information output from the overtaking range determination unit 231. ) 236, it is determined whether or not the value output from the adder 234 is within the range of the overtaking determination range information output from the overtaking range determining unit 231, and any value is determined as the overtaking range determining unit 231. In the case of being within the range of the overtaking determination range information output from the OR element 237, the overtaking detection information is output.

  When the frame memory control unit 24 detects that the overtaking detection information is output from the overtaking determining unit 23, as shown in FIG. It is possible to avoid the occurrence of overtaking by rereading the image at ().

  As described above, the input signal processing unit in the case where the frame memory can store the image data for a plurality of frames and avoids the occurrence of overtaking by selecting and reading out the image data in the frame where no overtaking occurs. The manner in which the overtaking detection unit 23 included in 2 detects the occurrence of overtaking has been described. As described in the first embodiment, overtaking also occurs when image data is read from the output frame memory 3, and the output frame memory 3 can store image data for a plurality of frames. Similarly, the overtaking determination unit 43 included in the signal processing unit 4 can avoid the occurrence of overtaking by selecting and reading out image data in a frame in which no overtaking occurs.

  In this example, the situation in which overtaking occurs in the image data read from the output frame memory 3 and the timing at which the overtaking occurs changes according to the scaling rate will be described with reference to FIGS.

  In FIG. 22, it is assumed that the internal synchronization signal generation unit 6 generates a synchronization signal at a timing capable of processing 1080 lines, and the output synchronization signal generation unit 7 generates a synchronization signal to the display unit 9 having 720 lines. FIG. 22- (A) shows a state in which the input image data is subjected to the same-size processing or enlargement processing in the image processing unit 5, and FIG. 22- (B). Shows a state where the input image data is reduced by 2/3 times in the image processing unit 5.

When the image processing unit 5 performs equal magnification processing or enlargement processing, the ENB signal is continuously output from the image processing unit 5 to the output signal processing unit 4 as shown in FIGS. . Therefore, as shown in FIG. 22- (A), the image data output from the image processing unit 5 is output 720 during the period from 1 line to 720 lines of the SHS signal for 1080 lines generated in the cycle of the SVS signal. Line image data is written to the output frame memory 3 (thick solid line)
Thus, image data for 720 lines is read out in the cycle of the OVS signal (thin solid line). Here, when the reading of the image data of the new frame from the output frame memory 3 is started, the image data of the new frame is read from the output frame memory 3 as it is at the time T1 when the count value of the SHS signal becomes M1. And the write address and the read address cross each other, and overtaking occurs. In such a case, overtaking occurs until the count value of the SHS signal reaches “1080”, that is, when the readout of image data of a new frame from the output frame memory 3 is started, the count value of the SHS signal is Overtaking occurs between M1 and “1080”.

  Next, when the image processing unit 5 performs the reduction process to 2/3 times, the ENB signal is output from the image processing unit 5 to the output signal processing unit 4 at a rate of two times for three SHS signals. . That is, as shown in FIG. 22- (B), an ENB signal for 720 lines is output from the image processing unit 5 with respect to 1080 SHS signals generated by the internal synchronization signal generating unit 6, and the image processing unit 5, image data for 720 lines is generated and output from image data for 1080 lines output from the input signal processing unit 2 in synchronization with the REQ signal. Here, when the reading of the image data of the new frame from the output frame memory 3 is started, the image data of the new frame is read from the output frame memory 3 as it is at the time T2 when the count value of the SHS signal becomes M2. And overtaking will occur. In such a case, overtaking occurs until the count value of the SHS signal reaches “1080”, that is, when the readout of image data of a new frame from the output frame memory 3 is started, the count value of the SHS signal is Overtaking occurs between M2 and “1080”.

  FIG. 23 shows how the timing of overtaking changes according to the scaling rate. When the image processing unit 5 performs equal magnification processing or enlargement processing, the count value of the SHS signal at the time when reading of image data of a new frame from the output frame memory 3 is started is between M1 and “1080”. Sometimes overtaking occurs. At this time, the count value of the SHS signal output from the internal synchronization signal generator 6 (dotted line in FIG. 22) and the line number written to the output frame memory 3 (thick solid line in FIG. 22) are as shown in FIG. As shown in A). Next, when the image processing unit 5 performs the reduction process, the line number written to the output frame memory 3 in accordance with the reduction ratio becomes smaller than the count value of the SHS signal, as shown in FIG. 22- (B). In addition, the slope of the line number written to the output frame memory 3 becomes gentler than the slope for counting the SHS signal. Until the slope of the line number written to the output frame memory 3 (thick solid line in FIG. 22) matches the slope of the line number read from the output frame memory 3 (thin solid line in FIG. 22), the upper limit is “1080”. As the reduction ratio increases, the range in which overtaking occurs becomes narrower, the reduction ratio further increases, and the slope of the line number written to the output frame memory 3 is gentler than the slope of the line number read from the output frame memory 3. In such a case, the range in which overtaking occurs starts from “0” as the starting point.

  Thus, also in this example, the timing at which the overtaking occurs changes according to the scaling rate, and the overtaking determining unit 43 predicts the overtaking in consideration of the scaling rate set in the image processing unit 5. .

With reference to FIG. 7, how the overtaking determination unit 43 predicts overtaking will be described. The horizontal synchronization signal counting unit 432 counts the number of occurrences of the SHS signal output from the internal synchronization signal generation unit 6. The count value is initialized to “0” by the SVS signal. The number of occurrences of the SHS signal counted by the horizontal synchronization signal counting unit 432 is stored at the timing at which the OVS signal is generated by the count value storage unit 433, and the value stored by the count value storage unit 433 is the comparison unit ( 1) 435, the comparison unit (2) 436, and the adder 434. The comparison unit (1) 435 and the comparison unit (2) 436 detect an overtaking occurrence range with “1080” as an upper limit, and detect an overtaking occurrence range with “0” as a starting point. . When the adder 434 detects the overtaking generation range starting from “0” in the comparison unit (2) 436, the adder 434 maintains a connection with the detection of the overtaking generation range with “1080” as the upper limit. The value “1080” is added to the value output from the count value storage unit 433 in order to treat the starting point “0” as “1080”, and output from the count value storage unit 433. The value added to the value is set as offset information included in the output determination threshold information by the CPU 8. The CPU 8 further sets start line information (S1) and line range information (L1) as overtaking range information at the time of enlargement or equal magnification to the overtaking range determination unit 431 as output determination threshold information, and the overtaking range determination unit 431 The overtaking occurrence range is determined according to the scaling information set by the CPU 8. FIG. 24 shows how the overtaking range determination unit 431 determines the overtaking occurrence range according to the scaling information. First, the range in which overtaking occurs at the time of enlargement or equal magnification is set as start line information (S1) and line range information (L1) including the lines from M1 to “1080” from the CPU8. Further, when the scaling rate information is set to the reduction process by the CPU 8, start line information and line range information corresponding to the scaling rate information are obtained. In the case of reduction to ½ times, the range of L1 with S2 as the start line is output as a range where overtaking occurs. In the case of reduction to 1/3, if the range of L1 with S3 as the start line is set as the range where overtaking occurs, the start line exceeds “1080”, so that SMIN including “1080” is set as the start line. The range of L2 to be output is output as a range where overtaking occurs. Similarly, in the case of reduction to 1/4 times, the range of L3 is output as the range where overtaking occurs, with SMIN as the start line.

  In this manner, the overtaking determination range information output from the overtaking range determination unit 431 changes according to the scaling rate information set by the CPU 8. The comparison unit (1) 435 determines whether or not the value output from the count value storage unit 433 is within the range of the overtaking determination range information output from the overtaking range determination unit 431, and the comparison unit (2 ) 436, it is determined whether or not the value output from the adder 434 is within the range of the overtaking determination range information output from the overtaking range determination unit 431, and any of the values is overtaking range determination unit 431. In the case of being within the range of the overtaking determination range information output from the OR element 437, the overtaking detection information is output.

  When the frame memory control unit 44 detects that the overtaking detection information is output from the overtaking determination unit 43, as shown in FIG. It is possible to avoid the occurrence of overtaking by rereading the image at ().

Also in this example, the scaling rate information described in the above embodiments can be suitably used as the information corresponding to the reading speed from the memory. That is, when the scaling rate information is set as enlarged, the reading speed of the image data from the input frame memory 1 changes as shown in FIG. In addition to changing the reading speed according to the scaling rate information, when the processing of the image data processed by the image processing unit 5 requires a plurality of clock periods, the reading speed of the image data from the input frame memory 1 is set. It can also be used when changing. That is, single or plural pieces of information indicating some correspondence with the reading speed can be used as information corresponding to the reading speed. Also, the scaling rate information described in the above embodiments can be suitably used as the information corresponding to the writing speed in the memory. That is, when the scaling rate information is set as reduced, the writing speed of image data to the output frame memory 3 changes as shown in FIG. In addition to changing the writing speed according to the scaling rate information, when the processing of the image data processed by the image processing unit 5 requires a plurality of clock periods, the writing speed of the image data to the output frame memory 3 is set. It can also be used when changing.
That is, single or plural pieces of information indicating some correspondence with the writing speed can be used as information corresponding to the writing speed.

The block diagram which shows the structural example of the image signal processing apparatus containing the memory control apparatus of this invention. The block diagram which shows the structural example of the input signal process part which performs the frame rate conversion process of the input image data. The block diagram which shows the structural example of the overtaking determination part in an input signal processing part. The block diagram which shows another structural example of the overtaking determination part in an input signal processing part. The block diagram which shows the structural example of the output signal process part which performs the frame rate conversion process of the image output. The block diagram which shows the structural example of the overtaking determination part in an output signal processing part. The block diagram which shows another structural example of the overtaking determination part in an output signal processing part. The timing chart figure which shows a mode at the time of carrying out the equal magnification process of image data with an image signal processing apparatus. The timing chart figure which shows a mode at the time of the expansion process of image data with an image signal processing apparatus. The timing chart figure which shows a mode at the time of the reduction process of image data with an image signal processing apparatus. The schematic diagram which shows a mode that overtaking occurs and overtaking is avoided. The schematic diagram which shows a mode that the timing which an overtaking generate | occur | produces by an expansion process changes. The schematic diagram which shows a mode that the range in which an overtaking occurs by expansion processing changes. The schematic diagram which shows a mode that the overtaking generation range calculated | required in the overtaking determination part by an expansion process changes. The schematic diagram which shows a mode that the timing which an overtaking generate | occur | produces by a reduction process changes. The schematic diagram which shows a mode that the range which the overtaking generate | occur | produces by a reduction process changes. The schematic diagram which shows a mode that the overtaking generation range calculated | required in the overtaking determination part by a reduction process changes. FIG. 6 is a schematic diagram showing the occurrence of overtaking and another situation where overtaking is avoided. The schematic diagram which shows another mode from which the timing which overtaking occurs by expansion processing changes. The schematic diagram which shows another mode from which the range in which an overtaking occurs by an expansion process changes. The schematic diagram which shows another aspect from which the overtaking generation range calculated | required in the overtaking determination part by an expansion process changes. The schematic diagram which shows another mode from which the timing which overtaking occurs by reduction processing changes. The schematic diagram which shows another mode from which the range in which an overtaking occurs by a reduction process changes. The schematic diagram which shows another aspect from which the overtaking generation range calculated | required in the overtaking determination part by a reduction process changes.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input frame memory 2 Input signal processing part 3 Output frame memory 4 Output signal processing part 5 Image processing part 6 Internal synchronization signal generation part 7 Output synchronization signal generation part 8 CPU
9 Display unit 21, 41 Dual port memory 22, 42 Effective area determination unit 23, 43 Passing determination unit 24, 44 Frame memory control unit 231, 431 Passing range determination unit 232, 432 Horizontal synchronization signal determination unit 233, 433 Count value storage Units 234, 434 Adders 235, 236, 435, 436 Comparison units 237, 437 OR elements

Claims (6)

A memory control circuit for writing information to a memory in synchronization with a first synchronization signal, and reading information from the memory in synchronization with a second synchronization signal that is asynchronous with the first synchronization signal;
A prediction circuit that predicts overtaking between writing and reading information to the memory based on information corresponding to a speed at which the information is read from the memory or information corresponding to a speed at which the information is written to the memory;
Have
The memory control circuit executes control for writing information to the memory or reading information from the memory, which is executed when the overtaking is predicted, and is different from the control when the overtaking is not predicted. A memory control device characterized by avoiding overtaking. The memory control device according to claim 1, wherein the memory control circuit avoids overtaking by not writing information to the memory when the overtaking is predicted. The memory has a plurality of memory units,
The memory control circuit sequentially writes information to the plurality of memory units, and reads information from a memory unit in which no overtaking occurs when the overtaking in a predetermined memory unit is predicted. The memory control device according to claim 1, wherein overtaking is avoided by doing so. The memory control device according to claim 3, wherein the information is an image signal. 5. An image signal processing apparatus having the memory control apparatus according to claim 4 and the memory controlled by the memory control apparatus. An image display device comprising: the image signal processing device according to claim 5; and a display unit that performs display based on an image signal output from the image signal processing device.