JP2006261559A - Mos-type semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of an MOS-type semiconductor apparatus by eliminating movable and ionic impurities in a thinned gate insulating film by a simple configuration, with respect to the MOS-type semiconductor apparatus. <P>SOLUTION: The apparatus is provided with sub-gate electrodes 17 which is formed on both sides of a gate electrode 14 on the gate insulating film 13 and positions distant from a channel region 18 as a base of the film 13, and is applied with a voltage for discharging the movable impurities 19 from the gate insulating film 13 immediately below the gate electrode 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a MOS type semiconductor device in which the structure of a gate, in particular, the structure in the vicinity of a gate insulating film (oxide film) is improved to suppress the occurrence of leakage current and improve the reliability.

  In recent years, the progress of technology for manufacturing semiconductor integrated circuit devices has been remarkable. However, gate insulating films in MOS semiconductor devices have become increasingly thinner, and gate lengths and gate widths have been increasingly miniaturized.

  FIG. 7 is a cutaway side view showing a main part of a conventional standard MOS type semiconductor device. As shown in FIG. 7, a gate insulating film 33 is formed on a channel layer 32 epitaxially grown on a semiconductor substrate 31, and gate insulation is performed. A gate electrode 34 is formed on the film 33, and a source region 35 and a drain region 36 are formed on the sides of the gate.

  Although the MOS type semiconductor device shown in the drawing can be improved in performance by miniaturization, on the other hand, problems in terms of reliability as a semiconductor device are gradually becoming apparent.

  In recent miniaturized MOS type semiconductor devices, fluctuations in drain current of 2 to 3% are observed, characteristics change when stress is applied, and application of reverse stress, for example, reverse direction The phenomenon of recovery by an operation such as continuously applying a constant voltage has been observed, and these are caused by ionized impurity atoms (for example, sodium) present in the gate insulating film 33 or lattice defects (for example, hydrogen is released). It is thought that this is a defect.

  These ionized impurities or lattice defects are present in the lattice of the insulating film or between the lattices, and are considered to be movable at a very low speed.

  In the structure of the conventional MOS type semiconductor device described above, the movable ionized impurity or lattice defect is caused by the region under the gate electrode in the gate insulating film depending on the bias voltage during operation of the semiconductor device, or Since the distance between the impurities is reduced and the distance between the impurities is shortened, the probability of the tunnel effect between traps increases, resulting in an increase in gate leakage current and the formation of a sudden current path. However, there is an increased possibility of causing malfunction of the circuit and destruction of the device.

  The MOS type semiconductor device of the present invention is, of course, described in detail in the section [Disclosure of the Invention], but is based on a structure in which a sub-gate electrode is provided on the side of the gate electrode. A structure similar to this is already known (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4).

  However, any of these known examples is an invention for the purpose of controlling the inversion layer generated in the channel layer by applying a voltage to the sub-gate electrode, and in the present invention, as shown in FIG. It does not disclose a technique for eliminating mobile ionized impurities, and therefore the gate structure is naturally different.

  That is, since the inventions disclosed in Patent Document 1, Patent Document 3, and Patent Document 4 all control the threshold value with the voltage applied to the sub-gate electrode, the sub-gate electrode is present on the channel region. However, this is not necessary in the MOS type semiconductor device according to the present invention.

  Further, in the known example of Patent Document 2, the sub-gate electrode exists on the drain (or source) region and does not exist on the channel region, and thus has the same structure as the MOS type semiconductor device of the present invention. As will be recognized, in order to reduce the capacitance between the drain (or source) electrode and the sub-gate electrode, the insulating film under the sub-gate electrode has a thicker structure than the insulating film under the gate electrode. Yes.

On the other hand, in the present invention, the thickness of the insulating film under the sub-gate electrode is equal to or thinner than that of the insulating film under the gate electrode. It is recognized that the purpose and structure are different.
JP-A-1-207970 JP-A-4-326524 JP 2004-274209 A JP-A-6-283716

  In the present invention, it is intended to improve the reliability of a MOS type semiconductor device by removing movable and ionic impurities in a thin gate insulating film with a simple structure.

  In the MOS type semiconductor device according to the present invention, the channel region (for example, the gate insulating film, for example, on both sides of the gate electrode (for example, the gate electrode 14) on the gate insulating film (for example, the gate insulating film 13) A sub-gate electrode (for example, sub-gate electrode 17), which is formed at a position deviated from the channel region 14) and to which a voltage for eliminating movable impurities (for example, movable impurities 19) is applied from the gate insulating film immediately below the gate electrode. It is characterized by becoming.

  By adopting the above means, by applying an appropriate voltage to the sub-gate electrode, mobile ions such as impurities and defects in the gate insulating film can be removed from the region directly under the gate electrode and moved to the sub-gate electrode side. As a result, the tunnel current in the gate insulating film can be reduced, the generation of leakage current that causes the breakdown of the gate insulating film directly under the gate electrode is suppressed well, and the reliability of the MOS semiconductor device is improved. improves.

  FIG. 1 is a cutaway side view illustrating a MOS type semiconductor device embodying the present invention. As shown in FIG. 1, a gate insulating film 13 is formed on an epitaxially grown silicon semiconductor layer 12 formed on a silicon semiconductor substrate 11. Then, the gate electrode 14 is formed on the gate insulating film 13, and the gate insulating film 13 is dug down to the side of the gate electrode 14 to form a thinned region 13A. The sub-gate electrode 17 is formed on the thinned region 13A. The source region 15 and the drain region 16 are formed in the silicon semiconductor layer 12 on the side of the gate. Reference numeral 18 denotes a channel region immediately below the gate electrode 14, and 19 denotes an ionized impurity which has become movable.

  FIG. 2 and FIG. 3 are fragmentary cutaway side views showing the MOS type semiconductor device at the main points of the process for explaining the process of manufacturing the MOS type semiconductor device according to the present invention. Will be described with reference to FIG.

See Fig. 2 (1)
A silicon semiconductor layer 22 is epitaxially grown on the silicon semiconductor substrate 21 by applying an MBE (molecular beam epitaxy) method. This silicon semiconductor layer 22 operates as a channel layer. The MBE method may be replaced with the MOCVC (metal organic chemical vapor deposition) method. Although the process is slightly complicated, an oxide film may be formed on the surface of the silicon semiconductor layer 22 and attached to another silicon semiconductor substrate, and then the silicon semiconductor substrate 21 may be removed to form an SOI structure. .

See Fig. 3 (2)
A gate insulating film 23 made of SiO ₂ is formed by applying a thermal oxidation method and exposing the surface of the epitaxially grown silicon semiconductor layer 22 to water vapor in an electric furnace.

See Fig. 4 (3)
By applying a CVD (Chemical Vapor Deposition) method, a polysilicon layer is formed on the gate insulating film 23, and then by applying a lithography technique, the polysilicon layer is etched to form the gate electrode 24. Form.

Refer to FIG. 5 (4)
The source region 25 and the drain region 26 are formed by implanting As ions or Ga ions into the silicon semiconductor layer 22 by applying the ion implantation method.

See FIG. 6 (5)
By applying a resist process and a dry etching method in lithography technology, the gate insulating film 23 is etched to form openings in the source electrode formation scheduled portion and the drain electrode formation scheduled portion, and then a sputtering method is performed. A metal film is formed by application and then a resist process in the lithography technique and a dry etching method are applied again to form the source electrode 27 and the drain electrode 28 by etching the metal film. To do.

(6)
By applying a resist process in the lithography technique and a dry etching method, the sub-gate electrode formation scheduled portions of the gate insulating film 23 on both sides of the gate electrode 24 are etched to form a recess. The purpose of this etching is to make a part of the gate insulating film 23 thinner, and an opening penetrating the gate insulating film 23 is not formed.

(7)
A metal film is formed by applying a sputtering method, and then the metal film is etched to fill the recess by applying a resist process in a lithography technique and a dry etching method. A sub-gate electrode 29 is formed.

  As described above, the MOS type semiconductor device is completed. The voltage application to the sub-gate electrode 29 is performed in the course of the production of the MOS type semiconductor device, and from the gate insulating film 23 immediately below the gate electrode 24. After the removal of the movable impurities, no voltage is applied in a state where the device is actually operated. However, since impurities (defects) may be generated by actually operating the MOS semiconductor device, it is optional to apply a voltage to the sub-gate electrode 29 even during operation.

It is a principal part cutting side view which illustrates the MOS semiconductor device which implemented this invention. It is a principal part cutting side view showing the MOS type semiconductor device in a process important point. It is a principal part cutting side view showing the MOS type semiconductor device in a process important point. It is a principal part cutting side view showing the MOS type semiconductor device in a process important point. It is a principal part cutting side view showing the MOS type semiconductor device in a process important point. It is a principal part cutting side view showing the MOS type semiconductor device in a process important point. It is a principal part cutting side view showing the conventional standard MOS type semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Silicon semiconductor substrate 12 Epitaxial growth silicon semiconductor layer 13 Gate insulating film 13A Thinned region of gate insulating film 13 Gate electrode 15 Source region 16 Drain region 17 Sub-gate electrode 18 Channel region 19 Ionized movable impurity

Claims (2)

A sub-gate electrode formed on both sides of the gate electrode on the gate oxide film and at a position deviated from the channel region under the gate oxide film, to which a voltage for removing movable impurities is applied from the gate oxide film immediately below the gate electrode. A MOS type semiconductor device comprising: The gate oxide film that is the base of the sub-gate electrode is made thinner than the other parts, and the side surface of one of the sub-gate electrodes formed at the thinned portion is connected to the other through the gate oxide film on the channel region. 2. The MOS type semiconductor device according to claim 1, wherein the MOS type semiconductor device is opposed to a side surface of the sub-gate electrode.

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