JP2006261279A - Semiconductor switch integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively operate an ESD protection element without exerting any influence of the ESD protection element on high-frequency characterisitic. <P>SOLUTION: First and second separation switches 61 and 62 are provided between the gates of first and second switch FET elements 1 and 2 as a switch FET element for signal passage and a switch control circuit 102, respectively, and third and fourth separation switches 63 and 64 are provided between the gates of switch FET elements 3 and 4 for bypass and the switch control circuit 102. In non-operation state, the gates of the first to fourth switch FET elements 1 to 4 are electrically interrupted by the first to fourth separation switch 61 to 64 from the switch control circuit 102, and they get into an open state, permitting electric discharging of ESD surge by ESD protection elements 21 and 22. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor switch integrated circuit using a FET (Field Effect Transistor) switch element, and more particularly to a circuit that has improved surge resistance.

  Semiconductor switches are used for transmission / reception switching between an antenna of a mobile phone terminal and a radio circuit, and switching between a transceiver of a plurality of frequency bands and a plurality of antenna terminals. As the switch elements constituting this semiconductor switch, there are mainly those using PIN diodes and those using GaAsFETs. The former is GSM (Global System for Mobile Communications) with a large transmission output, and the latter is compared with GSM. It is used for portable terminals such as PDC (Personal Digital Cellular), PHS (Personal Handyphone System), and CDMA (Code Division Multiple Access), which have relatively low transmission power.

In the portable terminal as described above, a semiconductor switch using GaAsFET is used as an antenna switch for switching between a plurality of antenna terminals and a transmitter / receiver terminal. A decoder circuit for controlling elements is sometimes incorporated, and the tendency of the circuit configuration to be complicated is remarkable.
In such an antenna switch using a GaAsFET, a depletion type FET is mainly used as a switch element. As a method of configuring a switch using the depletion type FET, there are two types of configuration methods as described below.

  One of them is that the FET drain and source are arranged between the high-frequency signal terminals, the gate terminal is set as a control terminal, and a potential corresponding to the logical value High is set, thereby turning on the FET and conducting between the high-frequency terminals. On the other hand, there is a type of switch called a series switch configured to shut off between high-frequency terminals by setting the gate terminal to a low potential which is a ground potential, thereby turning off the FET by the cutoff characteristic of the FET.

  The other is that the drain and source of the FET are arranged between the high-frequency signal terminal and the ground terminal, and the FET is turned on by applying a potential corresponding to the logical value High to the gate terminal as the control terminal. The high-frequency signal terminal and the ground terminal are electrically connected to cut off the high-frequency signal terminal, while the FET is turned off by applying a potential corresponding to the logical value Low to the gate terminal, and the high-frequency signal terminal and the ground are grounded. There is what is called a parallel switch configured so as to bring the high-frequency signal terminals into a conductive state by interrupting the terminals.

In the case of configuring an antenna switch, it is possible to switch a complicated path with low insertion loss and high isolation by appropriately using these together.
The antenna switch drives a plurality of switch elements, but basically one drive signal is required for one switch element. Actually, the switch control from the outside of the antenna switch can be controlled with the minimum number of terminals, a control circuit such as a decoder is provided in the antenna switch, and the control signal input from the outside is sent to each switch element. In many cases, the control is assigned to the control.

When an antenna switch is used in a mobile terminal, the possibility of being exposed to the outside is relatively high among various semiconductor elements used in the mobile terminal. For this reason, it is required to have high resistance against electrostatic discharge (ESD).
However, the ESD resistance of the GaAsFET itself is not necessarily high. In particular, the gate terminal and the drain-source between the off state are about 15 V to 30 V depending on the device structure, and some low noise elements have lower elements.

  In an antenna switch, a FET having a relatively high breakdown voltage and a large gate width is often used as a switch element. In addition, since it is sometimes used connected in series from the viewpoint of improving linearity, it is low noise in terms of ESD tolerance. In general, it has a high resistance compared to an element, but it is not always sufficient, and an ESD resistance technology needs to be improved.

Increasing the ESD protection capability at the high-frequency signal terminal of the antenna switch can be realized by providing an ESD protection element between the high-frequency signal terminal and the ground terminal, but the following problems arise.
In other words, the ESD protection element is designed to have a high impedance during normal operation when no ESD surge is applied, but due to the characteristic of the function of discharging a large current due to ESD, the element size is large, so parasitic capacitance is ignored. Can not. Such parasitic capacitance acts as a mismatching element for high-frequency signals, leading to an increase in insertion loss and an increase in reflection loss. For this reason, when an ESD protection element is connected to the high-frequency signal terminal, the parasitic capacitance value is desirably as low as possible.

Further, the ESD protection element also becomes a source of distortion. In WCDMA requiring low distortion and GSM with large transmission power, the generation of slight distortion becomes a problem, so strict standards are applied.
However, there is a trade-off between ESD protection and distortion reduction. When an ESD protection element is used for a high-frequency signal terminal, it is difficult to satisfy both ESD protection and distortion reduction.

  As described above, in the antenna switch, a depletion type FET is usually used, and the connection terminal side of the parallel type FET described above is not directly grounded but is short-circuited at high frequency using a large-capacitance capacitor. Is used. In this case, when the ESD protection element is not used, there is no discharge path between the high-frequency signal terminal and the ground terminal, so a method of adding an ESD protection element between both ends of the capacitor can be considered. In such a configuration, the ESD protection terminal hardly affects the high-frequency signal, so that the problem of distortion can be avoided.

  In this method, since the switch FET elements are connected in series at a plurality of locations between the high-frequency signal terminal and the ESD protection element, all the switch elements are required to operate the ESD protection element effectively. Is in an on state, that is, in a conductive state.

FIG. 7 shows an example of the circuit configuration of the antenna switch IC having the above-described configuration. Hereinafter, with reference to FIG. 7, problems in circuit operation with respect to the use of the ESD protection element in the antenna switch IC are shown. explain.
The antenna switch IC shown in FIG. 7 functions as a single pole double throw switch (hereinafter referred to as “SPDT switch”), and the first switch FET element 1 has a first high-frequency signal terminal. 51 and the second high-frequency signal terminal 52 are connected in series, and the second switch FET element 2 is connected in series between the first high-frequency signal terminal 51 and the third high-frequency signal terminal 53. ing. Here, for convenience of explanation, the first and second switch FET elements 1 and 2 are referred to as “series switch elements”.

  On the other hand, the third switch FET element 3 is connected between the second high-frequency signal terminal 52 and the ground via the first capacitor 25, and the fourth switch FET element 4 is connected to the third high-frequency signal terminal 52. The signal terminal 53 is connected to the ground via the second capacitor 26. Here, for convenience of explanation, the third and fourth switch FET elements 3 and 4 are referred to as “parallel switch elements”.

  These first to fourth switch FET elements 1 to 4 can be controlled in operation by applying a control signal from the switch control circuit 102 to the respective gates via the gate resistors 41 to 44. It has become. The switch control circuit 102 receives a switch control signal for the switch control circuit from the outside to the switch control external terminal 58, and drives the first to fourth switch FET elements 1 to 4 in accordance with the switch control signal. It is configured to output a control signal necessary for the operation.

  In order to prevent malfunctions caused by leakage of high-frequency signals passing through the switch FET elements 1 to 4 into the switch control circuit 102, connection points between the gate resistors 41 to 44 and the switch control circuit 102. The bypass capacitors 31 to 34 are connected between the ground and the ground.

In this configuration, it is assumed that the first to fourth switch FET elements 1 to 4 are depletion type FETs.
The depletion type FET is called a normally-on type, and is an element that can easily be turned on. For example, when ESD is applied to the source or drain when the gate electrode is in an open state, the gate potential rises through the capacitance between the gate and drain or between the gate and source, and is higher than that of the drain or source electrode. Since it becomes a potential, it is always turned on.
When this is seen in the circuit shown in FIG. 7, the first to fourth switch FET elements 1 to 4 are effective discharge paths for the ESD surge, and therefore the first to fourth switch FET elements 1 to 4 are used. It is less likely to destroy itself.
In addition, as this kind of semiconductor switch circuit, what was disclosed by patent document 1 or patent document 2 is known, for example.

JP 2003-100953 A (page 5-9, FIGS. 1 to 9) JP 2004-229075 A (page 4-8, FIGS. 1 to 7)

  However, when the switch control circuit 102 is provided inside the antenna switch IC as shown in FIG. 7, the gates of the switch FET elements 1 to 4 are terminated by the switch control circuit 102. This portion is not particularly fixed in voltage, but usually has a low potential. This is because the switch control circuit 102 itself operates with a small current, and thus the element size used inside is small, and therefore the ESD resistance of the switch control circuit 102 is usually low.

  For this reason, normally, an ESD protection element is added to the power supply terminal, the input terminal, etc. in the switch control circuit 102 to improve ESD resistance. However, since the protection element has a clamp voltage, the switch control circuit 102 It is fixed at the clamp voltage. According to the simulation by the applicant of the present application, such a switch control circuit 102 can be regarded as a portion where the potential is fixed.

Further, in the circuit shown in FIG. 7, since the bypass capacitors 31 to 34 can be regarded as not being charged before the ESD surge is applied, the short-circuit element is applied when the ESD surge is applied. Will function as.
For this reason, the bypass capacitors 31 to 34 and the switch control circuit 102 have the function of fixing the gates of the switch FET elements 1 to 4 to the ground potential or a low potential close thereto. Can be caught.

In such a circuit, when ESD is applied to the high-frequency signal terminal, the first to fourth switch FET elements 1 to 4 are turned off even if they are depletion type FETs. For this reason, the switch FET elements 1 to 4 cannot operate as an ESD discharge path, and as a result, a voltage higher than the breakdown voltage of the FET is applied between the terminals, and eventually the breakdown occurs.
That is, in the antenna switch IC incorporating the switch control circuit 102, the switch FET element is not necessarily turned on but may be turned off, resulting in a problem that the ESD tolerance is reduced.

  The present invention has been made in view of the above circumstances, and provides a semiconductor switch integrated circuit having good ESD protection characteristics without the ESD protection element affecting high frequency characteristics.

In order to achieve the above object of the present invention, a semiconductor switch integrated circuit according to the present invention includes:
A plurality of high-frequency signal terminals are provided, and at least one signal-passing switch FET element is connected between the plurality of high-frequency signal terminals, and is connected to an end of the signal-passing switch FET element. At least one bypass switch FET element is connected between one of the high frequency signal terminals and the ground, and outputs a signal for controlling the operation of the signal passing switch FET element and the bypass switch FET element, A semiconductor switch integrated circuit comprising a switch control circuit configured to enable conduction between desired high frequency signal terminals among a plurality of high frequency signal terminals,
Provided between the gates of the signal passing switch FET element and the bypass switch FET element and the switch control circuit are separation switches that open the respective gates when not in operation,
When an ESD surge is applied, all the signal passing switch FET elements and the bypass switch FET elements are made conductive to enable ESD discharge.

  According to the present invention, when an ESD surge is applied, all the signal passing switch FET elements and the bypass switch FET elements are made conductive, so that the discharge is reliably performed through the ESD protection element. On the other hand, during normal operation, the ESD protection element does not affect the circuit operation at all, the characteristic deterioration between the high frequency signal terminals is prevented, and the number of ESD protection elements is smaller than that of the conventional one. A semiconductor switch integrated circuit having high ESD protection capability can be provided.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. The same components as those in the conventional circuit shown in FIG.
First, a basic configuration example of a semiconductor switch integrated circuit according to an embodiment of the present invention will be described with reference to FIG.
The semiconductor switch integrated circuit according to the embodiment of the present invention is roughly divided into a switch unit 101 and a switch control circuit 102. The switch unit 101 is a single pole double throw switch (SPDT switch). Is an example configured.

The switch unit 101 includes the first to fourth switch FET elements 1 to 4 and the first to fourth separation switches 61 to 64 as main components, and the first high-frequency signal terminal 51 and the second or The third high-frequency signal terminals 52 and 53 can be connected.
As the first to fourth switch FET elements 1 to 4, specifically, depletion type FETs (field effect transistors) are used.

  The drains (or sources) of the first and second switch FET elements 1 and 2 as signal passing switch FET elements are both connected to the first high-frequency signal terminal 51, while the source of the first switch FET element ( (Or drain) is connected to the second high-frequency signal terminal 52, and the source (or drain) of the second switch FET element 2 is connected to the third high-frequency signal terminal 53. For convenience of explanation, the first and second switch FET elements 1 and 2 are referred to as “series switch elements”.

Further, the third switch FET element 3 as the bypass switch FET element has its drain (or source) connected to the second high-frequency signal terminal 52, and between the source (or drain) and the ground side. The first capacitor 25 and the first ESD protection element 21 are connected in parallel.
Further, the fourth switch FET element 4 as the bypass switch FET element has its drain (or source) connected to the third high-frequency signal terminal 53, and between the source (or drain) and the ground side. The second capacitor 26 and the second ESD protection element 22 are connected in parallel. For convenience of explanation, the third and fourth switch FET elements 3 and 4 are referred to as “parallel switch elements”.

  Still further, the first of the first to fourth switch FET elements 1 to 4 and the switch control circuit 102 that outputs control signals to the gates of the first to fourth switch FET elements 1 to 4 are output. Between the 1st thru | or 4th control signal terminals 54a-54d, the 1st, 2nd, 3rd and 4th isolation | separation switch 61, 62, 63, 64 is each provided. The power supply voltage from the switch control circuit 102 is applied to predetermined locations of the first to fourth separation switches 61 to 64 from an internal power supply terminal 55 provided in the switch control circuit 102. ing.

  The switch control circuit 102 is grounded via an external ground terminal 56, while a predetermined power supply voltage is applied from the outside via a switch external power supply terminal 57. A predetermined control voltage is applied to the switch control external terminal 58 from an external circuit (not shown), and the first to fourth control signal terminals 54a to 54d are supplied to the first to fourth control signal terminals 54a to 54d according to the control voltage. A control signal for turning on or off the switch FET elements 1 to 4 is output.

  In such a configuration, the operation as a high-frequency signal switch is basically the same as this kind of known and well-known switch, and generally described below, the switch control external terminal 58 of the switch control circuit 102 is connected to the switch control external terminal 58. Then, a control voltage corresponding to a desired high-frequency signal path, that is, between the first to third high-frequency signal terminals 51 to 53 to be brought into a conductive state is applied. Then, a control signal is output to the first to fourth control signal terminals 54a to 54d in accordance with the logic state of the control voltage, and as a result, the desired high frequency signal terminals are made conductive and a high frequency signal path is formed. Will be.

Next, an ESD protection function in the semiconductor switch integrated circuit having such a configuration will be described.
Usually, ESD protection is a problem in a state where the circuit is handled as an individual component, that is, no power supply voltage is applied to the semiconductor switch integrated circuit, and the first to third high-frequency signals are applied. Since the problem occurs when the terminals 51 to 53 are open, in the following description, it is assumed that the integrated semiconductor circuit is in such a state.

In this state, it is assumed that an ESD surge having a positive polarity on the first high-frequency signal terminal 51 side is applied between the first high-frequency signal terminal 51 and the external ground terminal 56.
Since no power supply voltage is applied to the switch control circuit 102, no voltage is generated at the internal power supply terminal 55, so that the switch control circuit 102 has the same potential as the ground potential. For this reason, the gates of the first to fourth separation switches 61 to 64 are also at the ground potential, and the first to fourth separation switches 61 to 64 are turned off.
This state is equivalent to the open state when the first to fourth separation switches 61 to 64 are viewed from the gate side of the first to fourth switch FET elements 1 to 4.

The first high-frequency signal terminal 51 has its potential suddenly increased on the positive electrode side by applying positive ESD, and the first switch FET element 1 has a drain (or source) and a second one. The potential of the drain (or source) of the switch FET element 2 increases on the positive electrode side.
Accordingly, in the first switch FET element 1, the gate potential is increased due to the capacitance between the drain (or source) and the gate and between the gate and the source (or drain).

Then, since the gate potential of the first switch FET element 1 is higher than the source (or drain) potential, the first switch FET element 1 is turned on, and the drain (or source) and the source (or drain) are turned on. Are substantially the same potential. Similarly, the second switch FET element 2 is also turned on.
The same applies to the third and fourth switch FET elements 3 and 4 that are parallel switch elements. After all, all the switch FET elements 1 to 4 are turned on.

As a result, the ESD applied to the first high-frequency signal terminal 51 is divided into two paths, the source (or drain) of the third switch FET element 3 and the source (or drain) of the fourth switch FET element 4. However, since the ESD protection elements 21 and 22 are connected to each other, if the potential at this part exceeds the operating voltage of the ESD protection elements 21 and 22, A conductive state is established and discharging is performed.
For this reason, the potential at the first high-frequency signal terminal 51 is held at a voltage slightly higher than the clamp voltage of the ESD protection elements 21 and 22.

  Here, the clamp voltage of the ESD protection elements 21 and 22 is set to be lower than the breakdown voltage of the first to fourth switch FET elements 1 to 4 and the first and second capacitors 25 and 26. In this case, the semiconductor switch integrated circuit is not destroyed by ESD.

Next, a case where a negative ESD surge is applied to the first high-frequency signal terminal 51 will be described.
The gate potentials of the first to fourth switch FET elements 1 to 4 are the same as those when the positive ESD surge described above is applied.
When a negative ESD surge is applied to the first high-frequency signal terminal 51, the drain (or source) potential of the first switch FET element 1 is lower than the ground potential. On the other hand, the gate potential of the first switch FET element 1 is relatively higher than the drain (or source) potential even though it is the ground potential. 1 is turned on. The same applies to the other second to fourth switch FET elements 2 to 4, and all of the first to fourth switch FET elements 1 to 4 are turned on after all. Then, the ESD surge applied to the first high-frequency signal terminal 51 appears at the source (or drain) of the third switch FET element 3 and the source (or drain) of the fourth switch FET element 4.

Since the ESD protection elements 21 and 22 are connected to the sources (or drains) of the third and fourth switch FET elements 3 and 4, the potential of this portion is a negative operating voltage of the ESD protection elements 21 and 22. When the voltage reaches Vr, the ESD protection elements 21 and 22 become conductive and discharge is performed.
Therefore, the potential of the first high-frequency signal terminal 51 is held at a potential slightly higher than the clamp voltage of the ESD protection elements 21 and 22.

Therefore, if the clamp voltage of the ESD protection elements 21 and 22 is set lower than the breakdown voltage of the first to fourth switch FET elements 1 to 4 and the first and second capacitors 25 and 26, the semiconductor The switch integrated circuit is not destroyed by ESD.
The above-described ESD protection operation is basically the same even when an ESD surge is applied to the second and third high-frequency signal terminals 52 and 53.
As described above, the semiconductor switch integrated circuit according to the embodiment of the present invention exhibits a sufficient protection function against both positive and negative ESD surges.

Next, a more specific circuit configuration example based on the above-described basic configuration example will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. Hereinafter, different points will be mainly described.
This specific circuit configuration example is a specific circuit example of the first to fourth separation switches 61 to 64 in the basic circuit configuration shown in FIG. The configuration of the fourth to fourth separation switches 61 to 64 and the connection with the peripheral portions will be described.

  First, the first to fourth separation switches 61 to 64 all have the same circuit configuration. Here, the configuration of the first separation switch 61 will be described, and the second to fourth separation switches will be described. The description of the configuration of the fourth separation switches 62 to 64 will be replaced. In FIG. 2, the components of the second to fourth separation switches 62 to 64 corresponding to the components of the first separation switch 61 are denoted by reference numerals, respectively.

The first separation switch 61 is composed of a first gate switch FET 5 and a first diode 11. Here, an enhancement type FET is suitable for the first gate switch FET 5, but a depletion type FET can also be used in consideration of an applied voltage from the internal power supply terminal 55 of the switch control circuit 102.
The drain (or source) of the first gate switch FET5 is connected to the gate of the first switch FET element 1 through the first gate resistor 41, and the first gate switch FET5 and the first gate resistance. The connection point with the device 41 is grounded via the first bypass capacitor 31.

  The source (or drain) of the first gate switch FET5 is connected to the first control signal terminal 54a of the switch control circuit 102, while the gate is switched via the first gate resistor 45 for the separation switch. It is connected to the internal power supply terminal 55 of the control circuit 102.

Similarly, the drain (or source) of the second gate switch FET 6 constituting the second isolation switch 62 is connected to the gate of the second switch FET element 2 via the second gate resistor 42. The second bypass capacitor 32 is grounded.
The source (or drain) of the second gate switch FET6 is connected to the second control signal terminal 54b, while the gate is connected to the inside of the switch control circuit 102 via the second gate resistor 46 for separation switch. The power supply terminal 55 is connected.

The drain (or source) of the third gate switch FET7 constituting the third isolation switch 63 is connected to the gate of the third switch FET element 3 via the third gate resistor 43, and the third Are grounded via a bypass capacitor 33.
The source (or drain) of the third gate switch FET7 is connected to the third control signal terminal 54c, while the gate is connected to the inside of the switch control circuit 102 via the third gate resistor 47 for separation switch. The power supply terminal 55 is connected.

The drain (or source) of the fourth gate switch FET 8 constituting the fourth isolation switch 64 is connected to the gate of the fourth switch FET element 4 via the fourth gate resistor 44, and the fourth Are grounded via a bypass capacitor 34.
The source (or drain) of the fourth gate switch FET8 is connected to the fourth control signal terminal 54d, while the gate is connected to the inside of the switch control circuit 102 via the separation switch fourth gate resistor 48. The power supply terminal 55 is connected.

  In the above configuration, the first to fourth gate resistors 41 to 44 and the first to fourth bypass capacitors 31 to 34 are for the purpose of separating high-frequency signals and fulfill an ESD protection function. It is not a thing.

The operation as a high-frequency switch in such a configuration is not different from the basic circuit configuration example shown in FIG. 1 and is the same as that of a general high-frequency switch of this type, and therefore the description thereof is omitted here.
Further, since the ESD protection operation is the same as that described in the basic circuit configuration example shown in FIG. 1, only a general description will be given here.
It is assumed that the preconditions for considering the ESD protection operation are the same as those described in the basic circuit configuration example in FIG.

First, when positive ESD is applied to the first high-frequency signal terminal 51, the gates of the first to fourth switch FET elements 1 to 4 are off of the first to fourth separation switches 61 to 64. Since it is opened according to the state, all are turned on.
Then, as a result of ESD appearing as it is at the sources (or drains) of the third and fourth switch FET elements 3 and 4, ESD exceeds the operating voltage Vt of the ESD protection elements 21 and 22 connected to the respective sources. At this time, the ESD protection elements 21 and 22 suddenly become conductive, and discharge is performed.

  On the other hand, when negative ESD is applied to the first high-frequency signal terminal 51, the gates of the first to fourth switch FET elements 1 to 4 have a relatively high potential with respect to the drain (or source). As a result, when the positive ESD is applied, the first to fourth switch FET elements 1 to 4 are all turned on. As a result, the source (or drain) voltage of the third and fourth switch FET elements 3 and 4 exceeded the operating voltage Vt of the ESD protection elements 21 and 22 in the same manner as when positive ESD was applied. At this time, the ESD protection elements 21 and 22 suddenly become conductive, and discharge is performed.

  As described above, the characteristic feature of the semiconductor switch integrated circuit according to the embodiment of the present invention is that the first to fourth separation switches are provided between the switch control circuit 102 and the first to fourth switch FET elements 1 to 4. 61 to 64 are provided, but when the first to fourth separation switches 61 to 64 are not provided, the following state is obtained.

  First, when the first to fourth separation switches 61 to 64 are not provided, the gates of the first to fourth switch FET elements 1 to 4 are fixed to the ground potential even when ESD is applied. When the potential of the first high-frequency signal terminal 51 increases on the positive electrode side, even if the first switch FET element 1 is in the off state, the drain potential becomes the source due to the leak current between the drain and the source. It will be reported and will increase. At this time, since the gate of the first switch FET element 1 is maintained at the ground potential, the first switch FET element 1 is maintained in the OFF state.

  The same applies to the other second to fourth switch FET elements 2 to 4, and all of the first to fourth switch FET elements 1 to 4 are eventually turned off. Therefore, unlike the case where the first to fourth separation switches 61 to 64 are provided, the source potential of the third and fourth switch FET elements 3 and 4 exceeds the operating potential Vt of the ESD protection elements 21 and 22. The ESD protection elements 21 and 22 are not operated, and the ESD applied voltage is applied to the third and fourth switch FET elements 3 and 4 as they are. Depending on the magnitude of the ESD surge voltage, The fourth switch FET elements 3 and 4 are destroyed.

  On the other hand, in the case where the first to fourth separation switches 61 to 64 are not provided and the negative ESD is applied to the first high-frequency signal terminal 51, the first to fourth separation switches 61 to 64 are switched. Regardless of the presence or absence, the first to fourth switch FET elements 1 to 4 are turned on, and there is no difference in this point depending on the presence or absence of the first to fourth separation switches 61 to 64. However, ESD protection has no intrinsic meaning unless it has both positive and negative polarities. For this reason, when the first to fourth separation switches 61 to 64 are not used, the ESD tolerance particularly when positive polarity ESD is applied is lowered.

  The semiconductor switch integrated circuit according to the embodiment of the present invention has three high-frequency signal terminals 51 to 53. If the conventional circuit has a configuration in which an ESD protection element is directly connected to the high-frequency signal terminal, three ESDs are provided. Where a protection element is required, in the case of the present invention, ESD protection can be realized by two ESD protection elements. In addition, the ESD protection elements 21 and 22 of the semiconductor switch integrated circuit according to the embodiment of the present invention do not cause deterioration of distortion characteristics with respect to high-frequency signals, and the capacitance of the ESD protection elements 21 and 22 does not matter. In addition, it is not necessary to be an ESD protection element having a special specification.

Next, the ESD protection test example of the semiconductor switch integrated circuit having the configuration shown in FIG. 2 in the semiconductor switch integrated circuit according to the embodiment of the present invention will be described with reference to FIGS. However, it will be explained.
First, the test example shown in FIG. 3 will be described. In FIG. 3, the first example is a case where a surge of MM (Machine Model) +200 V is applied as an ESD surge between the first high-frequency signal terminal 51 and the ground. The terminal voltage change in the high frequency signal terminal 51 is shown. In the figure, the solid characteristic line indicates the characteristic of the semiconductor switch integrated circuit in the embodiment of the present invention, and the dotted line indicates the change characteristic in the conventional circuit for the same test. It is assumed that the conventional circuit does not have the first to fourth separation switches 61 to 64 in the circuit configuration example shown in FIG. 2 according to the embodiment of the present invention. The same applies to the examples.

According to this test result, in the conventional circuit, the terminal voltage (corresponding to the voltage of the first high-frequency signal terminal 51) reaches about 130 V after about 30 ns after the surge is applied. In the case of the semiconductor switch integrated circuit in FIG. 2, it can be confirmed that the terminal voltage at the first high-frequency signal terminal 51 is clamped to 40 V at the maximum.
Among these 40V voltages, about 20V is a clamp voltage by the ESD protection elements 21 and 22, and a voltage of about 10V is directly applied to the first to fourth switch FET elements 1 to 4, respectively. It is enough to avoid voltage breakdown.
On the other hand, in the case of the conventional circuit, the voltage reaches 55 V, and destruction occurs.

Next, a test example when MM-200 V is similarly applied to the first high-frequency signal terminal 51 as an ESD surge will be described with reference to FIG.
In this test example, there is no significant difference between the semiconductor switch integrated circuit according to the embodiment of the present invention and the conventional circuit until about 40 ns after the application of the surge in which the terminal voltage has a negative polarity, and is about -40V. It is clamped with.

As described above, in the case of applying a negative polarity surge, all the switch FET elements 1 to 4 can be kept on in both the semiconductor switch integrated circuit and the conventional circuit in the embodiment of the present invention. Because.
However, since the polarity is reversed in the MM surge, a difference occurs between the operations after that. That is, in the semiconductor switch integrated circuit according to the embodiment of the present invention, it is clamped at +20 V (see the characteristic line of the solid line in FIG. 4), whereas in the case of the conventional circuit, about 63 ns after applying the surge, A maximum voltage of +67 V is generated (see the dotted characteristic line in FIG. 4).
As described above, in the semiconductor switch integrated circuit according to the embodiment of the present invention, it is confirmed that the terminal voltage at the time of surge application can be clamped low because the switch FET element can be kept on regardless of the polarity of the surge. it can.

Next, a test example when HBM (Human Body Model) +2000 V is applied as an ESD surge will be described with reference to FIG.
In this test example, the semiconductor switch integrated circuit according to the embodiment of the present invention can clamp the terminal voltage at about + 30V (see the characteristic line of the solid line in FIG. 5), whereas the conventional circuit reaches a maximum of 140V. Therefore, it can be confirmed that the semiconductor switch integrated circuit according to the embodiment of the present invention exhibits a reliable ESD protection function.

FIG. 6 shows a test example for HBM-2000V. In this case, there is no difference between the semiconductor switch integrated circuit in the embodiment of the present invention and the conventional circuit, and it can be confirmed that they have the same characteristics. .
From these test examples, the semiconductor switch integrated circuit according to the embodiment of the present invention can be reliably clamped at a voltage lower than that of the conventional circuit, and can greatly improve the ESD protection function as compared with the conventional circuit. It can be confirmed that

It is a block diagram which shows the basic structural example of the semiconductor switch integrated circuit in embodiment of this invention. FIG. 2 is a circuit diagram showing a more specific first circuit configuration example of the semiconductor switch integrated circuit shown in FIG. 1. It is a characteristic diagram which shows the change of the terminal voltage of the semiconductor switch integrated circuit in embodiment of this invention when the ESD surge of MM + 200V is applied with the characteristic of a conventional circuit. It is a characteristic diagram which shows the change of the terminal voltage of the semiconductor switch integrated circuit in embodiment of this invention when the ESD surge of MM-200V is applied with the characteristic of a conventional circuit. It is a characteristic diagram which shows the change of the terminal voltage of the semiconductor switch integrated circuit in embodiment of this invention when an ESD surge of HBM + 2000V is applied with the characteristic of a conventional circuit. It is a characteristic diagram which shows the change of the terminal voltage of the semiconductor switch integrated circuit in embodiment of this invention when an ESD surge of HBM-2000V is applied with the characteristic of a conventional circuit. It is a circuit diagram which shows the circuit structural example of a conventional circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st switch FET element 2 ... 2nd switch FET element 3 ... 3rd switch FET element 4 ... 4th switch FET element 21, 22 ... ESD protection element 51 ... 1st high frequency signal terminal 52 ... 1st 2 high frequency signal terminals 53 ... 3rd high frequency signal terminal 61 ... 1st separation switch 62 ... 2nd separation switch 63 ... 3rd separation switch 64 ... 4th separation switch 101 ... switch part 102 ... switch control circuit

Claims (3)

A plurality of high-frequency signal terminals are provided, and at least one signal-passing switch FET element is connected between the plurality of high-frequency signal terminals, and is connected to an end of the signal-passing switch FET element. At least one bypass switch FET element is connected between one of the high frequency signal terminals and the ground, and outputs a signal for controlling the operation of the signal passing switch FET element and the bypass switch FET element, A semiconductor switch integrated circuit comprising a switch control circuit configured to enable conduction between desired high frequency signal terminals among a plurality of high frequency signal terminals,
Provided between the gates of the signal passing switch FET element and the bypass switch FET element and the switch control circuit are separation switches that open the respective gates when not in operation,
A semiconductor switch integrated circuit, wherein all the signal passing switch FET elements and the bypass switch FET elements are made conductive when an ESD surge is applied, thereby enabling ESD discharge.   2. The semiconductor switch integrated circuit according to claim 1, wherein the bypass switch FET element is grounded via a capacitor, and an ESD protection element is connected in parallel to the capacitor.   3. The semiconductor switch integrated circuit according to claim 1, wherein the separation switch is a gate switch made of a semiconductor element.

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