JP2006251931A - Cpu-to-cpu communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CPU-to-CPU communication system capable of reducing errors such as underruns and overruns during high-speed communication. <P>SOLUTION: A first CPU 1 generates first clocks 7 and sends first data in sequence and in synchronism with the first clocks 7. A second CPU 2 generates second clocks 8. A first FIFO 3 holds the first data from the first CPU 1 in sequence and outputs the first data that it holds as second data in sequence and in synchronism with transfer clocks 9. A second FIFO 4 holds the second data in sequence and outputs the second data that it holds to the second CPU 2 as third data in sequence and in synchronism with the second clocks 8. A clock control circuit 10 outputs one of the first clocks 7 from the first CPU 1 and the second clocks 8 from the second CPU 2 to the first FIFO 3 as the transfer clocks 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inter-CPU communication system that performs communication between CPUs (Central Processing Units).

  When high-speed communication is performed between CPUs, underruns due to differences in processing performance of each CPU, the buffer for data transfer, and the size of FIFO (First In First Out), Errors such as overruns can occur. This will be described.

FIG. 1 is a block diagram showing a configuration of a conventional inter-CPU communication system. A conventional inter-CPU communication system includes CPUs 101 and 102 and FIFOs 103, 104, 105, and 106.
The CPU 101 is connected to a FIFO 103 which is a FIFO on the transmission side and a FIFO 105 which is a FIFO on the reception side. The CPU 102 is connected to a FIFO 106 that is a FIFO on the transmission side and a FIFO 104 that is a FIFO on the reception side. Thereby, communication between CPUs is performed.

The CPU 101 generates a first clock and transmits data in synchronization with the first clock. Further, the CPU 101 supplies a first clock to the FIFOs 103 and 105.
The CPU 102 generates a second clock and sequentially transmits data in synchronization with the second clock. In addition, the CPU 102 supplies the second clock to the FIFOs 104 and 106.
The FIFO 103 sequentially holds the data from the CPU 101, and sequentially outputs the data held by itself to the FIFO 104 in synchronization with the first clock.
The FIFO 104 sequentially holds the data from the FIFO 103 and sequentially outputs the data held by itself to the CPU 102 in synchronization with the second clock.
The FIFO 106 sequentially holds the data from the CPU 102 and sequentially outputs the data held by itself to the FIFO 105 in synchronization with the second clock.
The FIFO 105 sequentially holds the data from the FIFO 106 and sequentially outputs the data held by itself to the CPU 101 in synchronization with the first clock.

  Normally, when high-speed communication is performed between the CPU 101 and the CPU 102, the FIFOs 103, 104, 105, and 106 do not always satisfy the necessary capacity. In the conventional inter-CPU communication system, data transfer from the CPU 101 to the FIFO 103 and data transfer from the FIFO 105 to the CPU 101 are performed by the first clock supplied from the CPU 101 side. Data transfer from the FIFO 104 to the CPU 102 and data transfer from the CPU 102 to the FIFO 106 are performed by the second clock supplied from the CPU 102 side. For this reason, depending on the capacity of the FIFO, underrun (data missing), overrun (FIFO data overflow), etc. may occur.

  Here, technologies related to data transmission (data transfer) will be introduced.

  Japanese Patent Laid-Open No. 8-149179 (Patent Document 1) describes a data communication control device. A data communication control device receives and demodulates first transmission data transmitted from a partner station and outputs corresponding reception data, a reception buffer memory for temporarily storing reception data, and a storage data amount in the reception buffer memory A buffer memory monitoring circuit for generating a warning signal when a predetermined first threshold value is exceeded, a clock generation circuit for generating a data synchronization clock, and a transmission buffer memory for temporarily storing transmission data A transmission circuit that modulates the output data of the transmission buffer memory into second transmission data and transmits it to the other station in synchronization with the clock, and each of the data between the own station and the other station in synchronization with the clock. Give and receive. The buffer memory monitoring circuit detects a memory empty state in which the amount of stored data becomes zero, and outputs a frequency signal when the frequency, which is the number of times this memory empty state is within a predetermined time, exceeds a predetermined second threshold value. An empty frequency detection circuit is provided. The clock generation circuit selectively generates a clock having first and second frequencies corresponding to a first data transmission speed at a normal time and a second data transmission speed lower than the first data transmission speed, respectively, and gives a warning. Clock frequency switching means for selectively switching the signal and the frequency signal to one of the second and first frequencies is provided. This prevents an overrun error in the reception buffer and improves data transmission efficiency.

  Japanese Patent Application Laid-Open No. 2001-212228 (Patent Document 2) describes a telephone terminal device. A telephone terminal device is a device that is connected between a personal computer (PC) and a telephone exchange network, and transmits and receives digital audio signals between the PC and the telephone exchange network. This telephone terminal device includes a USB interface with a USB (Universal Serial Bus) bus connected to a PC and a line interface circuit with a telephone exchange network, and connection with the PC is performed in an isochronous mode of the USB bus. As a result, the digital audio data is interrupted due to the clock difference between the PC and the telephone exchange network, or noise generated by truncating data that cannot be sent is removed.

  Japanese Patent Laid-Open No. 11-205408 (Patent Document 3) describes a digital signal transmission device. A digital signal transmission device includes a first device having a transmission / reception unit for transmitting / receiving a digital signal, a control unit for variably controlling a data transfer rate in the transmission / reception unit, and a bidirectional transmission / reception unit of the first device. A transmitting / receiving unit connected by a communication member, a storage unit for temporarily storing data received by the transmitting / receiving unit, a conversion unit for reading data from the storage unit and performing signal conversion, and each of these units Signal transmission is performed with a second device having a control unit that controls the above. In the digital signal transmission device, a reference clock signal generation unit that generates a reference clock signal for the conversion unit is provided in the second device. In the digital signal transmission device, the control unit of the second device monitors the usage status of the storage unit and sends a signal from the control unit to the control unit of the first device via the bidirectional communication member. The data transfer rate from the transmission / reception unit of the first device to the transmission / reception unit of the second device is variably controlled. As a result, a digital signal is transmitted without complicating the signal transmission path or causing signal deterioration.

  Japanese Patent Application Laid-Open No. 7-6130 (Patent Document 4) describes a method and apparatus for transferring data between two asynchronous apparatuses and matching the maximum data transfer rates of the apparatuses. Yes.

JP-A-8-149179 JP 2001-211228 A JP-A-11-205408 Japanese Patent Laid-Open No. 7-6130

  An object of the present invention is to provide an inter-CPU communication system that can reduce errors such as underrun and overrun when performing high-speed communication.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and the description of [Best Mode for Carrying Out the Invention]. It should not be used to interpret the technical scope of the invention described in “

The inter-CPU communication system of the present invention includes a first CPU (1), a second CPU (2), a first FIFO (3), a second FIFO (4), and a clock control circuit (10).
The first CPU (1) generates a first clock (7) and sequentially transmits first data in synchronization with the first clock (7).
The second CPU (2) generates a second clock (8).
The first FIFO (3) sequentially holds the first data from the first CPU (1), and in synchronization with the transfer clock (9), the first FIFO (3) stores the first data held by itself. Are output sequentially.
The second FIFO (4) sequentially holds the second data, and in synchronization with the second clock (8), the second CPU held by the second FIFO (4) as the third data sequentially. Output to (2).
The clock control circuit (10) is configured to transfer one of the first clock (7) from the first CPU (1) and the second clock (8) from the second CPU (2) to the transfer clock (9). To the first FIFO (3).

In the inter-CPU communication system of the present invention, the first FIFO (3) outputs to the clock control circuit (10) a first data amount (11) representing the amount of the first data that it sequentially holds. To do.
The second FIFO (4) outputs, to the clock control circuit (10), a second data amount (12) representing the amount of the second data that it sequentially holds.
The clock control circuit (10) determines the first clock (7) and the second clock (8) based on the comparison result between the first data amount (11) and the second data amount (12). Is output to the first FIFO (3) as the transfer clock (9).

  In the inter-CPU communication system of the present invention, the clock control circuit (10) includes a comparison result between the frequency (13) of the first clock (7) and the frequency (14) of the second clock (8); Based on the comparison result between the first data amount (11) and the second data amount (12), one of the first clock (7) and the second clock (8) is used as the transfer clock (9). To the first FIFO (3).

  In the inter-CPU communication system according to the present invention, the clock control circuit (10) is configured such that the frequency (13) of the first clock (7) is higher than the frequency (14) of the second clock (8), and the first data When the amount (11) is larger than the second data amount (12), the first clock (7) is output to the first FIFO (3) as the transfer clock (9) (S7-YES, S8, S10-). YES, S11).

  In the inter-CPU communication system according to the present invention, the clock control circuit (10) is configured such that the frequency (13) of the first clock (7) is equal to or lower than the frequency (14) of the second clock (8). When the data amount (11) is larger than the second data amount (12), the second clock (8) is output to the first FIFO (3) as the transfer clock (9) (S7-NO, S9, S10). -YES, S11).

  In the inter-CPU communication system according to the present invention, the clock control circuit (10) is configured such that the frequency (13) of the first clock (7) is higher than the frequency (14) of the second clock (8), and the first data When the amount (11) is less than or equal to the second data amount (12), the second clock (8) is output to the first FIFO (3) as the transfer clock (9) (S7-YES, S8, S10). -NO, S12).

  In the inter-CPU communication system according to the present invention, the clock control circuit (10) is configured such that the frequency (13) of the first clock (7) is equal to or lower than the frequency (14) of the second clock (8). When the data amount (11) is less than or equal to the second data amount (12), the first clock (7) is output as the transfer clock (9) to the first FIFO (3) (S7-NO, S9, S10-NO, S12).

  The inter-CPU communication system of the present invention is applied to a mobile phone.

  The inter-CPU communication system of the present invention is applied to a PDA (Personal Digital Assistant).

  The inter-CPU communication system of the present invention is applied to a PC (Personal Computer).

  As described above, in the inter-CPU communication system of the present invention, the clock control circuit determines the clock for data transfer from the transmission-side FIFO to the reception-side FIFO according to the data amount in each FIFO. Thereby, errors such as underrun and overrun when performing high-speed communication can be reduced.

  Hereinafter, an inter-CPU communication system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the configuration of the inter-CPU communication system of the present invention. The inter-CPU communication system of the present invention includes CPUs (Central Processing Units) 1 and 2, FIFOs (First In First Out) 3 and 4, and a clock control circuit 10.
The CPU 1 is connected to a FIFO 3 that is a FIFO on the transmission side. The CPU 2 is connected to a FIFO 4 that is a reception-side FIFO. Thereby, communication between CPUs is performed.
The clock control circuit 10 is connected to CPUs 1 and 2 and FIFOs 3 and 4.

The CPU 1 generates the first clock 7 and sequentially transmits the first data to the FIFO 3 in synchronization with the first clock 7. Further, the CPU 1 supplies the first clock 7 to the clock control circuit 10 and also supplies the first clock frequency information 13 indicating the frequency of the first clock 7 to the clock control circuit 10.
The CPU 2 generates a second clock 8. Further, the CPU 2 supplies the second clock 8 to the FIFO 4 and the clock control circuit 10, and supplies the second clock frequency information 14 indicating the frequency of the second clock 8 to the clock control circuit 10.
The FIFO 3 sequentially holds the first data from the CPU 1 and sequentially outputs the first data held by itself to the FIFO 4 as the second data in synchronization with the transfer clock 9 from the clock control circuit 10. The FIFO 3 outputs a first data amount 11 representing the amount of first data held by itself to the clock control circuit 10.
The FIFO 4 sequentially holds the second data from the FIFO 3 and sequentially outputs the second data held by itself to the CPU 2 as the third data in synchronization with the second clock 8 from the CPU 2. The FIFO 4 outputs a second data amount 12 representing the amount of second data held by itself to the clock control circuit 10.

  Based on the comparison result between the first clock frequency information 13 and the second clock frequency information 14 and the comparison result between the first data amount 11 and the second data amount 12, the clock control circuit 10 The second clock 8 is output to the FIFO 3 as the transfer clock 9 described above. The clock control circuit 10 will be described in detail.

  FIG. 3 is a flowchart showing the operation of the clock control circuit 10 of the inter-CPU communication system of the present invention. Here, it is assumed that the sizes of the FIFOs 3 and 4 are the same.

The clock control circuit 10 acquires the first data amount 11 from the FIFO 3 (step S1), and acquires the second data amount 12 from the FIFO 4 (step S2).
At the same time, the clock control circuit 10 receives the first clock 7 from the CPU 1 (step S3) and receives the second clock 8 from the CPU 2 (step S4).
At the same time, the clock control circuit 10 receives the first clock frequency information 13 from the CPU 1 (step S5), and receives the second clock frequency information 14 from the CPU 2 (step S6).

The clock control circuit 10 compares the first clock frequency information 13 and the second clock frequency information 14. That is, the frequency of the first clock 7 is compared with the frequency of the second clock 8 (step S7).
When the frequency of the first clock 7 is higher than the frequency of the second clock 8 (step S7—YES), the clock control circuit 10 recognizes the first clock 7 as the high frequency H_Clock and the second clock 8 as the low frequency L_Clock. (Step S8).
When the frequency of the first clock 7 is equal to or lower than the frequency of the second clock 8 (step S7-NO), the clock control circuit 10 recognizes the second clock 8 as the high frequency H_Clock and sets the first clock 7 as the low frequency L_Clock. (Step S9).

At the same time, the clock control circuit 10 compares the first data amount 11 and the second data amount 12. That is, the amount of the first data held in the FIFO 3 is compared with the amount of the second data held in the FIFO 4 (step S10).
When the first data amount 11 is larger than the second data amount 12 (step S10-YES), the clock control circuit 10 uses the high frequency H_Clock as the above-mentioned transfer clock 9 in order to accelerate the data transfer from the FIFO 3 to the FIFO 4, and to the FIFO 3 (Step S11), and the process returns to step S1.
When the first data amount 11 is equal to or less than the second data amount 12 (step S10—NO), the clock control circuit 10 outputs the low frequency L_Clock as the transfer clock 9 to the FIFO 3 (step S12), and then proceeds to step S1. Return.

Thereby, when the frequency of the first clock 7 is higher than the frequency of the second clock 8 and the first data amount 11 is larger than the second data amount 12, the clock control circuit 10 uses the first clock 7 as the transfer clock 9 described above. Is output to the FIFO 3 (steps S7-YES, S8, S10-YES, S11).
When the frequency of the first clock 7 is equal to or lower than the frequency of the second clock 8 and the first data amount 11 is greater than the second data amount 12, the clock control circuit 10 uses the second clock 8 as the transfer clock 9 and the FIFO 3 (Steps S7-NO, S9, S10-YES, S11).
When the frequency of the first clock 7 is higher than the frequency of the second clock 8 and the first data amount 11 is less than or equal to the second data amount 12, the clock control circuit 10 uses the second clock 8 as the transfer clock 9 and the FIFO 3 (Steps S7-YES, S8, S10-NO, S12).
When the frequency of the first clock 7 is equal to or lower than the frequency of the second clock 8 and the first data amount 11 is equal to or smaller than the second data amount 12, the clock control circuit 10 uses the first clock 7 as the transfer clock 9 described above. The data is output to the FIFO 3 (steps S7-NO, S9, S10-NO, S12).

  As described above, in the inter-CPU communication system according to the present invention, the clock control circuit 10 determines the clock for data transfer from the FIFO 3 on the transmission side to the FIFO 4 on the reception side according to the data amount in each of the FIFOs 3 and 4. ing. Thereby, errors such as underrun and overrun when performing high-speed communication can be reduced.

When the sending side (CPU1, FIFO3) stops data transfer with reference to the data amount 12 in the receiving side FIFO4, the CPU1 accumulates data in the inside (buffer or memory), and in the worst case, the data is discarded. Will do.
On the other hand, in the inter-CPU communication system according to the present invention, the transmission side (CPU 1, FIFO 3) does not refer to the data amount 12 in the reception side FIFO 4, but the clock control circuit 10 determines the data amount in the FIFOs 3, 4. Accordingly, clock control is performed to output one of the first clock 7 from the CPU 1 and the second clock 8 from the CPU 2 to the FIFO 3 as a transfer clock. For this reason, data transfer from the CPU 1 on the transmission side to the FIFO 3 is always performed at a constant interval by the first clock 7 and does not compress the inside (buffer or memory) of the CPU 1.

  In the inter-CPU communication system of the present invention, since the clock control circuit 10 performs the above-described clock control, the processing load when the CPUs 1 and 2 process data can be reduced.

  In the inter-CPU communication system of the present invention, when the sizes of the FIFO 3 and the FIFO 4 are different, the data amount corresponding to the difference between the FIFO 3 size and the FIFO 4 size is set as an offset (offset data amount). For example, when the size of the FIFO 4 is smaller than the size of the FIFO 3, as shown in FIG. 4, in step S10, the clock control circuit 10 adds the offset data amount to the second data amount 12, and then adds the first data The amount 11 and the second data amount 12 are compared. Thereby, in the communication system between CPUs of the present invention, even when the sizes of the FIFO 3 and the FIFO 4 are different, the above-described effects are exhibited.

The inter-CPU communication system of the present invention is applied to, for example, a computer provided with a communication device and a display device. Examples of the computer include a mobile phone, a PDA (Personal Digital Assistant), and a PC (Personal Computer). The PC includes a notebook PC.
For example, a communication CPU connected to the communication device is a first CPU, and a display CPU connected to the display device is a second CPU. In this case, the first CPU transfers data from the communication device to the second CPU via the first FIFO and the second FIFO. The second CPU displays the data on the display device.

FIG. 1 is a block diagram showing a configuration of a conventional inter-CPU communication system. FIG. 2 is a block diagram showing the configuration of the inter-CPU communication system of the present invention. FIG. 3 is a flowchart showing the operation of the clock control circuit 10 of the inter-CPU communication system of the present invention. FIG. 4 is a flowchart showing the operation of the clock control circuit 10 of the inter-CPU communication system of the present invention. (Other examples)

Explanation of symbols

1, 2 CPU
3, 4 FIFO
7, 8 clock 9 transfer clock 10 clock control circuit 11, 12 data amount 13, 14 clock frequency information 101, 102 CPU
103, 104, 105, 106 FIFO

Claims (10)

A first CPU for generating a first clock and transmitting first data in synchronization with the first clock;
A second CPU for generating a second clock;
A first FIFO that sequentially holds the first data from the first CPU and that sequentially outputs the first data held by itself as second data in synchronization with a transfer clock;
A second FIFO for sequentially holding the second data, and synchronizing the second data with the second clock and sequentially outputting the second data held by itself as third data to the second CPU;
An inter-CPU communication system comprising: a clock control circuit that outputs one of the first clock from the first CPU and the second clock from the second CPU as the transfer clock to the first FIFO. In the inter-CPU communication system according to claim 1,
The first FIFO outputs a first data amount representing the amount of the first data held by the first FIFO to the clock control circuit;
The second FIFO outputs a second data amount representing the amount of the second data that the second FIFO sequentially holds to the clock control circuit,
The clock control circuit is configured to output one of the first clock and the second clock to the first FIFO as the transfer clock based on a comparison result between the first data amount and the second data amount. Communications system. The inter-CPU communication system according to claim 2,
The clock control circuit, based on a comparison result between the frequency of the first clock and the frequency of the second clock, and a comparison result between the first data amount and the second data amount, An inter-CPU communication system that outputs one of the second clocks as the transfer clock to the first FIFO. In the inter-CPU communication system according to claim 3,
The clock control circuit includes:
An inter-CPU communication system that outputs the first clock as the transfer clock to the first FIFO when the frequency of the first clock is higher than the frequency of the second clock and the first data amount is larger than the second data amount. . In the inter-CPU communication system according to claim 3 or 4,
The clock control circuit includes:
Inter-CPU communication that outputs the second clock to the first FIFO as the transfer clock when the frequency of the first clock is less than or equal to the frequency of the second clock and the first data amount is greater than the second data amount system. In the inter-CPU communication system according to any one of claims 3 to 5,
The clock control circuit includes:
When the frequency of the first clock is higher than the frequency of the second clock and the first data amount is less than or equal to the second data amount, the inter-CPU communication that outputs the second clock to the first FIFO as the transfer clock system. In the inter-CPU communication system according to any one of claims 3 to 6,
The clock control circuit includes:
When the frequency of the first clock is less than or equal to the frequency of the second clock and the first data amount is less than or equal to the second data amount, the CPU outputs the first clock to the first FIFO as the transfer clock Communications system. A mobile phone to which the inter-CPU communication system according to claim 1 is applied. A PDA (Personal Digital Assistant) to which the inter-CPU communication system according to claim 1 is applied. A PC (Personal Computer) to which the inter-CPU communication system according to claim 1 is applied.

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