JP2006245150A - Semiconductor device for evaluation and its manufacturing method, and evaluation method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for evaluation which can more accurately evaluate a semiconductor device by measuring the operating condition of the semiconductor device during operation (driving), and also to provide a method of manufacturing the semiconductor device for evaluation and a method of evaluating the semiconductor device. <P>SOLUTION: Drain, source, and gate electrodes 3a, 4a, and 5 of an arbitrary semiconductor device formed on a semiconductor substrate 2 are formed, and an active region 2a wherein the carrier distribution is controlled is formed between these electrodes 3a, 4a, and 5. Then an insulation film 7 is formed for covering the electrodes 3a, 4a, and 5. An exposure surface 1a is formed wherein the active region 2a to be observed is exposed. In order to connect the electrodes 3a, 4a, and 5 to the outside, interconnection portions 3b, 4b, and 5a are formed in the insulation film 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for evaluation for elucidating the physical mechanism of the normal operation and defective operation of a semiconductor device having electrical characteristics such as amplification and switching by controlling the carrier density distribution, a method for producing the semiconductor device for evaluation, The present invention relates to a semiconductor device evaluation method.

  LSIs (Large Scale Integrated Circuits) are led by Intel and IBM, and their performance and functionality are being promoted, but their development costs are rapidly increasing year by year. Public and private research institutes developing next generation LSIs are searching for new manufacturing and evaluation technologies all over the world, and the current situation is that evaluation technologies do not follow the progress of manufacturing technologies.

  Conventionally, as shown in FIG. 10, when the cross section 51a of the semiconductor device 51 inside the LSI is exposed, wiring for driving the semiconductor device 51 cannot be left, and the semiconductor device 51 is turned off from the cross section 51a. Only static characteristics such as potential distribution and carrier density distribution can be analyzed and evaluated.

  Since the characteristic evaluation of the semiconductor device 51 through the cross section 51a is limited to a static state (OFF state), a two-dimensional potential distribution or a carrier density distribution measured using a probe microscope or the like is practical. There is no example of positive feedback in the manufacturing process of the semiconductor device 51.

  Therefore, elucidation of the mechanism of the normal operation (or defective operation) of the semiconductor device 51 relies on computer simulation using the current flowing through the semiconductor device 51 as an index. In this method, as shown in FIG. 11, in order to derive the electric field distribution inside the semiconductor device 51, it is necessary to assume a model such as a two-dimensional space charge distribution 53, and the difference between the model and the actual distribution is required. Therefore, high-precision characteristic prediction is almost impossible.

Therefore, Non-Patent Document 1 discloses a new method for manufacturing a special chip-like semiconductor device from which wiring can be taken out using a dedicated mask.
CY Nakakura et al .: REVIEW OF SCIENTIFIC INSTRUMENTS Vol.74, No.1 page 127-133 (2003)

  However, in the conventional method described in Non-Patent Document 1, it is not possible to drive a device having a cross section at an arbitrary location in an arbitrary LSI due to its manufacturing method, and high cost is required for manufacturing one semiconductor device. It becomes. In order to manufacture such a special chip, the entire process of manufacturing an LSI is required, and the cost thereof is insignificantly higher.

  In order to solve the above problems, an evaluation semiconductor device according to the present invention includes a semiconductor substrate, at least two electrodes of any semiconductor device provided on the semiconductor substrate, and the at least two electrodes in the semiconductor substrate. An active region in which the distribution state of carriers or charges formed between two electrodes is controlled, an insulating film covering the at least two electrodes, an exposed surface exposing the active region to be observed, and the at least two In order to connect the two electrodes to the outside, a wiring portion provided in each of the insulating films is provided.

  According to the above configuration, since the wiring portion for each electrode is formed in the insulating film, respectively, the wiring portion can be formed for each arbitrary electrode position, and a semiconductor device at any location in any LSI, For example, a field effect transistor (hereinafter referred to as FET) can be driven with its exposed surface exposed.

  Thus, unlike the semiconductor device described in Non-Patent Document 1, the above configuration does not require a new special cross-section (exposed surface) evaluation semiconductor device. Therefore, a semiconductor device manufactured by a normal LSI process is used. Direct evaluation is possible, leading to a significant reduction in the development cost of semiconductor devices. Therefore, the above configuration can reduce the LSI development cost, so it can revitalize the sluggish semiconductor industry in Japan and overseas, and can become a driving force for the second IT revolution by realizing and popularizing ultra-high performance and high-performance electronic computing units.

  In the semiconductor device for evaluation, the wiring portion may be formed in a tapered shape that narrows toward at least one of the at least two electrodes.

  According to the above configuration, since the wiring portion is formed in a tapered shape that becomes narrower toward the at least two electrodes, the area of the at least two electrodes is small, and the area of one end portion of the wiring portion connected thereto Even if it is small, the area of the other end of the wiring part can be increased, and the electrical connection between the wiring part and the outside can be stabilized.

  In the semiconductor device for evaluation, the wiring portion is preferably formed in a direction different from perpendicular to the plane of the surface of the semiconductor substrate toward at least one of the at least two electrodes.

  According to the above configuration, since the wiring portion is formed in a direction different from perpendicular to the plane of the semiconductor substrate surface toward at least one of the at least two electrodes, the wiring portions are arranged on the electrode side. Since it can be formed radially away from the base end portion toward the front end portion on the surface side of the insulating film, the area of the at least two electrodes is small, and the area of one end portion of the wiring portion connected to them is small. The area of the other end of the wiring part can be increased, and the electrical connection between the wiring part and the outside can be stabilized.

  In the semiconductor device for evaluation, the active region uses a field effect, and the at least two electrodes may be a source electrode, a drain electrode, and a gate electrode, respectively.

  In order to solve the above problems, a method for producing an evaluation semiconductor device according to the present invention includes a semiconductor substrate, at least two electrodes of an arbitrary semiconductor device provided on the semiconductor substrate, and the semiconductor substrate. In the method for producing an evaluation semiconductor device, comprising: an active region formed between the at least two electrodes, in which a carrier or charge distribution state is controlled; and an insulating film covering the at least two electrodes. In order to connect at least one of the electrodes to the outside, a contact hole is formed by a focused ion beam from the outside to the top of the electrode, the electrode is connected to the outside by a conductor passing through the contact hole, and The observation area in the active area is exposed.

  In order to solve the above-described problem, another method for manufacturing the semiconductor device for evaluation includes a semiconductor substrate, at least two electrodes of any semiconductor device provided on the semiconductor substrate, and the semiconductor substrate described above. In the method of manufacturing an evaluation semiconductor device having an active region formed between at least two electrodes, in which a carrier or charge distribution state is controlled, and an insulating film covering the at least two electrodes, in the active region, In order to expose the observation region and connect at least one of the at least two electrodes to the outside, a contact hole is formed by a focused ion beam from the outside to the top of the electrode, and the conductor passes through the contact hole. The electrode is connected to the outside by the above.

  In the method for manufacturing the semiconductor device for evaluation, it is desirable that the conductor passing through the contact hole is embedded by a chemical vapor deposition method using a focused ion beam.

  According to the above method, the evaluation semiconductor device uses a three-dimensional wiring formation method using a focused ion beam in which the wiring portion which is a bias line to which a voltage can be applied even when the exposed surface is exposed. It is provided. This wiring formation method can form a three-dimensional wiring on an LSI wafer three-dimensionally with a spatial resolution of about 100 nm. Unlike the semiconductor device described in Non-Patent Document 1, a new special section (exposed surface) is formed. There is no need to produce an evaluation semiconductor device having

  Therefore, the above method can directly evaluate a semiconductor device manufactured by a normal LSI process, leading to a significant reduction in device development cost. Reducing LSI development costs can revitalize the sluggish semiconductor industry at home and abroad, and become the driving force for the second IT revolution by realizing and spreading ultra-high performance and high-performance electronic computing units.

  The semiconductor device evaluation method according to the present invention uses the evaluation semiconductor device obtained by any one of the manufacturing methods described above to solve the above problems, and evaluates each electrode through the conductor. The semiconductor device is in a driving state, and the carrier density distribution in the active region of the exposed surface is measured under the driving state.

  In the semiconductor device evaluation method, the carrier density distribution is measured by scanning probe microscopy such as scanning capacitance microscopy or Kelvin force microscopy, scanning electron microscopy, measurement using an electron beam induced current, and It is preferable to use at least one selected from the measurement method group consisting of scanning ion microscopy.

  According to the above method, the semiconductor device at a specific location inside the LSI can be driven even when the exposed surface is exposed by using the three-dimensional wiring forming method using a focused ion beam by the manufacturing method according to the present invention. Since a new semiconductor device with a possible wiring portion (via) is used, it is possible to measure the carrier density distribution in the active region of the exposed surface under the driving state while driving the semiconductor device. Become.

  For this reason, unlike the case disclosed in Non-Patent Document 1, the above method does not require a new special chip that can be used to extract the wiring by using a dedicated mask, so that it is manufactured by a normal LSI process. This makes it possible to directly evaluate the semiconductor device, which leads to a significant reduction in the development cost of the semiconductor device. Reducing LSI development costs can revitalize the sluggish semiconductor industry at home and abroad, and become the driving force for the second IT revolution by realizing and spreading ultra-high performance and high-performance electronic computing units.

  As described above, an evaluation semiconductor device according to the present invention includes at least two electrodes of an arbitrary semiconductor device provided on a semiconductor substrate, and carriers formed between the at least two electrodes in the semiconductor substrate. Alternatively, an active region in which the distribution state of charge is controlled, an insulating film covering the at least two electrodes, an exposed surface exposing the active region to be observed, and the at least two electrodes are connected to the outside. A wiring portion provided in the insulating film, and the wiring portion is formed after the insulating film is deposited.

  Therefore, the above configuration has a new special cross section (exposed surface), unlike the semiconductor device described in Non-Patent Document 1, because the wiring portions for the respective electrodes are formed after the deposition of the insulating film. Since there is no need to produce an evaluation semiconductor device, it is possible to directly evaluate a semiconductor device produced by a normal LSI process, leading to a significant reduction in the development cost of the semiconductor device.

  As a result, the above configuration can reduce LSI development costs, so it can energize the sluggish semiconductor industry in Japan and overseas, and can become the driving force for the second IT revolution by realizing and popularizing ultra-high performance, high-performance electronic computing units. There is an effect.

  As described above, in the method of manufacturing the semiconductor device for evaluation according to the present invention, in order to connect at least one of the at least two electrodes to the outside, the contact opening is formed from the outside to the top of the electrode by a focused ion beam. In this method, the electrode is connected to the outside by a conductor passing through the contact hole, and the observation region in the active region is exposed.

  Therefore, unlike the semiconductor device described in Non-Patent Document 1, the above method does not require a new special cross-section (exposed surface) evaluation device, so that a semiconductor device manufactured by a normal LSI process is directly used. It becomes possible to evaluate, and it becomes possible to significantly reduce the device development cost.

  Therefore, the above method has the effect that the reduction of LSI development cost can energize the semiconductor industry that is stagnating at home and abroad, and can become the driving force of the second IT revolution by the realization and spread of ultra-high performance, high-performance electronic computing units. Play.

  As described above, the semiconductor device evaluation method according to the present invention uses the evaluation semiconductor device obtained by any one of the manufacturing methods described above, and the evaluation semiconductor device is driven by each electrode through the conductor. And the carrier density distribution in the active region of the exposed surface is measured under the driving state.

  Therefore, the above method uses a three-dimensional wiring forming method using a focused ion beam by the manufacturing method according to the present invention to drive a semiconductor device at a specific location inside the LSI even when the exposed surface is exposed. Because a new semiconductor device with a wiring section (via) that can be used is used, the carrier density distribution in the active region of the exposed surface can be measured under the driving state while driving the semiconductor device. It becomes.

  For this reason, unlike the case disclosed in Non-Patent Document 1, the above method does not require a new special chip that can be used to extract the wiring by using a dedicated mask, so that it is manufactured by a normal LSI process. This makes it possible to directly evaluate the semiconductor device, which leads to a significant reduction in the development cost of the semiconductor device. Reducing LSI development costs will energize the semiconductor industry, which has been sluggish both in Japan and overseas, and will have the effect of becoming the driving force for the second IT revolution through the realization and spread of ultra-high performance, high-performance electronic computing units.

  Each embodiment of the present invention will be described below with reference to FIGS. In other words, the semiconductor device for evaluation according to the present invention includes the FET 1 shown in FIG. 2, and exhibits electrical characteristics such as amplification and switching by controlling the carrier density distribution or charge distribution state by applying a voltage. The present invention can be suitably used for, for example, a bipolar transistor instead of the FET. In FIG. 2, one FET 1 is illustrated, but a large number of FETs 1 may be simultaneously formed inside the LSI wafer by using a photolithography method.

The FET 1 has a p-type well (boron: 1.0 × 10 ¹⁷ cm ⁻³ ) 2 a formed on an upper portion of a semiconductor substrate 2 such as silicon, and drain regions (n-type) 3, respectively, at both ends of the upper portion. A source region (n-type) 4 is formed.

A gate electrode (n ⁺ poly-Si) 5 is provided on the p-type well 2 a between the drain region 3 and the source region 4 with a gate insulating layer (metal oxide, thickness: 10 nm) 6 interposed therebetween. ing. Therefore, a region of the p-type well 2a sandwiched between the drain region 3 and the source region 4 and facing the gate electrode 5 is an active region (also referred to as a carrier region in the FET).

  In such an FET 1, the carrier density distribution in the active region is controlled by the electric field generated by the voltage applied to the gate electrode 5, and the current flowing between the drain region 3 and the source region 4 is controlled. Such electrical characteristics can be demonstrated.

  Further, as shown in FIG. 1A, a drain electrode 3a and a source electrode 4a are attached to the drain region 3 and the source region 4, respectively. An insulating film 7 is formed on the gate electrode 5, the drain electrode 3a, and the source electrode 4a so as to cover them. Examples of the material of the insulating film 7 include metal oxides such as alumina, nitrides such as silicon nitride, glass such as multicomponent glass, and synthetic resins such as acrylic resins.

  Then, after the insulating film 7 is formed, the insulating film 7 penetrates the insulating film 7 in the film thickness direction in order to connect the gate electrode 5, the drain electrode 3a and the source electrode 4a to the outside. The wiring portions 5a, 3b, and 4b provided respectively in FIG. 6 are formed of tungsten (W) as a conductor.

  The wiring portions 5a, 3b, and 4b are preferably formed in a tapered shape that becomes thinner toward the gate electrode 5, the drain electrode 3a, and the source electrode 4a. In the figure, each of the wiring portions 5a, 3b, and 4b is not a taper shape but is simply shown as a straight tube.

  The wiring portions 5a, 3b, and 4b are formed in directions different from, or inclined to, the plane of the surface of the semiconductor substrate 2 toward the gate electrode 5, the drain electrode 3a, and the source electrode 4a. It is desirable that Furthermore, it is preferable that the wiring portions 5a, 3b, and 4b are provided in a radial pattern so as to be sequentially separated from each electrode side toward the surface side of the insulating film 7 when formed at an inclination.

  On the insulating film 7, pad portions 5b, 3c, and 4c, which are electrically connected to the wiring portions 5a, 3b, and 4b, are provided for connection to the outside. . The pad portions 5b, 3c, and 4c are formed on the insulating film 7 at positions separated from the exposed surfaces described later with respect to the ends of the wiring portions 5a, 3b, and 4b. It is preferable for ensuring the connection.

  Further, in order to expose the active region at an arbitrary position to be observed, as shown in FIG. 3A, the FET 1 is diced at a position including the arbitrary position and crossing the gate electrode 5. The cleaved surface is polished and smoothed to form an exposed surface 1a that is a cross section.

Each of the wiring portions 5a, 3b, and 4b as described above is formed by a focused ion beam (hereinafter referred to as FIB) method as a manufacturing method thereof. In the FIB method, ions, for example, gallium ions (Ga ⁺ ) are focused by an electromagnetic force, and an ion beam is irradiated onto the object to be etched, in this embodiment, the insulating film 7 from above, and the irradiation position is without a mask. The contact opening 4d having a width of about several hundreds of nanometers and a depth of about 1 μm for the wiring portion 4b can be formed in a straight shape along the traveling direction of the ion beam. In this way, the contact holes are similarly formed in the other wiring portions 5a and 3b.

  Since the ion beam can be focused to a diameter of 0.1 μm, the contact opening 4d having the above dimensions can be accurately formed. In the FIB etching, the diameter of the ion beam is approximately the same as the diameter of the ion beam at the tip of the ion beam. However, the ion beam is slightly expanded at the base of the etching due to the slight spread of the ion beam. Therefore, the contact opening obtained by the ion beam has a tapered shape in which the area in the direction orthogonal to the traveling direction of the ion beam is sequentially reduced toward the corresponding electrode. can do.

  In the FIB etching, the wiring portions 5a, 3b, and 4b described above are different from perpendicular to the plane of the surface of the semiconductor substrate 2 toward the gate electrode 5, the drain electrode 3a, and the source electrode 4a. It is possible to facilitate and simplify forming each in a direction, that is, an inclination.

  Furthermore, in the FIB etching, the semiconductor substrate 2 is tilted or the ion beam is tilted, so that conduction to the electrodes that do not require connection is avoided even for other electrodes that do not require connection. However, the wiring portion can be reliably formed obliquely from the side.

  Thus, when performing the etching by the FIB method, the contact hole 4d is observed with a scanning ion microscope or a scanning electron microscope, and the ion beam is etched on the insulating film 7 so as to be formed on the upper portion of the source electrode 4a. When it reaches, since the amount of secondary electrons to be reflected changes with respect to the upper insulating film (passivation layer) 7, it is a through-hole in the vertical direction due to a change in luminance of the scanning ion microscope image or the scanning electron microscope image. The depth of the contact opening 4d can be detected and controlled.

Subsequently, in order to fill the contact hole 4d with tungsten as a conductor, while maintaining the ion beam, the gas of the organometallic compound, in this embodiment, hexacarbonyl tungsten (W (CO) ₆ ) Gas is introduced into the contact hole 4d. Thus, when the gas comes into contact with the ion beam, metallic tungsten is deposited by the reaction, and is deposited and filled in the contact opening 4d.

Other examples of the conductor other than tungsten include carbon and platinum. When these are used, phenanthrene (C ₁₄ H ₁₀ ) and nonine are used as their organometallic compounds, respectively. Platinum (Pt ₉ H ₁₆ ) is mentioned.

  Below, the evaluation method of FET1 as an evaluation semiconductor device which formed each wiring part 5a, 3b, 4b which is three-dimensional wiring using the said manufacturing method, ie, FIB-CVD method, is demonstrated. In the above evaluation method, the two-dimensional carrier density distribution was observed using SCM (Scanning Capacitance Microscopy) while the FET 1 was driven.

  First, as shown in FIG. 3, a specific FET 1 having an exposed surface (cross section) 1a is formed by bonding the pad portions 5b, 3c, and 4c described above and external wiring by bonding or conductive resin. Thus, external wiring, which is a bias line to which a voltage can be applied from the outside, the pad portions 5b, 3c, and 4c and the wiring portions 5a, 3b, and 4b can be manufactured (FIGS. 1A and 1C). See also)).

  Thereafter, SCM observation was performed using the FET 1 as a sample. The measurement system is shown in FIGS. Vi + Vaccos ωt (i = g, d, s) obtained by superimposing an AC voltage (Vaccos ωt) on the gate, drain, and source voltages (Vg, Vd, Vs) was applied to each electrode. The probe (cantilever) is connected to the ground. In this case, the potential difference between the electrodes of the element corresponds to the difference between Vg, Vd, and Vs, and no alternating current is superimposed.

  On the other hand, since Vg, Vd, and Vs are added with the two-dimensional potential Vdc and Vaccosωt formed inside the FET 1 between the probe and the FET 1, SCM measurement can be performed.

  In the SCM measurement, a dimension 3000 probe microscope manufactured by Di Co., and the cantilever was a SI cantilever of a rhodium-coated probe, SI-DF3-Rh-spring constant 2.3 N / m, and a resonance frequency of 30 KHz (manufactured by seiko instruments). An AC electric field having a frequency of 1 GHz was applied between the probe and the FET 1, and a modulation voltage having a frequency of 40 KHz, Vac = 6 Vpp, and Vdc = 0 V was superimposed thereon. The measurement was performed in the atmosphere.

  As an evaluation result by the above measurement, FIG. 6 shows Id-Vg characteristics (measurement points: A, B, C) and (Vd, Vg) = (1, −1), (2.0, 4.8) at Vd = 1V. ) Current value is shown. The SCM measurement results corresponding to each (Id, Vg) are shown in FIGS.

  In the above evaluation results, as Vg increased, Id increased and the device turned on, and it was confirmed that the FET 1 as a semiconductor device wired by FIB-CVD was driven. 7A to 7D show SCM images corresponding to the coordinates (Vg, Vd, Id) of the current value measurement points A, B, C, D shown in FIG. 6 in the same order. .

  Next, how to add contrast in each SCM image will be described. First, since the MOSFET has steep step junctions in the source region and the drain region, the SCM signal has a maximum value of different polarity before and after the junction. In order to clearly indicate the maximum and minimum values, all the SCM images in FIGS. 7A to 7D use contour plots that subdivide the signal level near the junction and emphasize the steepness of the signal. The white band-like contrasts at the source / drain edges from FIG. 7B to FIG. 7D indicate the maximum values of the signals near the depletion layer.

  Subsequently, the contrast in the FET 1 during operation (driving) will be described. First, it is shown that the contrast intensity differs between the source region and the drain region. The origin of the SCM signal in the cross section of the FET 1 in operation can be explained qualitatively as follows. The signal intensity of SCM differs in the high concentration implantation regions in the source and drain. The signal detected by the SCM is a differential value of the capacitance-voltage curve, and dC / dV (V = Vs) and dC / dV (V = Vd) are respectively obtained in the high concentration implantation regions of the source region and the drain region. For detection, the signal intensity is different even at the same impurity concentration as seen in FIGS. 7 (a) to 7 (d).

  Next, the meaning of the contrast near the junction will be described. Further, the contrast of the SCM at the pn junction is different between forward bias application and reverse bias application. When forward bias is applied, carriers are supplied from both sides of p and n to the MOS capacitor formed by the probe-FET 1 even in the vicinity of the metallurgical junction position, so that a strong capacitance modulation signal is detected also in the vicinity of the junction position.

  On the other hand, when the reverse bias is applied, the depletion layer spreads to the well on the low concentration side, but the carrier density is remarkably reduced in the vicinity of the depletion region, so that the SCM signal gradually decreases from the high concentration region to the low concentration region. That is, in the FET 1 in operation, the contrast of the drain region shows a gradual signal change toward the well, and in the source region, a sharp signal change is shown at the junction. From FIG. 7A to FIG. 7D, it can be seen that SCM shows a strong signal up to the lower end of the depletion layer in the source region, and shows a gradual signal change in the substrate direction in the drain region.

  In the channel region, capacitance measurement is performed on a depletion region induced by an electric field applied to the gate by a modulation electric field perpendicular to the electric field. When the depletion layer expands in the substrate direction due to the gate voltage, the signal strength of the SCM decreases from the substrate to the gate oxide film, similarly to the state in which a reverse bias is applied to the pn junction.

  From FIG. 7A to FIG. 7D, it can be seen that the depletion region expands in the direction of the semiconductor substrate as the gate voltage is applied.

  Next, the asymmetric structure of the measurement data will be described. A steep potential distribution exists between the source and gate and between the drain and gate, and the depletion layer is different from the one-dimensional analysis model. Expand in dimension. When the state is changed from FIG. 7A to FIG. 7B, the asymmetry of the depletion region between the source and the drain increases. Further, when changing from FIG. 7B to FIG. 7C, the depletion region of the source and the depletion region of the drain begin to expand under the gate oxide film, and in FIG. 7C and FIG. And the depletion region extends in the direction of the substrate across the source, drain, and gate.

  From the above, it can be seen that in the linear region where the FET 1 changes from the OFF state to the ON state, the change in the carrier density distribution of the FET 1 which expands two-dimensionally can be directly observed.

  In conclusion, the above evaluation method succeeded in operating the MOS type FET 1 in the LSI wafer with the exposed cross section by using the FIB-CVD wiring method. Furthermore, it was found that the FET 1 can be evaluated by measuring the change in the two-dimensional carrier density distribution using SCM on the exposed surface (cross section) of the driven FET 1. Further, other measurement examples related to the evaluation method are shown in FIGS. 8 and 9A to 9D.

  As described above, in the present invention, since the FIB etching and the FIB-CVD method are used as a method for driving the FET 1 with an arbitrary cross-section exposure, the FET 1 with the cross-section exposure is not dependent on the orientation of the cleavage plane of the LSI FET 1. At the same time, the two-dimensional carrier density distribution in the operating state of the FET 1 can be measured through the exposed surface of the cross section by a probe microscope such as SCM or an electron microscope.

  In the above embodiment, the carrier density distribution in the active region is measured using the SCM. However, the present invention is not particularly limited to the above, and scanning probe microscopy, Kelvin force microscopy, At least one selected from a scanning electron microscopy, a measurement method using an electron beam induced current, and a measurement method group consisting of a scanning ion microscope can be used.

  By the way, in the next-generation semiconductor device, since the small amount of three-dimensional information (potential distribution, carrier density distribution, etc.) inside the device in the ON state is a major factor in the rapid development cost, It is expected that the development of next-generation semiconductor devices will be highly efficient and cost-effective, and the performance and functionality of various electronic computing units will be promoted.

  Since the semiconductor device for evaluation of the present invention, the method for producing the semiconductor device for evaluation, and the method for evaluating the semiconductor device can visualize and measure the carrier density distribution of the semiconductor device during operation (driving), the normal operation of the semiconductor device, Since the physical mechanism of defective operation can be more reliably evaluated and elucidated, it can be suitably used in the semiconductor manufacturing field.

1 shows an FET as a semiconductor device for evaluation of the present invention, (a) is a perspective view, (b) is a cross-sectional view, and (c) is a plan view. It is principal part sectional drawing which shows the basic composition of the said FET. (A)-(c) is the following process drawing which shows the preparation methods of the semiconductor device for evaluation of this invention. It is a block diagram of SCM as an example of the measuring method used for the evaluation method of the semiconductor device of this invention. It is a perspective view when the SCM is applied to the semiconductor device for evaluation. It is a graph of an example which shows that the said semiconductor device for an evaluation is operating by applying a drain voltage and a gate voltage to the said semiconductor device for an evaluation while changing them. (A)-(d) is drawing substitute photograph which shows the SCM image respectively corresponding to each voltage point (AD) shown in FIG. It is a graph of the other example which shows that the said semiconductor device for evaluation is operating by changing and applying the drain voltage and the gate voltage with respect to the said semiconductor device for evaluation. (A)-(d) is drawing substitute photograph which shows the SCM image respectively corresponding to each voltage point (AD) shown in FIG. It is a perspective view of FET which has the conventional exposed surface. It is a schematic sectional drawing which shows the operation | movement concept in the said conventional FET.

Explanation of symbols

2 Semiconductor substrate 2a Active region 3a Drain electrode 3b Wiring part 4a Source electrode 4b Wiring part 5 Gate electrode 5a Wiring part 7 Insulating film

Claims (9)

A semiconductor substrate;
At least two electrodes of any semiconductor device provided on the semiconductor substrate;
An active region in which the distribution state of carriers or charges formed between the at least two electrodes in the semiconductor substrate is controlled;
An insulating film covering the at least two electrodes;
An exposed surface that exposes the active area to be observed;
An evaluation semiconductor device comprising: a wiring portion provided in each of the insulating films to connect the at least two electrodes to the outside.   2. The semiconductor device for evaluation according to claim 1, wherein the wiring portion is formed in a tapered shape that narrows toward at least one of the at least two electrodes.   3. The evaluation according to claim 1, wherein the wiring portion is formed in a direction different from perpendicular to a plane of the surface of the semiconductor substrate toward at least one of the at least two electrodes. For semiconductor devices.   4. The active region according to claim 1, wherein the active region uses a field effect, and the at least two electrodes are a source electrode, a drain electrode, and a gate electrode, respectively. Semiconductor device for evaluation. A semiconductor substrate;
At least two electrodes of any semiconductor device provided on the semiconductor substrate;
An active region in which the distribution state of carriers or charges formed between the at least two electrodes in the semiconductor substrate is controlled;
In the method for producing an evaluation semiconductor device having an insulating film covering the at least two electrodes,
In order to connect at least one of the at least two electrodes to the outside, a contact hole is formed from the outside to the top of the electrode by a focused ion beam,
The electrode is connected to the outside by a conductor passing through the contact opening,
A method for producing an evaluation semiconductor device, wherein an observation region in the active region is exposed. A semiconductor substrate;
At least two electrodes of any semiconductor device provided on the semiconductor substrate;
An active region in which the distribution state of carriers or charges formed between the at least two electrodes in the semiconductor substrate is controlled;
In the method for producing an evaluation semiconductor device having an insulating film covering the at least two electrodes,
Exposing the observation area in the active area,
In order to connect at least one of the at least two electrodes to the outside, a contact hole is formed from the outside to the top of the electrode by a focused ion beam,
A method for producing an evaluation semiconductor device, wherein the electrode is connected to the outside by a conductor passing through the contact opening.   7. The method of manufacturing a semiconductor device for evaluation according to claim 5, wherein the conductor through the contact hole is embedded by a chemical vapor deposition method using a focused ion beam. Using the semiconductor device for evaluation obtained by the production method according to any one of claims 5 to 7,
The semiconductor device for evaluation is driven by each electrode via the conductor,
A method for evaluating a semiconductor device, comprising: measuring a carrier density distribution in an active region of the exposed surface under the driving state.   The carrier density distribution is measured by scanning probe microscopy such as scanning capacitance microscopy and Kelvin force microscopy, scanning electron microscopy, measurement using electron beam induced current, and scanning ion microscopy. 9. The method for evaluating a semiconductor device according to claim 8, wherein at least one selected from a legal group is used.