JP2006245070A - Circuit apparatus - Google Patents

Circuit apparatus Download PDF

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Publication number
JP2006245070A
JP2006245070A JP2005055077A JP2005055077A JP2006245070A JP 2006245070 A JP2006245070 A JP 2006245070A JP 2005055077 A JP2005055077 A JP 2005055077A JP 2005055077 A JP2005055077 A JP 2005055077A JP 2006245070 A JP2006245070 A JP 2006245070A
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Prior art keywords
circuit
solder
wiring
layer
circuit element
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Inventor
Ryosuke Usui
良輔 臼井
Hideki Mizuhara
秀樹 水原
Yasunori Inoue
恭典 井上
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2005055077A priority Critical patent/JP2006245070A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To improve the heat-resistance reliability of a circuit apparatus which carries a circuit element in a circuit substrate. <P>SOLUTION: The circuit apparatus includes a multilayer wiring structure 500 in which an interlayer insulating film 405 and a plurality of wiring layers each consisting of wiring 407 are laminated, and circuit elements 410a and 410b formed in the front surface. The circuit element 410a is fixed by an adhesion layer 430a, such as a conductive paste, etc., and conducted to the wiring 407 by gold wiring bonding 412. The circuit element 410b is fixed by a solder material 430b having the three-layer structure of an Ni alloy nucleus, an Ni solder plating layer, and an Sn-Sb-Bi solder layer, and further, connected electrically with the wiring 407 through the solder material 430b. A solder ball 420 is formed at the rear surface of a multilayer wiring structure 500. The circuit elements 410a and 410b have a structure by which sealing is performed with a sealing resin 415. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板にＩＣチップ（回路素子）などを搭載した回路装置に関するものである。   The present invention relates to a circuit device in which an IC chip (circuit element) or the like is mounted on a circuit board.

携帯電話、ＰＤＡ、ＤＶＣ、ＤＳＣといったポータブルエレクトロニクス機器の高機能化が加速するなか、こうした製品が市場で受け入れられるためには小型・軽量化が必須となっており、その実現のために高集積のシステムＬＳＩが求められている。一方、これらのエレクトロニクス機器に対しては、より使い易く便利なものが求められており、機器に使用されるＬＳＩに対し、高機能化、高性能化が要求されている。このため、ＬＳＩチップの高集積化にともないそのＩ／Ｏ数が増大する一方でパッケージ自体の小型化要求も強く、これらを両立させるために、半導体部品の高密度な基板実装に適合した半導体パッケージの開発が強く求められている。こうした要求に対応するため、ＣＳＰ（Chip Size Package）と呼ばれるパッケージ技術が種々開発されている。   As portable electronic devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are essential for their acceptance in the market. There is a need for a system LSI. On the other hand, these electronic devices are required to be easier to use and convenient, and higher functionality and higher performance are required for LSIs used in the devices. For this reason, as the number of I / Os increases with higher integration of LSI chips, there is a strong demand for miniaturization of the package itself. In order to achieve both of these, a semiconductor package suitable for high-density board mounting of semiconductor components Development is strongly demanded. In order to meet such demands, various package technologies called CSP (Chip Size Package) have been developed.

こうしたパッケージの例として、ＢＧＡ（Ball Grid Array）が知られている。ＢＧＡは、パッケージ用基板の上に半導体チップを実装し、それを樹脂モールディングした後、反対側の面に外部端子としてハンダボールをエリア状に形成したものである。ＢＧＡでは、実装エリアが面で達成されるので、パッケージを比較的容易に小型化することができる。また、回路基板側でも狭ピッチ対応とする必要がなく、高精度な実装技術も不要となるので、ＢＧＡを用いると、パッケージコストが多少高い場合でもトータルな実装コストとしては低減することが可能となる。   As an example of such a package, BGA (Ball Grid Array) is known. In the BGA, a semiconductor chip is mounted on a package substrate, resin-molded, and then solder balls are formed in an area as external terminals on the opposite surface. In BGA, since the mounting area is achieved in terms of surface, the package can be reduced in size relatively easily. In addition, it is not necessary to support narrow pitches on the circuit board side, and high-precision mounting technology is not required. Therefore, if BGA is used, the total mounting cost can be reduced even if the package cost is somewhat high. Become.

ＢＧＡ（回路装置）の概略構成として、図１にＩＳＢ（Integrated System in Board；登録商標）の一例を示す。ＩＳＢとは、半導体ベアチップを中心とする電子回路のパッケージングにおいて、銅による配線パターンを持ちながら回路部品を支持するためのコア（基材）を使用しない独自のコアレスシステム・イン・パッケージである。特許文献１には、こうしたシステム・イン・パッケージが記載されている。   As a schematic configuration of a BGA (circuit device), FIG. 1 shows an example of an ISB (Integrated System in Board; registered trademark). ISB is an original coreless system-in-package that does not use a core (base material) for supporting circuit components while having a wiring pattern made of copper in packaging of electronic circuits centering on semiconductor bare chips. Patent Document 1 describes such a system-in-package.

図１ではＩＳＢの全体構造をわかりやすくするため、単一の配線層のみ示しているが、実際には、複数の配線層が積層した構造となっている。このＩＳＢでは、ＬＳＩベアチップ２０１、Ｔｒベアチップ２０２、及びチップＣＲ２０３が銅パターン２０５からなる配線により結線された構造となっている。ＬＳＩベアチップ２０１は、引き出し電極や配線に対し、金線ボンディング２０４により導通されている。また、チップＣＲ２０３は、はんだ等のロウ材からなる接着部材２０９により銅パターン２０５上に固定され、接着部材２０９を介して銅パターン２０５と導通する構造となっている。ＬＳＩベアチップ２０１の直下には、導電性ペースト２０６が設けられ、これを介してＩＳＢがプリント配線基板に実装される。ＩＳＢ全体はエポキシ樹脂などからなる樹脂パッケージ２０７により封止された構造となっている。
特開２００２−１１０７１７号公報 In FIG. 1, only a single wiring layer is shown for easy understanding of the entire structure of the ISB. However, in reality, a structure in which a plurality of wiring layers are stacked is shown. This ISB has a structure in which an LSI bare chip 201, a Tr bare chip 202, and a chip CR 203 are connected by a wiring made of a copper pattern 205. The LSI bare chip 201 is electrically connected to the extraction electrode and wiring by gold wire bonding 204. The chip CR 203 is fixed on the copper pattern 205 by an adhesive member 209 made of a brazing material such as solder, and has a structure that is electrically connected to the copper pattern 205 through the adhesive member 209. A conductive paste 206 is provided immediately below the LSI bare chip 201, and the ISB is mounted on the printed wiring board via the conductive paste 206. The entire ISB has a structure sealed with a resin package 207 made of an epoxy resin or the like.
JP 2002-110717 A

しかしながら、ＢＧＡ２００をプリント配線基板に実装する際（具体的には、はんだボール２０８をプリント配線基板上の電極と接続固定する際）に加わる熱処理によって、ＢＧＡ２００内のはんだ接着部材２０９が体積膨張し、ＢＧＡ２００内で剥離の起点となることがあるため、ＢＧＡ２００を実装したプリント配線基板の信頼性が劣化する問題がある。   However, when the BGA 200 is mounted on the printed wiring board (specifically, when the solder balls 208 are connected and fixed to the electrodes on the printed wiring board), the solder bonding member 209 in the BGA 200 expands in volume, Since it may become a starting point of peeling in the BGA 200, there is a problem that the reliability of the printed wiring board on which the BGA 200 is mounted is deteriorated.

さらに、ＢＧＡ２００の製造工程において、はんだ等のロウ材からなる接着部材２０９を設けた後にはんだボール２０８を設ける場合には、はんだボール２０８を形成する際に加わる熱処理によって、ＢＧＡ２００内のはんだ接着部材２０９が体積膨張し、ＢＧＡ２００内で剥離の起点となったりすることがあるため、ＢＧＡ２００の信頼性が著しく劣化する問題がある。   Further, in the manufacturing process of the BGA 200, when the solder ball 208 is provided after the adhesive member 209 made of solder or the like is provided, the solder adhesive member 209 in the BGA 200 is subjected to heat treatment applied when the solder ball 208 is formed. May expand and may become a starting point of peeling in the BGA 200, so that the reliability of the BGA 200 is remarkably deteriorated.

本発明は、上記事情に鑑みなされたものであって、回路基板に回路素子を搭載した回路装置の耐熱信頼性を向上させることを目的とする。   The present invention has been made in view of the above circumstances, and an object thereof is to improve the heat resistance reliability of a circuit device in which a circuit element is mounted on a circuit board.

上記課題を解決するために、本発明のある態様の回路装置は、回路基板と、回路基板の一方の面に搭載された回路素子と、回路基板に、回路素子を固定する第１接続部材と、回路基板の他方の面に設けられた第２接続部材と、を備え、第１接続部材は、熱収縮性を有するＮｉ合金を核とした接続部材であることを特徴とする。   In order to solve the above problems, a circuit device according to an aspect of the present invention includes a circuit board, a circuit element mounted on one surface of the circuit board, and a first connection member that fixes the circuit element to the circuit board. And a second connecting member provided on the other surface of the circuit board, wherein the first connecting member is a connecting member having a heat shrinkable Ni alloy as a core.

この態様によると、回路装置をプリント実装基板上に実装する際に加わる熱処理によって発生する回路基板と回路素子との剥離による断線や回路素子の位置ずれを抑制することができる。このため、回路装置の耐熱信頼性が向上する。これは、第１接着部材が加わる熱処理によって熱収縮する機能を有しているので、従来の接続部材を用いた場合に発生する体積膨張に起因した応力負荷が抑制されるためである。   According to this aspect, it is possible to suppress disconnection and displacement of the circuit element due to separation between the circuit board and the circuit element, which are generated by heat treatment applied when the circuit device is mounted on the printed mounting board. For this reason, the heat resistance reliability of the circuit device is improved. This is because, since the first adhesive member has a function of being thermally contracted by the heat treatment applied, the stress load due to the volume expansion generated when the conventional connecting member is used is suppressed.

また別の態様によると、第１接続部材は、Ｎｉ合金核、Ｎｉめっき層、及びＳｎを主体とするはんだ層の３層構造を有するはんだ材であることが好ましい。このようにすることにより、Ｎｉめっき層がＮｉ合金核とＳｎを主体とするはんだ層とが熱混合することがなくなり、Ｎｉ合金核の熱収縮性を効果的に機能させるはんだ材とすることができる。この結果、熱処理によって発生する回路基板と回路素子との剥離による断線や回路素子の位置ずれをより効果的に抑制することができる。   According to another aspect, the first connection member is preferably a solder material having a three-layer structure of a Ni alloy nucleus, a Ni plating layer, and a solder layer mainly composed of Sn. By doing so, the Ni plating layer does not thermally mix the Ni alloy core and the solder layer mainly composed of Sn, and a solder material that effectively functions the heat shrinkability of the Ni alloy core can be obtained. it can. As a result, it is possible to more effectively suppress disconnection due to peeling between the circuit board and the circuit element generated by the heat treatment and displacement of the circuit element.

本発明の別の態様の回路装置は、回路素子と第１接続部材は、樹脂で覆われていることを特徴とする。このようにすることにより、回路装置を実装する際に加わる熱処理によって発生する樹脂の剥離欠陥やクラック発生も抑制することができる。   The circuit device according to another aspect of the present invention is characterized in that the circuit element and the first connecting member are covered with a resin. By doing in this way, the resin peeling defect and the crack which generate | occur | produce by the heat processing added when mounting a circuit apparatus can also be suppressed.

さらに別の態様によると、第２接続部材は、熱膨張性を有するはんだ材であって、第１接続部材を設けた後に第２接続部材を設けることを特徴とする。このようにすることにより、第２接続部材を形成する際に加わる熱処理によって発生する回路基板と回路素子との剥離による断線や回路素子の位置ずれを抑制することができる。   According to still another aspect, the second connecting member is a solder material having a thermal expansion property, and the second connecting member is provided after the first connecting member is provided. By doing in this way, the disconnection by the peeling of the circuit board and circuit element which generate | occur | produced by the heat processing added when forming a 2nd connection member, and the position shift of a circuit element can be suppressed.

本発明によれば、回路基板に回路素子を搭載した回路装置の耐熱信頼性を向上させることができる。   ADVANTAGE OF THE INVENTION According to this invention, the heat resistance reliability of the circuit apparatus which mounted the circuit element on the circuit board can be improved.

以下、本発明を具現化した実施形態について図面に基づいて説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。また、本明細書において、「上」方向とは、多層配線構造体に対して、回路素子が存在する方向が上であると規定している。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate. Further, in this specification, the “upward” direction defines that the direction in which the circuit elements exist is upward with respect to the multilayer wiring structure.

図２は、本発明の実施形態に係る回路装置の断面構造の一例を示す図である。この回路装置は、層間絶縁膜４０５および配線４０７からなる配線層が複数層積層した多層配線構造体５００と、その表面に形成された回路素子４１０ａおよび４１０ｂにより構成されている。回路素子４１０ａは、導電性ペーストなどの接着層４３０ａによって固定され、金線ボンディング４１２により配線４０７と導通されている。回路素子４１０ｂは、Ｎｉ合金核、Ｎｉめっき層、及びＳｎ−Ｓｂ−Ｂｉはんだ層の３層構造を有するはんだ材４３０ｂによって固着され、さらにはんだ材４３０ｂを介して配線４０７と電気的に接続している。   FIG. 2 is a diagram illustrating an example of a cross-sectional structure of the circuit device according to the embodiment of the present invention. This circuit device includes a multilayer wiring structure 500 in which a plurality of wiring layers including an interlayer insulating film 405 and wirings 407 are stacked, and circuit elements 410a and 410b formed on the surface thereof. The circuit element 410 a is fixed by an adhesive layer 430 a such as a conductive paste, and is electrically connected to the wiring 407 by a gold wire bonding 412. The circuit element 410b is fixed by a solder material 430b having a three-layer structure of a Ni alloy nucleus, a Ni plating layer, and a Sn—Sb—Bi solder layer, and is further electrically connected to the wiring 407 through the solder material 430b. Yes.

はんだ材４３０ｂとしては、例えば、Ｎｉ：３２％、Ｃｏ：５％、Ｆｅ：６３％（重量％）の合金に冷間加工を施したものを核とし、Ｎｉ−Ｐの無電解めっき（めっき厚３μｍ）でバリア膜を形成し、Ｓｎ：８５％、Ｓｂ：１０％、Ｂｉ：５％（重量％）はんだを用いる。上記Ｎｉを核とした合金は、３０％の冷間加工により熱収縮性を発現する。   As the solder material 430b, for example, an alloy of Ni: 32%, Co: 5%, Fe: 63% (weight%), which is cold-worked, is used as a core, and Ni—P electroless plating (plating thickness) 3 μm), a barrier film is formed, and Sn: 85%, Sb: 10%, Bi: 5% (weight%) solder is used. The alloy having Ni as a core exhibits heat shrinkability by cold working of 30%.

多層配線構造体５００の裏面には、はんだボール４２０が設けられている。回路素子４１０ａおよび４１０ｂは、封止樹脂４１５により封止された構造となっている。尚、はんだ材４３０ｂは、本発明の「第１接続部材」、はんだボール４２０は、本発明の「第２接続部材」の一例である。   Solder balls 420 are provided on the back surface of the multilayer wiring structure 500. The circuit elements 410a and 410b have a structure sealed with a sealing resin 415. The solder material 430b is an example of the “first connection member” in the present invention, and the solder ball 420 is an example of the “second connection member” in the present invention.

こうした回路装置においては、回路装置をプリント実装基板に実装する際に加わる熱処理によって発生する回路基板と回路素子との剥離による断線や回路素子の位置ずれを抑制することができる。また、封止樹脂の剥離欠陥やクラック発生も抑制することができる。これは、従来のはんだ接続部材を用いた場合では、回路装置をプリント実装基板などに実装接続する際に加わる熱処理によって、回路基板と回路素子を接続固定している部分の接続部材が体積膨張し、回路素子や封止樹脂に応力負荷がかかることに起因している。本実施形態では、熱収縮性を有するＮｉ合金核としたはんだ材を接続部剤として用いているので、回路装置をプリント実装基板などに実装接続する際の熱処理が加わっても応力負荷はかからないため、回路基板と回路素子との剥離や封止樹脂のクラックといった欠陥は生じない。   In such a circuit device, it is possible to suppress disconnection due to peeling between the circuit board and the circuit element and displacement of the circuit element caused by heat treatment applied when the circuit device is mounted on the printed mounting board. Moreover, peeling defects and cracks in the sealing resin can be suppressed. This is because when a conventional solder connection member is used, the connection member in the portion where the circuit board and the circuit element are connected and fixed is volume-expanded by heat treatment applied when the circuit device is mounted and connected to a printed circuit board or the like. This is because the stress load is applied to the circuit element and the sealing resin. In this embodiment, since a solder material having a Ni alloy core having heat shrinkability is used as a connecting agent, no stress load is applied even if heat treatment is applied when the circuit device is mounted and connected to a printed circuit board or the like. Defects such as peeling between the circuit board and the circuit element and cracks in the sealing resin do not occur.

次に本発明の実施形態として、支持基板のない回路装置の製造方法を例に挙げ、図３〜図５を参照して説明する。   Next, as an embodiment of the present invention, a method for manufacturing a circuit device without a support substrate will be described as an example and described with reference to FIGS.

まず、図３（Ａ）のように、金属箔４００上に所定の表面に選択的に導電被膜４０２を形成する。具体的には、フォトレジスト４０１で金属箔４００を被覆した後、電界めっき法により、金属箔４００の露出面に導電被膜４０２を形成する。導電被膜４０２の膜厚は、例えば１〜１０μｍ程度とする。この導電被膜４０２は、最終的に回路装置の裏面電極となるので、はんだ等のロウ材との接着性の良い金、または銀を用いて形成することが好ましい。 金属箔４００の主材料は、Ｃｕ、Ａｌ、Ｆｅ−Ｎｉ等の合金等とすることが好ましい。ロウ材の付着性やめっき性が良好だからである。金属箔４００の厚さは、ここでは７０μｍとするが、特に制限はない。通常は１０μｍ〜３００μｍ程度とする。   First, as shown in FIG. 3A, a conductive film 402 is selectively formed on a predetermined surface on a metal foil 400. Specifically, after covering the metal foil 400 with the photoresist 401, the conductive coating 402 is formed on the exposed surface of the metal foil 400 by electroplating. The film thickness of the conductive coating 402 is, for example, about 1 to 10 μm. Since this conductive film 402 finally becomes the back electrode of the circuit device, it is preferable to form the conductive film 402 using gold or silver having good adhesion to a brazing material such as solder. The main material of the metal foil 400 is preferably an alloy such as Cu, Al, or Fe—Ni. This is because the adhesion and plating properties of the brazing material are good. The thickness of the metal foil 400 is 70 μm here, but is not particularly limited. Usually, it is about 10 μm to 300 μm.

つづいて図３（Ｂ）に示すように、金属箔４００上に、第一層目の配線パターンを形成する。まず金属箔４００を化学研磨して表面のクリーニングと表面粗化を行う。次に、金属箔４００上に熱硬化性樹脂で導電被膜４０２全面を覆い、加熱硬化させて平坦な表面を有する膜とする。つづいてこの膜中に、導電被膜４０２に到達する直径１００μｍ程度のビアホール４０４を形成する。ビアホール４０４を設ける方法としては、本実施形態では炭酸ガスレーザーを用いた加工によったが、その他、機械加工、薬液による化学エッチング加工、プラズマを用いたドライエッチング法などを用いることもできる。   Subsequently, as shown in FIG. 3B, a first-layer wiring pattern is formed on the metal foil 400. First, the metal foil 400 is chemically polished to perform surface cleaning and surface roughening. Next, the entire surface of the conductive coating 402 is covered with a thermosetting resin on the metal foil 400 and is cured by heating to form a film having a flat surface. Subsequently, a via hole 404 having a diameter of about 100 μm reaching the conductive coating 402 is formed in the film. In this embodiment, the via hole 404 is formed by processing using a carbon dioxide gas laser. However, mechanical processing, chemical etching using chemicals, dry etching using plasma, or the like can also be used.

その後、エキシマレーザーを照射してエッチング滓を除去し、つづいて、ビアホール４０４を埋め込むように全面に銅めっき層を形成する。この銅めっき層はビアホール４０４の段差で断線しないように、まず無電界銅めっきして全面に約０．５μｍと薄く形成した後、電界めっきにより合計約２０μｍの厚みに形成する。無電解めっき用触媒は、通常パラジウムを用いることが多く、可とう性の絶縁基材に無電解用めっき用触媒を付着させるには、パラジウムを錯体の状態で水溶液に含ませ、可とう性の絶縁基材を浸漬して表面にパラジウム錯体を付着させ、そのまま、還元剤を用いて、金属パラジウムに還元することによって可とう性の絶縁基材表面にめっきを開始するための核を形成することができる。通常は、このような操作をするために、被めっき物を、アルコールや酸で洗浄し、表面に付着した油分を除去しておく。   Thereafter, excimer laser irradiation is performed to remove the etching soot, and then a copper plating layer is formed on the entire surface so as to fill the via hole 404. This copper plating layer is first formed by electroless copper plating so as to have a thin thickness of about 0.5 μm over the entire surface so as not to break at the step of the via hole 404, and then formed by electroplating to a total thickness of about 20 μm. In many cases, the electroless plating catalyst usually uses palladium. To attach the electroless plating catalyst to a flexible insulating substrate, palladium is included in an aqueous solution in the form of a complex. Forming a nucleus to start plating on the surface of a flexible insulating substrate by dipping the insulating substrate to attach a palladium complex to the surface and reducing it to metallic palladium directly using a reducing agent. Can do. Usually, in order to perform such an operation, the object to be plated is washed with alcohol or acid to remove oil adhering to the surface.

銅めっき層の形成時に、形成条件を調整することにより、所望の表面粗さや表面形態を実現し、その後に形成される層間絶縁膜との密着性を向上させることもできる。たとえば、無電界めっきを行う際、めっき液に添加剤を含有させ、その後、所定の条件でパルス電流による電界めっきを施し、さらに薬液により表面処理することにより、平滑表面に微細銅粒子の凹凸面が形成される。これにより、層間絶縁膜との密着性が向上する。微細銅粒子の凹凸面を好適に形成するためには、無電界めっきの段階で、銅のグレインサイズを小さくするとともに結晶軸が様々な方向を向くようにすることが好ましい。本実施形態と同様の工程により形成した銅めっきの表面凹凸を測定したところ、約０．８μｍ程度であった。   By adjusting the formation conditions during the formation of the copper plating layer, it is possible to achieve a desired surface roughness and surface form, and to improve the adhesion with an interlayer insulating film formed thereafter. For example, when electroless plating is performed, an additive is added to the plating solution, followed by electroplating with a pulsed current under predetermined conditions, and further surface treatment with a chemical solution, thereby providing an uneven surface with fine copper particles on a smooth surface. Is formed. This improves the adhesion with the interlayer insulating film. In order to suitably form the uneven surface of the fine copper particles, it is preferable that the grain size of the copper is reduced and the crystal axes are directed in various directions at the stage of electroless plating. When the surface unevenness of the copper plating formed by the same process as in the present embodiment was measured, it was about 0.8 μm.

その後、フォトレジストをマスクとして銅めっき層をエッチングし、銅からなる配線４０７を形成する。たとえば、レジストから露出した箇所に、化学エッチング液をスプレー噴霧して不要な銅箔をエッチング除去し、配線パターンを形成することができる。エッチングレジストは、通常のプリント配線板に用いることのできるエッチングレジスト材料を用いることができ、レジストインクをシルクスクリーン印刷して形成したり、エッチングレジスト用感光性ドライフィルムを銅箔の上にラミネートして、その上に配線導体の形状に光を透過するフォトマスクを重ね、紫外線を露光し、露光しなかった箇所を現像液で除去して形成することができる。化学エッチング液には、塩化第二銅と塩酸の溶液、塩化第二鉄溶液、硫酸と過酸化水素の溶液、過硫酸アンモニウム溶液など、通常のプリント配線板に用いる化学エッチング液を用いることができる。   Thereafter, the copper plating layer is etched using the photoresist as a mask to form a wiring 407 made of copper. For example, a chemical etching solution can be sprayed and sprayed onto a portion exposed from the resist to remove unnecessary copper foil, thereby forming a wiring pattern. As the etching resist, an etching resist material that can be used for an ordinary printed wiring board can be used. The resist can be formed by silk screen printing of a resist ink, or a photosensitive dry film for etching resist is laminated on a copper foil. Then, a photomask that transmits light is superimposed on the shape of the wiring conductor, and ultraviolet rays are exposed, and a portion that is not exposed can be removed with a developer. As the chemical etching solution, a chemical etching solution used for an ordinary printed wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

同様の手順により、層間絶縁膜４０５の形成、ビアホール形成、銅めっき層の形成および銅めっき層のパターニングの手順を繰り返し行うことにより、図３（Ｃ）に示すような多層配線構造を形成する。すなわち、配線４０７および層間絶縁膜４０５からなる配線層が積層した多層配線構造を形成する。   A multilayer wiring structure as shown in FIG. 3C is formed by repeating the procedure of forming the interlayer insulating film 405, forming the via hole, forming the copper plating layer, and patterning the copper plating layer by the same procedure. That is, a multilayer wiring structure in which wiring layers including the wiring 407 and the interlayer insulating film 405 are stacked is formed.

つづいて図４（Ａ）に示すように、回路素子４１０ａ、４１０ｂを搭載する。まず多層配線パターンの表面にソルダーレジスト層４０８を形成する。ソルダーレジスト層４０８を構成する材料としては、エポキシ樹脂、アクリル樹脂、ウレタン樹脂、ポリイミド樹脂等の樹脂、および、これらの混合物、さらに、これらの樹脂にカーボンブラック、アルミナ、窒化アルミニウム、窒化ホウ素、酸化スズ、酸化鉄、酸化銅、タルク、雲母、カオリナイト、炭酸カルシウム、シリカ、酸化チタン等の無機フィラーを混合したもの等が例示される。ここでは、フィラー含有エポキシ樹脂を用いる。   Subsequently, as shown in FIG. 4A, circuit elements 410a and 410b are mounted. First, a solder resist layer 408 is formed on the surface of the multilayer wiring pattern. As a material constituting the solder resist layer 408, epoxy resin, acrylic resin, urethane resin, polyimide resin and the like, and a mixture thereof, carbon black, alumina, aluminum nitride, boron nitride, oxide Examples thereof include a mixture of inorganic fillers such as tin, iron oxide, copper oxide, talc, mica, kaolinite, calcium carbonate, silica, and titanium oxide. Here, a filler-containing epoxy resin is used.

次に、ソルダーレジスト層４０８の表面に回路素子４１０ａ、４１０ｂを搭載する。回路素子４１０ａとしては、トランジスタ、ダイオード、ＩＣチップ等の半導体素子であり、回路素子４１０ｂとしては、チップコンデンサ、チップ抵抗等の受動素子である。なお、ＣＳＰ、ＢＧＡ等のフェイスダウンの半導体素子も実装できる。図４（Ａ）の構造では、回路素子４１０ａがベアーのトランジスタチップであり、回路素子４１０ｂがチップコンデンサである。回路素子４１０ａは、樹脂からなる接着層４３０ａによりソルダーレジスト層４０８に固着する。接着層４３０ａとして、熱硬化性樹脂で構成される絶縁ペーストを用いる場合は、１００℃以上に加熱することにより、ソルダーレジスト層４０８と固着する。その後、配線４０７と金線４１２により結線する。回路素子４１０ｂは、Ｎｉ合金核、Ｎｉめっき層、及びＳｎ−Ｓｂ−Ｂｉはんだ層の３層構造を有するはんだ材４３０ｂにより配線層４０７に固着される。上記はんだ材を微粒子にし、クリームはんだとして用いる場合は、リフロー工程をさらに経ることで、固着される。これらを絶縁性樹脂４１５でモールドする。回路素子のモールドは、金属箔４００に設けた複数個のモジュールに対して、金型を用いて同時に行う。この工程は、トランスファーモールド、インジェクションモールド、ポッティングまたはディッピングにより実現できる。樹脂材料としては、エポキシ樹脂等の熱硬化性樹脂がトランスファーモールドまたはポッティングで実現でき、ポリイミド樹脂、ポリフェニレンサルファイド等の熱可塑性樹脂はインジェクションモールドで実現できる。   Next, circuit elements 410 a and 410 b are mounted on the surface of the solder resist layer 408. The circuit element 410a is a semiconductor element such as a transistor, a diode, or an IC chip, and the circuit element 410b is a passive element such as a chip capacitor or a chip resistor. A face-down semiconductor element such as CSP or BGA can also be mounted. In the structure of FIG. 4A, the circuit element 410a is a bare transistor chip, and the circuit element 410b is a chip capacitor. The circuit element 410a is fixed to the solder resist layer 408 with an adhesive layer 430a made of resin. In the case where an insulating paste made of a thermosetting resin is used as the adhesive layer 430a, the adhesive layer 430a is fixed to the solder resist layer 408 by heating to 100 ° C. or higher. Thereafter, the wiring 407 and the gold wire 412 are connected. The circuit element 410b is fixed to the wiring layer 407 by a solder material 430b having a three-layer structure of a Ni alloy nucleus, a Ni plating layer, and a Sn—Sb—Bi solder layer. When the solder material is made into fine particles and used as a cream solder, the solder material is fixed through a reflow process. These are molded with an insulating resin 415. The molding of the circuit element is simultaneously performed on a plurality of modules provided on the metal foil 400 using a mold. This process can be realized by transfer molding, injection molding, potting or dipping. As the resin material, a thermosetting resin such as epoxy resin can be realized by transfer molding or potting, and a thermoplastic resin such as polyimide resin and polyphenylene sulfide can be realized by injection molding.

はんだ材４３０ｂとしては、例えば、Ｎｉ：３２％、Ｃｏ：５％、Ｆｅ：６３％（重量％）の合金に冷間加工を施したものを核とし、Ｎｉ−Ｐの無電解めっき（めっき厚３μｍ）でバリア膜を形成し、Ｓｎ：８５％、Ｓｂ：１０％、Ｂｉ：５％（重量％）はんだを用いる。上記Ｎｉを核とした合金は３０％の冷間加工により、熱収縮性を発現する。   As the solder material 430b, for example, an alloy of Ni: 32%, Co: 5%, Fe: 63% (weight%), which is cold-worked, is used as a core, and Ni—P electroless plating (plating thickness) 3 μm), a barrier film is formed, and Sn: 85%, Sb: 10%, Bi: 5% (weight%) solder is used. The alloy having Ni as a core exhibits heat shrinkability by cold working of 30%.

その後、図４（Ｂ）に示すように、多層配線構造から金属箔４００を除去し、裏面にはんだボール４２０を形成する。金属箔４００の除去は、研磨、研削、エッチング、レーザの金属蒸発等により行うことができる。本実施形態では以下の方法を採用する。すなわち、研磨装置または研削装置により金属箔４００全面を５０μｍ程度削り、残りの金属箔４００を化学的にウェットエッチングにより除去する。なお、金属箔４００全部をウェットエッチングにより除去してもよい。こうした工程を経ることにより、回路素子の搭載された側と反対側の面に、第１層目の配線４０７の裏面が露出する構造となる。これにより、本実施形態で得られるモジュールでは裏面が平坦となり、回路装置のマウント時にはんだ等の表面張力でそのまま水平に移動し、容易にセルフアラインできるというプロセス上の利点が得られる。つづいて露出した導電被膜４０２にはんだ等の導電材を被着してはんだボール４２０を形成し、回路装置を完成する。   Thereafter, as shown in FIG. 4B, the metal foil 400 is removed from the multilayer wiring structure, and solder balls 420 are formed on the back surface. The metal foil 400 can be removed by polishing, grinding, etching, laser metal evaporation, or the like. In the present embodiment, the following method is adopted. That is, the entire surface of the metal foil 400 is cut by about 50 μm with a polishing apparatus or a grinding apparatus, and the remaining metal foil 400 is chemically removed by wet etching. Note that the entire metal foil 400 may be removed by wet etching. Through these steps, the back surface of the first layer wiring 407 is exposed on the surface opposite to the circuit element mounting side. As a result, the module obtained in the present embodiment has a flat surface on the back surface, and when the circuit device is mounted, it can be moved horizontally by the surface tension of solder or the like and can be easily self-aligned. Subsequently, a conductive material such as solder is applied to the exposed conductive film 402 to form solder balls 420, thereby completing the circuit device.

はんだボール４２０としては、例えば、Ｓｎ：８５％、Ｓｂ：１０％、Ｂｉ：５％（重量％）はんだを用いる。   As the solder ball 420, for example, Sn: 85%, Sb: 10%, Bi: 5% (weight%) solder is used.

なお、はんだ材４３０ｂとはんだボール４２０の溶融温度は、それぞれ２４０℃と２２０℃である。このため、はんだボール４２０を形成する際においても、はんだ材４３０ｂは溶融することはなく、安定して回路装置を形成することができる。   The melting temperatures of the solder material 430b and the solder ball 420 are 240 ° C. and 220 ° C., respectively. For this reason, even when the solder ball 420 is formed, the solder material 430b is not melted, and the circuit device can be stably formed.

上記した金属箔４００の除去工程を行うまでは、金属箔４００が支持基板となる。金属箔４００は、配線４０７形成時の電解めっき工程において電極としても利用される。また、封止樹脂４１５をモールドする際にも、金型への搬送、金型への実装の作業性を良好にすることができる。   Until the above-described removal process of the metal foil 400 is performed, the metal foil 400 becomes a support substrate. The metal foil 400 is also used as an electrode in the electrolytic plating process when the wiring 407 is formed. In addition, when molding the sealing resin 415, it is possible to improve the workability of conveyance to the mold and mounting on the mold.

次に、封止樹脂４１５を回路装置毎にダイシングにより分離する。図５は、ダイシングの方法を説明するための図である。絶縁樹脂層４５５上に、複数の回路装置形成領域がマトリクス状に配置されている。配線パターン４６５が形成されていない部分は絶縁樹脂４６０が露出している。ダイシングは、ダイシングライン４９０に沿って行われるため、絶縁樹脂のみの切断となり、金属箔の切断やモールド樹脂の切断によって引き起こされる切断面の荒れやブレードの消耗等が抑制される。なお、本例では位置合わせマーク４７０を設けているため、ダイシングラインの位置を迅速かつ正確に把握することができる。なお、ＢＧＡ等の従来のＣＳＰにおいては、基板上に形成されたモジュールを金型で打ち抜く方法が採用されている。本実施形態ではダイシングにより絶縁樹脂を切断することによりモジュールを得ることができ、製造プロセス上、大きなメリットがある。   Next, the sealing resin 415 is separated for each circuit device by dicing. FIG. 5 is a diagram for explaining a dicing method. A plurality of circuit device formation regions are arranged in a matrix on the insulating resin layer 455. The insulating resin 460 is exposed at a portion where the wiring pattern 465 is not formed. Since the dicing is performed along the dicing line 490, only the insulating resin is cut, and the roughening of the cut surface and the blade consumption caused by the cutting of the metal foil and the cutting of the mold resin are suppressed. In this example, since the alignment mark 470 is provided, the position of the dicing line can be grasped quickly and accurately. In a conventional CSP such as BGA, a method of punching a module formed on a substrate with a mold is employed. In the present embodiment, a module can be obtained by cutting the insulating resin by dicing, which has a great merit in the manufacturing process.

以上の工程により、支持基板を有しない回路装置を作製することができる。なお、本発明の回路装置は上記実施の形態以外の方法で作製することもできる。   Through the above steps, a circuit device having no supporting substrate can be manufactured. Note that the circuit device of the present invention can be manufactured by a method other than the above embodiment mode.

ＩＳＢ（登録商標）の構造を説明するための図である。It is a figure for demonstrating the structure of ISB (trademark). 実施の形態に係る回路装置の構造を説明するための図である。It is a figure for demonstrating the structure of the circuit device which concerns on embodiment. 実施の形態に係る回路装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the circuit device which concerns on embodiment. 実施の形態に係る回路装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the circuit device which concerns on embodiment. 実施の形態に係る回路装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the circuit device which concerns on embodiment.

符号の説明Explanation of symbols

２００ 回路装置
２０１ ＬＳＩベアチップ
２０２ Ｔｒベアチップ
２０３ チップＣＲ
２０４ 金線ボンディング
２０５ 銅パターン
２０６ 導電性ペースト
２０７ 樹脂パッケージ
２０８ はんだボール
２０９ 接続部材
４００ 金属箔
４０１ フォトレジスト
４０２ 導電被膜
４０５ 層間絶縁膜
４０７ 配線
４０８ ソルダーレジスト層
４１０ａ 回路素子
４１０ｂ 回路素子
４１２ 金線
４１５ 絶縁性樹脂
４２０ はんだボール
４３０ａ 接着層
４３０ｂ Ｎｉ合金核、Ｎｉめっき層、及びＳｎを主体とするはんだ層の３層構造を有するはんだ材
４５５ 絶縁樹脂層
４６０ 絶縁樹脂
４６５ 配線パターン
４７０ マーク
４９０ ダイシングライン
５００ 回路装置 200 Circuit Device 201 LSI Bare Chip 202 Tr Bare Chip 203 Chip CR
204 Gold wire bonding 205 Copper pattern 206 Conductive paste 207 Resin package 208 Solder ball 209 Connection member 400 Metal foil 401 Photo resist 402 Conductive coating 405 Interlayer insulating film 407 Wiring 408 Solder resist layer 410a Circuit element 410b Circuit element 412 Gold line 415 Insulation Resin 420 Solder ball 430a Adhesive layer 430b Solder material 455 having three-layer structure of Ni alloy core, Ni plating layer, and solder layer mainly composed of Sn Insulating resin layer 460 Insulating resin 465 Wiring pattern 470 Mark 490 Dicing line 500 Circuit apparatus

Claims (4)

回路基板と、
前記回路基板の一方の面に搭載された回路素子と、
前記回路基板に、前記回路素子を固定する第１接続部材と、
前記回路基板の他方の面に設けられた第２接続部材と、を備え、
前記第１接続部材は、熱収縮性を有するＮｉ合金を核とした接続部材であることを特徴とした回路装置。 A circuit board;
A circuit element mounted on one surface of the circuit board;
A first connecting member for fixing the circuit element to the circuit board;
A second connecting member provided on the other surface of the circuit board,
The circuit device according to claim 1, wherein the first connecting member is a connecting member having a heat-shrinkable Ni alloy as a core. 前記第１接続部材は、Ｎｉ合金核、Ｎｉめっき層、及びＳｎを主体とするはんだ層の３層構造を有するはんだ材であることを特徴とした請求項１に記載の回路装置。   The circuit device according to claim 1, wherein the first connection member is a solder material having a three-layer structure of a Ni alloy nucleus, a Ni plating layer, and a solder layer mainly composed of Sn. 前記回路素子と前記第１接続部材は、樹脂で覆われていることを特徴とした請求項１または２に記載の回路装置。   The circuit device according to claim 1, wherein the circuit element and the first connection member are covered with a resin. 前記第２接続部材は、熱膨張性を有する接続部材であって、前記第１接続部材を設けた後に前記第２接続部材を設けることを特徴とした請求項１〜３のいずれか１項に記載の回路装置。   The said 2nd connection member is a connection member which has thermal expansibility, Comprising: After providing the said 1st connection member, the said 2nd connection member is provided, The any one of Claims 1-3 characterized by the above-mentioned. The circuit device described.
JP2005055077A 2005-02-28 2005-02-28 Circuit apparatus Pending JP2006245070A (en)

Priority Applications (1)

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Family Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207006A (en) * 2012-03-28 2013-10-07 Toppan Printing Co Ltd Wiring board with through electrode and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013207006A (en) * 2012-03-28 2013-10-07 Toppan Printing Co Ltd Wiring board with through electrode and manufacturing method of the same

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