JP2006237410A - Mounting method for semiconductor element - Google Patents

Mounting method for semiconductor element Download PDF

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Publication number
JP2006237410A
JP2006237410A JP2005052176A JP2005052176A JP2006237410A JP 2006237410 A JP2006237410 A JP 2006237410A JP 2005052176 A JP2005052176 A JP 2005052176A JP 2005052176 A JP2005052176 A JP 2005052176A JP 2006237410 A JP2006237410 A JP 2006237410A
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Prior art keywords
electrode
semiconductor element
mounting
insulating film
wiring board
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Japanese (ja)
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Kentaro Nishiwaki
健太郎 西脇
Hiroyuki Kobayashi
弘幸 小林
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005052176A priority Critical patent/JP2006237410A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting method which has small thermal hysteresis, and in which a semiconductor element is only pressed against a circuit board with a low load, and a conduction defect caused by shearing strain is reducible even if there is a difference in coefficient of thermal expansion between the circuit board and semiconductor element. <P>SOLUTION: A 2nd electrode 4 having a recess and an uncured insulating film layer 11 arranged outside the 2nd electrode 4 are formed on a wiring board 3 corresponding to a 1st projection electrode 2 formed on the semiconductor element 1. While the 1st electrode 2 is inserted into the recess of the 2nd electrode 4, the insulating film layer 11 on the wiring board 3 is shrunk to be cured while the 2nd electrode 4 is pressed against the outer peripheral side of the 1st electrode 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体素子を配線基板に実装する方法に関する。   The present invention relates to a method for mounting a semiconductor element on a wiring board.

(特許文献1)の図1には、回路基板と半導体素子の間に熱膨張係数の差があっても、突起電極と接続電極との係合によってせん断歪みによって生じていた導通不良を低減することを目的として、回路基板に形成された接続電極に凹部を形成し、実装すべき半導体素子には全部または一部が前記凹部に埋め込まれる突起電極が形成され、回路基板と半導体素子の間に封止樹脂を充填して実装する技術が示されている。   In FIG. 1 of (Patent Document 1), even if there is a difference in thermal expansion coefficient between the circuit board and the semiconductor element, conduction failure caused by shear strain due to the engagement between the protruding electrode and the connection electrode is reduced. For this purpose, a recess is formed in the connection electrode formed on the circuit board, and a protruding electrode in which all or part of the semiconductor element to be mounted is embedded in the recess is formed between the circuit board and the semiconductor element. A technique for filling and mounting a sealing resin is shown.

また、(特許文献2)の図3には、実装のし易さと強固な実装状態ならびに容易な取り外しを目的として、回路基板の実装位置にバンプ装着凹部を形成し、半導体素子には加熱により体積が収縮する形状記憶合金で形成されたバンプを形成し、加熱して体積を収縮させた状態で前記バンプをバンプ装着凹部に係合させ、次に冷却することによって前記収縮状態から膨張した前記バンプがバンプ装着凹部に接続固定する技術が示されている。電気接続はバンプ装着凹部の底部と前記バンプの先端との導通である。
特開2002−170852公報 図1 特開2002−208607公報 図3
Further, FIG. 3 of (Patent Document 2) shows a bump mounting recess formed at the mounting position of the circuit board for the purpose of easy mounting, strong mounting state, and easy removal, and the semiconductor element has a volume by heating. The bumps are expanded from the contracted state by forming bumps formed of a shape memory alloy that contracts, engaging the bumps with the bump mounting recesses while the volume is contracted by heating, and then cooling. Shows a technique for connecting and fixing to a bump mounting recess. The electrical connection is conduction between the bottom of the bump mounting recess and the tip of the bump.
JP 2002-170852 A Japanese Patent Laid-Open No. 2002-208607

しかしながら上記(特許文献1)の構成では、突起電極と接続電極との係合だけでなく回路基板と半導体素子の間に充填された封止樹脂とによって実装状態が維持されており、安定した実装状態を得るためには、突起電極と接続電極との係合の隙間を小さくするとともに、封止樹脂が硬化するまでは半導体素子を回路基板に押し付けていないといけない問題がある。厚みの薄いパッケージの半導体素子の場合には封止樹脂が硬化するまでの期間の押圧力が適当でなければ半導体素子の破壊が生じる。   However, in the configuration of the above (Patent Document 1), the mounting state is maintained not only by the engagement between the protruding electrode and the connection electrode but also by the sealing resin filled between the circuit board and the semiconductor element, so that stable mounting is possible. In order to obtain the state, there is a problem that the gap between the protrusion electrode and the connection electrode is reduced, and the semiconductor element must be pressed against the circuit board until the sealing resin is cured. In the case of a semiconductor element having a thin package, the semiconductor element is destroyed if the pressing force during the period until the sealing resin is cured is not appropriate.

また、(特許文献2)ではパンプが収縮するように加熱することが必要であって、熱履歴が大きくなる問題がある他、十分に冷まされてバンプが膨張するまでの期間にわたって半導体素子を回路基板に押し付けていないといけない問題がある。厚みの薄いパッケージの半導体素子の場合には半導体素子の破壊が生じる。   In addition, in (Patent Document 2), it is necessary to heat the pump so that the pump contracts, and there is a problem that the thermal history becomes large. In addition, the semiconductor element is formed over a period until the bump is sufficiently cooled and the bump expands. There is a problem that must be pressed against the circuit board. In the case of a semiconductor element having a thin package, the semiconductor element is destroyed.

本発明は、従来に比べて熱履歴が少なく、従来のように実装作業中に半導体素子を低荷重で回路基板に押し付けるだけでも極めて良好な実装状態が得られ、回路基板と半導体素子の間に熱膨張係数の差があってもせん断歪みによって生じていた導通不良を低減できる半導体素子の実装方法を提供することを目的とする。   The present invention has a less thermal history than the prior art, and a very good mounting state can be obtained just by pressing the semiconductor element against the circuit board with a low load during the mounting work as in the past, and between the circuit board and the semiconductor element. It is an object of the present invention to provide a method for mounting a semiconductor element that can reduce poor conduction caused by shear strain even if there is a difference in thermal expansion coefficient.

本発明の請求項1記載の半導体素子の実装方法は、半導体素子に形成された第1電極と配線基板に形成された第2電極とが導通状態となるように前記半導体素子を前記配線基板に実装するに際し、前記配線基板における前記半導体素子の実装位置に、前記半導体素子に形成された凸状の前記第1電極に対応して凹部が形成された前記第2電極とこの第2電極の外側に配置された未硬化の絶縁膜層を形成し、前記第2電極の凹部に前記第1電極を挿入した状態で前記配線基板の前記絶縁膜層を収縮させて前記第1電極の外周側に前記第2電極を押し付けた状態で硬化させることを特徴とする。   According to a first aspect of the present invention, there is provided a method of mounting a semiconductor element on the wiring board such that the first electrode formed on the semiconductor element and the second electrode formed on the wiring board are in a conductive state. In mounting, the second electrode in which a concave portion is formed corresponding to the convex first electrode formed in the semiconductor element at the mounting position of the semiconductor element on the wiring board, and the outside of the second electrode An uncured insulating film layer disposed on the second electrode is formed, and the insulating film layer of the wiring board is contracted in a state where the first electrode is inserted into the concave portion of the second electrode, so that the outer peripheral side of the first electrode It hardens | cures in the state which pressed the said 2nd electrode.

また、本発明の請求項2記載の半導体素子の実装方法は、半導体素子に形成された第1電極と配線基板に形成された第2電極とが導通状態となるように前記半導体素子を前記配線基板に実装するに際し、前記配線基板の実装位置に形成された凸状の前記第2電極に対応して、前記半導体素子には凹部が形成された前記第1電極とこの第1電極の外側に配置された未硬化の絶縁膜層を形成し、前記第1電極の凹部に前記第2電極を挿入した状態で前記半導体素子の前記絶縁膜層を収縮させて前記第2電極の外周側に前記第1電極を押し付けた状態で硬化させることを特徴とする。   According to a second aspect of the present invention, there is provided a method for mounting a semiconductor element, wherein the wiring of the semiconductor element is performed so that a first electrode formed on the semiconductor element and a second electrode formed on a wiring board are in a conductive state. When mounting on a substrate, the semiconductor element has a recess formed in the semiconductor element corresponding to the convex second electrode formed at the mounting position of the wiring substrate, and on the outside of the first electrode. An uncured insulating film layer is formed, and the insulating film layer of the semiconductor element is contracted in a state where the second electrode is inserted into the concave portion of the first electrode, and the outer peripheral side of the second electrode is It hardens | cures in the state which pressed the 1st electrode.

また、本発明の請求項3記載の半導体素子の実装方法は、請求項1において、凹部が形成された第2電極の内周面の少なくとも一部の表面粗さを、半導体素子に形成された第1電極の表面粗さよりも粗くすることを特徴とする。   According to a third aspect of the present invention, there is provided the semiconductor element mounting method according to the first aspect, wherein at least a part of the surface roughness of the inner peripheral surface of the second electrode in which the recess is formed is formed on the semiconductor element. The surface roughness of the first electrode is made rougher.

また、本発明の請求項4記載の半導体素子の実装方法は、請求項1において、第1電極の先端を基端部よりも細くすることを特徴とする。
また、本発明の請求項5記載の半導体素子の実装方法は、請求項1において、第2電極の凹部の形状を、奥端よりも開口部を広くすることを特徴とする。
According to a fourth aspect of the present invention, there is provided a semiconductor element mounting method according to the first aspect, wherein the tip of the first electrode is made thinner than the base end.
According to a fifth aspect of the present invention, there is provided a method for mounting a semiconductor element according to the first aspect, wherein the concave portion of the second electrode is made wider than the back end.

また、本発明の請求項6記載の半導体素子の実装方法は、請求項1において、前記第2電極の凹部に前記第1電極を挿入する前に、前記第2電極の凹部に前記第1電極を挿入する前に、前記第2電極の凹部に接着材または導電性材料またはクリーム半田などの材料を入れることを特徴とする。   The semiconductor element mounting method according to claim 6 of the present invention is the method for mounting a semiconductor element according to claim 1, wherein the first electrode is inserted into the recess of the second electrode before the first electrode is inserted into the recess of the second electrode. Before inserting a material, an adhesive, a conductive material, or a material such as cream solder is put into the recess of the second electrode.

また、本発明の請求項7記載の実装体は、第1電極が凸状の形成された半導体素子と、配線基板における前記半導体素子の実装位置に前記第1電極に対応して凹部が形成された前記第2電極とこの第2電極の外側に配置された絶縁膜層が形成された配線基板とを有し、未硬化の前記絶縁膜層に形成された凹部の内側に導電材料を蒸着して形成された前記第2電極の凹部に、前記第1電極を挿入した状態で前記配線基板の前記絶縁膜層を収縮させて硬化し前記第1電極の外周側に前記第2電極を押し付けて導通状態に実装したことを特徴とする。   In the mounting body according to claim 7 of the present invention, the first electrode has a convexly formed semiconductor element, and a concave portion is formed at the mounting position of the semiconductor element on the wiring board corresponding to the first electrode. And a wiring board on which an insulating film layer disposed outside the second electrode is formed, and a conductive material is deposited inside a recess formed in the uncured insulating film layer. The insulating film layer of the wiring board is contracted and cured in a state where the first electrode is inserted into the concave portion of the second electrode formed by pressing the second electrode against the outer peripheral side of the first electrode. It is mounted in a conductive state.

また、本発明の請求項8記載の実装体は、凹状の形成された第1電極とこの第1電極の外側に配置された絶縁膜層が形成された半導体素子と、前記半導体素子の実装位置に前記第1電極に対応して凸状の第2電極が形成された配線基板とを有し、未硬化の前記絶縁膜層に形成された凹部の内側に導電材料を蒸着して形成された前記第1電極の凹部に、前記第2電極を挿入した状態で半導体素子の前記絶縁膜層を収縮させて硬化し前記第2電極の外周側に前記第1電極を押し付けて導通状態に実装したことを特徴とする。   According to another aspect of the present invention, there is provided a mounting body including a semiconductor element having a first electrode formed in a concave shape and an insulating film layer disposed outside the first electrode, and a mounting position of the semiconductor element. And a wiring board on which a convex second electrode is formed corresponding to the first electrode, and formed by depositing a conductive material inside the concave portion formed in the uncured insulating film layer. The insulating film layer of the semiconductor element is contracted and cured in a state where the second electrode is inserted into the concave portion of the first electrode, and the first electrode is pressed against the outer peripheral side of the second electrode and mounted in a conductive state. It is characterized by that.

本発明の請求項1または請求項2に記載の半導体素子の実装方法によると、半導体素子と配線基板のうちの一方に設けられた凸状の電極の先端を他方に設けられた凹部が形成された電極に挿入し、前記凹部が形成された電極の外側に配置された未硬化の絶縁膜層を収縮硬化させて、変形した前記凹部が形成された電極が前記凸状の電極の外周側に押し付けられた良好な実装状態が得られる。   According to the semiconductor element mounting method of the first or second aspect of the present invention, a concave portion is formed in which the tip of the convex electrode provided on one of the semiconductor element and the wiring board is provided on the other. The uncured insulating film layer disposed outside the electrode in which the concave portion is formed is contracted and hardened so that the electrode in which the deformed concave portion is formed is on the outer peripheral side of the convex electrode. A good mounted state can be obtained.

以下、本発明の半導体素子の実装方法を具体的な各実施の形態に基づいて説明する。
(実施の形態1)
図1〜図3と図12(a)は本発明の(実施の形態1)を示す。
The semiconductor element mounting method of the present invention will be described below based on specific embodiments.
(Embodiment 1)
1 to 3 and FIG. 12A show (Embodiment 1) of the present invention.

図1は半導体素子1に形成された第1電極2と配線基板3に形成された第2電極4とが導通状態となるように実装する本発明の実装方法の工程を示す。
先ず、図1(a)に示す半導体素子1には、図2に示す工程で第1電極2が形成されている。
FIG. 1 shows the steps of the mounting method of the present invention in which mounting is performed so that the first electrode 2 formed on the semiconductor element 1 and the second electrode 4 formed on the wiring board 3 are in a conductive state.
First, in the semiconductor element 1 shown in FIG. 1A, the first electrode 2 is formed in the step shown in FIG.

図2(a)(b)に示すように、半導体素子1の端子電極5が形成されている側に端子電極5を覆うように形成したレジスト6を、マスク7を介して選択的に紫外光(UV)によって露光する。マスク7は、ここではそれぞれ端子電極5の上方位置に透過窓8が形成されている。露光の完了したレジスト6を現像して未硬化の部分を除去して図2(c)のように端子電極5に達する孔9が形成される。   As shown in FIGS. 2A and 2B, a resist 6 formed so as to cover the terminal electrode 5 on the side where the terminal electrode 5 of the semiconductor element 1 is formed is selectively irradiated with ultraviolet light through a mask 7. Exposure by (UV). Here, each of the masks 7 is formed with a transmission window 8 above the terminal electrode 5. The exposed resist 6 is developed to remove the uncured portion, and a hole 9 reaching the terminal electrode 5 is formed as shown in FIG.

次に、図2(d)に示すように孔9の内側にかけてAuをスパッタリングしてAu膜2bを形成する。さらにAu膜2bにAuを電解メッキして孔9の内側をAuで満たし、レジスト6の上のAu膜2bを除去して、図2(e)の状態から図2(f)に示すようにレジスト6を除去して図1(a)に示した凸状の第1電極2を有した半導体素子1を形成する。ここではそれぞれの第1電極2は円柱形である。   Next, as shown in FIG. 2D, Au is sputtered inside the hole 9 to form an Au film 2b. Further, the Au film 2b is electroplated with Au to fill the inside of the hole 9 with Au, and the Au film 2b on the resist 6 is removed, so that the state shown in FIG. 2 (e) is shown in FIG. 2 (f). The resist 6 is removed to form the semiconductor element 1 having the convex first electrode 2 shown in FIG. Here, each first electrode 2 has a cylindrical shape.

また、図1(a)に示す配線基板3には、図3に示す工程で第2電極4が形成されている。
図3(a)(b)に示すように、配線基板3の接続電極10が形成されている側に接続電極10を覆うように未硬化の絶縁膜層11を形成し、その上に図3(c)に示すように形成したレジスト12を、マスク13を介して選択的に紫外光(UV)によって露光する。マスク13は、ここではそれぞれ接続電極10の上方位置に透過窓14が形成されている。露光の完了したレジスト12を現像して未硬化の部分を除去して図3(d)のように除去した後に絶縁膜層11を選択的にエッチングして図3(e)に示すように接続電極10に達する孔15が形成される。
Further, the second electrode 4 is formed on the wiring substrate 3 shown in FIG. 1A by the process shown in FIG.
As shown in FIGS. 3A and 3B, an uncured insulating film layer 11 is formed on the side of the wiring board 3 on which the connection electrode 10 is formed so as to cover the connection electrode 10, and on that, the FIG. The resist 12 formed as shown in (c) is selectively exposed to ultraviolet light (UV) through a mask 13. Here, each of the masks 13 is formed with a transmission window 14 above the connection electrode 10. The exposed resist 12 is developed to remove the uncured portion and removed as shown in FIG. 3D, and then the insulating film layer 11 is selectively etched to connect as shown in FIG. A hole 15 reaching the electrode 10 is formed.

次に、図3(f)に示すように孔15の内側にかけてAuを蒸着してAu膜16を形成する。さらに、レジスト12を図3(g)に示すように除去して図1(a)に示した、凹部が形成された第2電極4とこの第2電極4の外側に配置された未硬化の絶縁膜層11を形成した配線基板3を形成する。ここでは絶縁膜層11としてエポキシ系樹脂を使用し、第2電極4の厚みは1.0μmであった。第2電極4の厚みの範囲は0.1μm〜5.0μmならよい。図12(a)に平面図を示す。   Next, as shown in FIG. 3 (f), Au is evaporated over the inside of the hole 15 to form an Au film 16. Further, the resist 12 is removed as shown in FIG. 3G, and the second electrode 4 with the recesses formed as shown in FIG. 1A and the uncured material arranged outside the second electrode 4 are shown. The wiring substrate 3 on which the insulating film layer 11 is formed is formed. Here, an epoxy resin was used as the insulating film layer 11, and the thickness of the second electrode 4 was 1.0 μm. The thickness range of the second electrode 4 may be 0.1 μm to 5.0 μm. FIG. 12A shows a plan view.

このようにして製作した半導体素子1の第1電極2を、図1(b)に示すように配線基板3の第2電極4に挿入し、例えば配線基板3を加熱して未硬化の絶縁膜層11を硬化させる。硬化が始まると絶縁膜層11は収縮して第2電極4が収縮した絶縁膜層11によって内側に向かって圧縮される。   The first electrode 2 of the semiconductor element 1 manufactured in this way is inserted into the second electrode 4 of the wiring board 3 as shown in FIG. 1B, and for example, the wiring board 3 is heated to form an uncured insulating film. Layer 11 is cured. When curing begins, the insulating film layer 11 contracts and the second electrode 4 is compressed inward by the contracted insulating film layer 11.

この圧縮によって第2電極4は変形して第1電極2の外周側に押し付けられて確実な導通状態が得られる。この状態では配線基板3と半導体素子1の間に熱膨張係数の差があってもせん断歪みによる導通不良は従来に比べて低減できた。   By this compression, the second electrode 4 is deformed and pressed against the outer peripheral side of the first electrode 2 to obtain a reliable conduction state. In this state, even if there is a difference in thermal expansion coefficient between the wiring board 3 and the semiconductor element 1, conduction failure due to shear strain can be reduced as compared with the conventional case.

(実施の形態2)
図4は本発明の(実施の形態2)を示す。
図1では第2電極4は開口部4aから奥端にかけて同一径であったが、この図4(a)では、第2電極4の開口部4aが奥端4bよりも僅かに広がっている。
(Embodiment 2)
FIG. 4 shows (Embodiment 2) of the present invention.
In FIG. 1, the second electrode 4 has the same diameter from the opening 4a to the back end, but in FIG. 4A, the opening 4a of the second electrode 4 is slightly wider than the back end 4b.

このように構成した場合には、第1電極2の先端を第2電極4に挿入しやすく、作業性が良好である。図4(b)はこの場合の実装完了状態を示している。
(実施の形態3)
図5は本発明の(実施の形態3)を示す。
When configured in this way, it is easy to insert the tip of the first electrode 2 into the second electrode 4 and the workability is good. FIG. 4B shows a mounting completion state in this case.
(Embodiment 3)
FIG. 5 shows (Embodiment 3) of the present invention.

図1では第1電極2は先端から基端にかけて同一径であったが、この図5(a)では、第1電極2の先端2aが僅かに細く形成されている。例えば第1電極2の先端の角部の面取りが行われている。   In FIG. 1, the first electrode 2 has the same diameter from the distal end to the proximal end, but in FIG. 5A, the distal end 2 a of the first electrode 2 is formed to be slightly thin. For example, the chamfering of the corner of the tip of the first electrode 2 is performed.

このように構成した場合には、第1電極2の先端を第2電極4に挿入しやすく、作業性が良好である。図5(b)はこの場合の実装完了状態を示している。
(実施の形態4)
図6は本発明の(実施の形態4)を示す。
When configured in this way, it is easy to insert the tip of the first electrode 2 into the second electrode 4 and the workability is good. FIG. 5B shows a mounting completion state in this case.
(Embodiment 4)
FIG. 6 shows (Embodiment 4) of the present invention.

図1では第1電極2は先端から基端にかけて同一径、第2電極4は凹部の開口部4aから奥端4bにかけて同一径であったが、この図6(a)では、第1電極2の先端が僅かに細く形成され、かつ第2電極4の開口部4aが奥端4bよりも僅かに広がっている。   In FIG. 1, the first electrode 2 has the same diameter from the front end to the base end, and the second electrode 4 has the same diameter from the opening 4a to the back end 4b of the recess, but in FIG. The tip of the second electrode 4 is slightly narrowed, and the opening 4a of the second electrode 4 is slightly wider than the back end 4b.

このように構成した場合には、第1電極2の先端を第2電極4にさらに挿入しやすく、作業性が良好である。図6(b)はこの場合の実装完了状態を示している。
(実施の形態5)
図7は本発明の(実施の形態5)を示す。
When configured in this way, the tip of the first electrode 2 can be more easily inserted into the second electrode 4 and the workability is good. FIG. 6B shows the mounting completion state in this case.
(Embodiment 5)
FIG. 7 shows (Embodiment 5) of the present invention.

図1では第2電極4の内周面は第1電極2の外周面と同じく滑らかであったが、この図7(a)では、第2電極4の内周面は第1電極2の外周面の表面粗さよりも粗く形成されている。図7(b)はこの場合の実装完了状態を示しており、第2電極4の内周面がより確実に第1電極2に接触して接触抵抗の低減に効果的である。   In FIG. 1, the inner peripheral surface of the second electrode 4 is as smooth as the outer peripheral surface of the first electrode 2, but in FIG. 7A, the inner peripheral surface of the second electrode 4 is the outer periphery of the first electrode 2. The surface is rougher than the surface roughness. FIG. 7B shows a state of completion of mounting in this case, and the inner peripheral surface of the second electrode 4 comes into contact with the first electrode 2 more reliably and is effective in reducing contact resistance.

なお、(実施の形態2)〜(実施の形態4)においても同様に実施できる。
(実施の形態6)
図8は本発明の(実施の形態6)を示す。
Note that the same can be applied to (Embodiment 2) to (Embodiment 4).
(Embodiment 6)
FIG. 8 shows (Embodiment 6) of the present invention.

ここでは図8(a)に示したように、第2電極4の内周面は、開口部4aから第1電極2の外周面と同じく滑らかで、続いて奥端4bにかけて第2電極4の内周面は第1電極2の外周面の表面粗さよりも粗く形成されている。図8(b)はこの場合の実装完了状態を示しており、第1電極2の先端を第2電極4に挿入しやすく、より良好な電気接続が得られた。   Here, as shown in FIG. 8 (a), the inner peripheral surface of the second electrode 4 is as smooth as the outer peripheral surface of the first electrode 2 from the opening 4a, and then continues to the back end 4b. The inner peripheral surface is formed to be rougher than the surface roughness of the outer peripheral surface of the first electrode 2. FIG. 8B shows a state where the mounting is completed in this case. The tip of the first electrode 2 can be easily inserted into the second electrode 4, and a better electrical connection can be obtained.

なお、(実施の形態2)〜(実施の形態4)においても同様に実施できる。
(実施の形態7)
図9と図12(b)は本発明の(実施の形態7)を示す。
Note that the same can be applied to (Embodiment 2) to (Embodiment 4).
(Embodiment 7)
9 and 12 (b) show (Embodiment 7) of the present invention.

図1では配線基板3に形成された各第2電極4は図12(a)に示すように、それぞれ独立した凹部に形成されていたが、この実施の形態では図9(a)と図12(b)に示すように、各第2電極4で共通の凹部17の内側に、スパッタリングと蒸着によって形成したAuの第2電極4が形成されている。この第2電極4は端子電極10の上面に密着した水平部4hとこの水平部4hから垂直に形成された側面部4vとで構成されている。第2電極4の外側には未硬化の絶縁膜層11が形成されている。   In FIG. 1, each second electrode 4 formed on the wiring board 3 is formed in an independent recess as shown in FIG. 12A, but in this embodiment, FIG. 9A and FIG. As shown in (b), the Au second electrode 4 formed by sputtering and vapor deposition is formed inside the concave portion 17 common to the second electrodes 4. The second electrode 4 includes a horizontal portion 4h that is in close contact with the upper surface of the terminal electrode 10 and a side surface portion 4v that is formed perpendicular to the horizontal portion 4h. An uncured insulating film layer 11 is formed outside the second electrode 4.

図2に示したように製作した半導体素子1の第1電極2の先端を、このように製作した配線基板3に図9(b)に示すように挿入し、例えば配線基板3を加熱して未硬化の絶縁膜層11を硬化させる。硬化が始まると絶縁膜層11は収縮して第2電極4が収縮した絶縁膜層11によって内側に向かって圧縮される。   The tip of the first electrode 2 of the semiconductor element 1 manufactured as shown in FIG. 2 is inserted into the wiring board 3 thus manufactured as shown in FIG. 9B, and the wiring board 3 is heated, for example. The uncured insulating film layer 11 is cured. When curing begins, the insulating film layer 11 contracts and the second electrode 4 is compressed inward by the contracted insulating film layer 11.

この圧縮によって第2電極4の側面部4vが変形して第1電極2の外周側に押し付けられて確実な導通状態が得られる。図9(c)はこの場合の実装完了状態を示しており、この状態では配線基板3と半導体素子1の間に熱膨張係数の差があっても、せん断歪みによる導通不良は従来に比べて低減できた。   By this compression, the side surface portion 4v of the second electrode 4 is deformed and pressed against the outer peripheral side of the first electrode 2, and a reliable conduction state is obtained. FIG. 9C shows a completed state of mounting in this case, and in this state, even if there is a difference in thermal expansion coefficient between the wiring board 3 and the semiconductor element 1, the conduction failure due to shear strain is smaller than in the conventional case. Reduced.

なお、(実施の形態2)〜(実施の形態7)においても同様に実施できる。
(実施の形態8)
図10は本発明の(実施の形態8)を示す。
The same applies to (Embodiment 2) to (Embodiment 7).
(Embodiment 8)
FIG. 10 shows (Embodiment 8) of the present invention.

図1では半導体素子1の第1電極2を配線基板3の第2電極4に挿入する際には、第2電極4の凹部には何も入れられていなかったが、この実施の形態では図10(a)に示すように、第2電極4の凹部に第1電極2を挿入する前に、第2電極4の凹部に適量の接着材または導電性材料またはクリーム半田などの材料18を入れることによって、図10(b)に示す実装完了状態では凹部に適量の材料11を入れることによってより良好な導通状態安定して維持できる。   In FIG. 1, when the first electrode 2 of the semiconductor element 1 is inserted into the second electrode 4 of the wiring substrate 3, nothing is put in the recess of the second electrode 4. As shown in FIG. 10 (a), before inserting the first electrode 2 into the recess of the second electrode 4, an appropriate amount of an adhesive material, conductive material, or material such as cream solder is put into the recess of the second electrode 4. Thus, in the mounting completion state shown in FIG. 10 (b), an appropriate amount of the material 11 can be put in the recess to stably maintain a better conduction state.

なお、(実施の形態2)〜(実施の形態7)においても同様に実施できる。
上記の各実施の形態において第1電極2は円柱形であったが、三角柱または四角柱またはそれ以上の多角柱などであっても同様に実施できる。
The same applies to (Embodiment 2) to (Embodiment 7).
In each of the embodiments described above, the first electrode 2 has a cylindrical shape. However, the first electrode 2 can be similarly implemented even if it is a triangular prism, a quadrangular prism, or a polygonal prism having more than that.

(実施の形態9)
図11は本発明の(実施の形態9)を示す。
図1では半導体素子1に凸状の第1電極2を形成し、配線基板3に凹部を有する第2電極4を設けたが、配線基板3の接続電極10に凸状の第2電極40を設け、半導体素子1に凹部を有する第1電極20を設けても同様に実施できる。具体的には、図11(a)に示すように配線基板3の実装位置に形成された凸状の第2電極40に対応して、半導体素子1には凹部が形成された第1電極20と、この第1電極20の外側に配置された未硬化の絶縁膜層11を形成し、図11(b)に示すように第1電極20の凹部に第2電極40を挿入した状態で、例えば半導体素子1を加熱して未硬化の絶縁膜層11を硬化させる。硬化が始まると絶縁膜層11は収縮して第1電極20が収縮した絶縁膜層11によって内側に向かって圧縮される。
(Embodiment 9)
FIG. 11 shows (Embodiment 9) of the present invention.
In FIG. 1, the convex first electrode 2 is formed on the semiconductor element 1, and the second electrode 4 having a concave portion is provided on the wiring board 3. However, the convex second electrode 40 is provided on the connection electrode 10 of the wiring board 3. Even if the first electrode 20 having a recess is provided in the semiconductor element 1, the same can be implemented. Specifically, as shown in FIG. 11A, the first electrode 20 in which a concave portion is formed in the semiconductor element 1 corresponding to the convex second electrode 40 formed at the mounting position of the wiring board 3. And forming the uncured insulating film layer 11 disposed outside the first electrode 20 and inserting the second electrode 40 into the recess of the first electrode 20 as shown in FIG. For example, the semiconductor element 1 is heated to cure the uncured insulating film layer 11. When curing starts, the insulating film layer 11 contracts and the first electrode 20 is compressed inward by the contracted insulating film layer 11.

この圧縮によって第1電極20は変形して第2電極40の外周側に押し付けられて確実な導通状態が得られる。図11(c)はこの場合の実装完了状態を示しており、この状態では配線基板3と半導体素子1の間に熱膨張係数の差があってもせん断歪みによる導通不良は従来に比べて低減できた。   By this compression, the first electrode 20 is deformed and pressed against the outer peripheral side of the second electrode 40 to obtain a reliable conduction state. FIG. 11C shows a state where the mounting is completed in this case, and in this state, even if there is a difference in thermal expansion coefficient between the wiring board 3 and the semiconductor element 1, conduction failure due to shear strain is reduced as compared with the conventional case. did it.

なお、この(実施の形態9)の凸状の電極と凹部を有する電極においても同様に(実施の形態2)〜(実施の形態8)を実施することができる。   It should be noted that (Embodiment 2) to (Embodiment 8) can be implemented in the same manner (Embodiment 9) on the convex electrode and the electrode having a recess.

本発明はフリップチップ実装などに使用して特に有効である。   The present invention is particularly effective when used for flip chip mounting and the like.

本発明の半導体素子の実装方法の(実施の形態1)の工程図Process drawing of (Embodiment 1) of the mounting method of the semiconductor element of this invention 同実施の形態の第1電極の形成工程図Process of forming first electrode of the embodiment 同実施の形態の第2電極の形成工程図Process of forming second electrode of the embodiment 本発明の半導体素子の実装方法の(実施の形態2)の要部工程図Process diagram of principal part of (embodiment 2) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態3)の要部工程図Process diagram of principal part of (embodiment 3) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態4)の要部工程図Process diagram of principal part of (embodiment 4) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態5)の要部工程図Process diagram of principal part of (embodiment 5) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態6)の要部工程図Process diagram of principal part of (embodiment 6) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態7)の要部工程図Process diagram of principal part of (embodiment 7) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態8)の要部工程図Principal part process diagram of (Embodiment 8) of mounting method of semiconductor element of the present invention 本発明の半導体素子の実装方法の(実施の形態9)の要部工程図Principal part process diagram of (Embodiment 9) of semiconductor device mounting method of the present invention 本発明の半導体素子の実装方法の(実施の形態1)と(実施の形態7)の平面図Plan views of (Embodiment 1) and (Embodiment 7) of the semiconductor element mounting method of the present invention

符号の説明Explanation of symbols

1 半導体素子
2 凸状の第1電極
2a 第1電極2の先端
2b Au膜
3 配線基板
4 凹部を有する第2電極
4a 第2電極4の開口部
4b 第2電極4の奥端
4h 第2電極4の水平部
4v 第2電極4の側面部
5 端子電極
6 レジスト
7 マスク
8 透過窓
9 孔
10 接続電極
11 未硬化の絶縁膜層
12 レジスト
13 マスク
14 透過窓
15 孔
16 Au膜
17 第2電極4で共通の凹部
18 接着材または導電性材料またはクリーム半田などの材料
20 凹部を有する第1電極
40 凸状の第2電極
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Convex-shaped 1st electrode 2a The tip of 1st electrode 2b Au film 3 Wiring board 4 The 2nd electrode which has a recessed part 4a The opening part of 2nd electrode 4b The back end of 2nd electrode 4h 2nd electrode 4 horizontal portion 4 v side surface of second electrode 4 5 terminal electrode 6 resist 7 mask 8 transmission window 9 hole 10 connection electrode 11 uncured insulating film layer 12 resist 13 mask 14 transmission window 15 hole 16 Au film 17 second electrode 4 common concave portion 18 Adhesive material or conductive material or material 20 such as cream solder First electrode 40 having concave portion Convex second electrode

Claims (8)

半導体素子に形成された第1電極と配線基板に形成された第2電極とが導通状態となるように前記半導体素子を前記配線基板に実装するに際し、
前記配線基板における前記半導体素子の実装位置に、前記半導体素子に形成された凸状の前記第1電極に対応して凹部が形成された前記第2電極とこの第2電極の外側に配置された未硬化の絶縁膜層を形成し、
前記第2電極の凹部に前記第1電極を挿入した状態で前記配線基板の前記絶縁膜層を収縮させて前記第1電極の外周側に前記第2電極を押し付けた状態で硬化させる
半導体素子の実装方法。
When mounting the semiconductor element on the wiring board so that the first electrode formed on the semiconductor element and the second electrode formed on the wiring board are in a conductive state,
The second electrode having a concave portion corresponding to the convex first electrode formed in the semiconductor element and the outside of the second electrode are disposed at the mounting position of the semiconductor element on the wiring board. Form an uncured insulating film layer,
A semiconductor element that is cured in a state in which the insulating film layer of the wiring substrate is contracted in a state where the first electrode is inserted into a recess of the second electrode and the second electrode is pressed against an outer peripheral side of the first electrode. Implementation method.
半導体素子に形成された第1電極と配線基板に形成された第2電極とが導通状態となるように前記半導体素子を前記配線基板に実装するに際し、
前記配線基板の実装位置に形成された凸状の前記第2電極に対応して、前記半導体素子には凹部が形成された前記第1電極とこの第1電極の外側に配置された未硬化の絶縁膜層を形成し、前記第1電極の凹部に前記第2電極を挿入した状態で前記半導体素子の前記絶縁膜層を収縮させて前記第2電極の外周側に前記第1電極を押し付けた状態で硬化させる
半導体素子の実装方法。
When mounting the semiconductor element on the wiring board so that the first electrode formed on the semiconductor element and the second electrode formed on the wiring board are in a conductive state,
Corresponding to the convex second electrode formed at the mounting position of the wiring board, the semiconductor element has the first electrode in which a concave portion is formed and an uncured material disposed outside the first electrode. An insulating film layer is formed, and the first electrode is pressed against the outer peripheral side of the second electrode by contracting the insulating film layer of the semiconductor element in a state where the second electrode is inserted into the recess of the first electrode. A method for mounting a semiconductor element that is cured in a state.
凹部が形成された第2電極の内周面の少なくとも一部の表面粗さを、半導体素子に形成された第1電極の表面粗さよりも粗くする
請求項1記載の半導体素子の実装方法。
The method for mounting a semiconductor element according to claim 1, wherein the surface roughness of at least a part of the inner peripheral surface of the second electrode in which the recess is formed is made rougher than the surface roughness of the first electrode formed in the semiconductor element.
第1電極の先端を基端部よりも細くする
請求項1記載の半導体素子の実装方法。
The method for mounting a semiconductor element according to claim 1, wherein the tip of the first electrode is made thinner than the base end.
第2電極の凹部の形状を、奥端よりも開口部を広くする
請求項1記載の半導体素子の実装方法。
The semiconductor element mounting method according to claim 1, wherein the shape of the concave portion of the second electrode is wider than the back end.
前記第2電極の凹部に前記第1電極を挿入する前に、前記第2電極の凹部に接着材または導電性材料またはクリーム半田などの材料を入れる
請求項1記載の半導体素子の実装方法。
The method for mounting a semiconductor element according to claim 1, wherein a material such as an adhesive, a conductive material, or cream solder is placed in the recess of the second electrode before the first electrode is inserted into the recess of the second electrode.
第1電極が凸状の形成された半導体素子と、
配線基板における前記半導体素子の実装位置に前記第1電極に対応して凹部が形成された前記第2電極とこの第2電極の外側に配置された絶縁膜層が形成された配線基板と
を有し、未硬化の前記絶縁膜層に形成された凹部の内側に導電材料を蒸着して形成された前記第2電極の凹部に、前記第1電極を挿入した状態で前記配線基板の前記絶縁膜層を収縮させて硬化し前記第1電極の外周側に前記第2電極を押し付けて導通状態に実装した
実装体。
A semiconductor element in which the first electrode is formed in a convex shape;
The wiring board includes the second electrode in which a recess is formed corresponding to the first electrode at the mounting position of the semiconductor element, and the wiring board in which an insulating film layer disposed outside the second electrode is formed. The insulating film of the wiring board in a state where the first electrode is inserted into the concave portion of the second electrode formed by depositing a conductive material inside the concave portion formed in the uncured insulating film layer. A mounting body in which a layer is contracted and cured, and the second electrode is pressed against the outer peripheral side of the first electrode and mounted in a conductive state.
凹状の形成された第1電極とこの第1電極の外側に配置された絶縁膜層が形成された半導体素子と、
前記半導体素子の実装位置に前記第1電極に対応して凸状の第2電極が形成された配線基板と
を有し、未硬化の前記絶縁膜層に形成された凹部の内側に導電材料を蒸着して形成された前記第1電極の凹部に、前記第2電極を挿入した状態で半導体素子の前記絶縁膜層を収縮させて硬化し前記第2電極の外周側に前記第1電極を押し付けて導通状態に実装した
実装体。
A semiconductor element in which a concavely formed first electrode and an insulating film layer disposed outside the first electrode are formed;
A wiring board having a convex second electrode formed corresponding to the first electrode at a mounting position of the semiconductor element, and a conductive material inside the concave portion formed in the uncured insulating film layer. The insulating film layer of the semiconductor element is contracted and cured in a state where the second electrode is inserted into the concave portion of the first electrode formed by vapor deposition, and the first electrode is pressed against the outer peripheral side of the second electrode. Mounting body mounted in a conductive state.
JP2005052176A 2005-02-28 2005-02-28 Mounting method for semiconductor element Pending JP2006237410A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010531003A (en) * 2007-05-25 2010-09-16 ジエマルト・エス・アー Method for processing application commands from physical channels using portable electronic devices and corresponding devices and systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010531003A (en) * 2007-05-25 2010-09-16 ジエマルト・エス・アー Method for processing application commands from physical channels using portable electronic devices and corresponding devices and systems

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