JP2006237180A - Method of forming photovoltaic device - Google Patents

Method of forming photovoltaic device Download PDF

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JP2006237180A
JP2006237180A JP2005048142A JP2005048142A JP2006237180A JP 2006237180 A JP2006237180 A JP 2006237180A JP 2005048142 A JP2005048142 A JP 2005048142A JP 2005048142 A JP2005048142 A JP 2005048142A JP 2006237180 A JP2006237180 A JP 2006237180A
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forming
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semiconductor layer
transparent electrode
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Naoto Okada
直人 岡田
Tokuji Yasuno
篤司 保野
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Canon Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a photovoltaic device which can prevent the degradation of characteristics with the passage of time due to the long-time film formation by a deposition film formation apparatus, can minimize the variation in characteristics at the time of mass-production, can manufacture a photovoltaic power device having a high photoelectric conversion efficiency stably with a high productivity. <P>SOLUTION: The photovoltaic device has a structure wherein a rear electrode 202, semiconductor layers 203, 204, and 205, and a transparent electrode 206 are stacked in order on a substrate 201. In forming the photovoltaic power device, the formation conditions for the transparent electrode are set based on the value of self-bias voltage generated at the time of forming the semiconductor layers. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、例えばアモルファスシリコンまたは微結晶シリコン等の非単結晶半導体を用いた光起電力素子の形成方法に関するものである。   The present invention relates to a method for forming a photovoltaic element using a non-single crystal semiconductor such as amorphous silicon or microcrystalline silicon.

従来、太陽電池などとして用いられる光起電力素子としては、アモルファスシリコン(a−Si:H)に代表されるアモルファス材料または微結晶シリコン等の非単結晶半導体材料が、安価で、大面積化及び薄膜化が可能であり、組成の自由度が大きく、電気的及び光学的特性を広い範囲で制御できる等の理由から注目されている。このような素子の作製には、減圧条件下でプラズマCVD法により薄膜を形成する堆積膜形成装置が一般的に広く用いられており、産業に供されている。   Conventionally, as a photovoltaic element used as a solar cell or the like, an amorphous material typified by amorphous silicon (a-Si: H) or a non-single-crystal semiconductor material such as microcrystalline silicon is inexpensive, has a large area and It is attracting attention because it can be made thin, has a high degree of freedom in composition, and can control electrical and optical characteristics over a wide range. For the production of such an element, a deposited film forming apparatus for forming a thin film by a plasma CVD method under a reduced pressure condition is generally widely used and used in industry.

太陽電池は、光電変換効率が十分に高く、特性の安定性に優れ、かつ大量生産し得るものであることが基本的に重要である。そこで、非単結晶半導体層などを用いた太陽電池の作製においては、作製する太陽電池の電気的、光学的、光導電的、機械的特性、および繰り返し使用に対する疲労特性、使用環境に対する耐性の向上を図るとともに、より大きな面積を有し、太陽電池を構成する半導体層の膜厚および膜質がより均一な光起電力素子を、再現性のある方法で、高速で成膜して量産できるようにすることが求められている。   It is fundamentally important that solar cells have sufficiently high photoelectric conversion efficiency, excellent characteristics stability, and can be mass-produced. Therefore, in the production of solar cells using non-single-crystal semiconductor layers, etc., the electrical, optical, photoconductive, mechanical properties, fatigue properties against repeated use, and resistance to usage environments are improved. In addition, a photovoltaic device having a larger area and a more uniform film thickness and film quality of the semiconductor layer constituting the solar cell can be formed and mass-produced by a reproducible method at high speed. It is requested to do.

太陽電池において、その重要構成要素である半導体層は、いわゆるpn接合、pin接合などの半導体接合がなされている。a−Siなどの薄膜状の半導体を用いる場合、ホスフィン(PH3)、ジボラン(B26)などのドーパントとなる元素を含むガスとシラン(SiH4)などを混合してグロー放電することにより原料ガスを分解し、熱せられた固体表面上に付着成長させる(プラズマCVD法)ことにより所望の導電型を有する半導体層が得られる。 In a solar cell, a semiconductor layer which is an important constituent element has a semiconductor junction such as a so-called pn junction or pin junction. When a thin-film semiconductor such as a-Si is used, a glow discharge is performed by mixing a gas containing an element serving as a dopant such as phosphine (PH 3 ) or diborane (B 2 H 6 ) with silane (SiH 4 ). The semiconductor layer having a desired conductivity type can be obtained by decomposing the source gas and growing it on a heated solid surface (plasma CVD method).

このようにして、所望の基板上に所望の導電型の半導体層を順次積層させることによって、これらの半導体膜を容易に半導体接合させられることが知られている。このことから、非単結晶半導体層を積層して得られる太陽電池の作製方法として、各々の半導体層を作製するための独立した半導体層作製用容器を設け、この半導体層作製用容器にて各々の半導体層の作製を順次行うことにより所望の半導体接合がなされた半導体層の積層体を作製する方法が提案されている。   Thus, it is known that these semiconductor films can be easily semiconductor-bonded by sequentially laminating semiconductor layers of a desired conductivity type on a desired substrate. Thus, as a method for manufacturing a solar cell obtained by stacking non-single-crystal semiconductor layers, an independent semiconductor layer manufacturing container for manufacturing each semiconductor layer is provided, and each of these semiconductor layer manufacturing containers is provided with There has been proposed a method of manufacturing a stacked body of semiconductor layers in which desired semiconductor junctions are formed by sequentially manufacturing the semiconductor layers.

例えば、一般には前記の独立した半導体層作製用容器がゲートバルブを介したロードロック方式にて連結され、基板を各容器へ順次移動させて各種半導体層を形成する方法が知られている。   For example, generally, there is known a method in which the independent semiconductor layer manufacturing containers are connected by a load lock system via a gate valve, and a substrate is sequentially moved to each container to form various semiconductor layers.

さらに量産性を著しく向上させる方法として、特許文献1には、ロール・ツー・ロール(Roll to Roll)方式を採用した連続プラズマCVD装置が開示されている。この装置は、グロー放電を行い半導体層を形成するためのグロー放電領域が複数設けられた搬送経路において、所望の幅を有し、かつ十分な長さを有する可撓性の基板を連続的に搬送し、各グロー放電領域において、必要とされる導電型の半導体層を基板に順次堆積させることにより、半導体接合された複数の半導体層を有するデバイスを連続作製する装置である。   Furthermore, as a method for significantly improving mass productivity, Patent Document 1 discloses a continuous plasma CVD apparatus that employs a roll-to-roll method. This apparatus continuously forms a flexible substrate having a desired width and a sufficient length in a transport path provided with a plurality of glow discharge regions for performing glow discharge to form a semiconductor layer. It is an apparatus that continuously manufactures a device having a plurality of semiconductor layers semiconductor-bonded by sequentially transporting and depositing necessary conductive semiconductor layers on a substrate in each glow discharge region.

しかしながら、このような光起電力素子の量産装置においては、大面積で長時間にわたってプラズマを発生させることにより電極表面への膜の堆積が徐々に起こり、電力投入の条件が変化するという問題があった。これは堆積膜厚の増加により、電極のインピーダンスが変化し、膜形成速度が低下していくものである。   However, in such a mass production apparatus for photovoltaic elements, there is a problem that a film is gradually deposited on the electrode surface by generating plasma over a long time in a large area, and the condition of power input changes. It was. This is because the impedance of the electrode changes as the deposited film thickness increases, and the film formation rate decreases.

この問題に関して特許文献2には、高周波電極に生じるセルフバイアス電圧(Vdc)が一定値となるように投入電力を調整することを特徴とする膜形成方法について述べられている。この方法は成膜初期、あるいはセルフバイアス電圧絶対値が小さい場合の成膜には有効である。   Regarding this problem, Patent Document 2 describes a film forming method characterized in that input power is adjusted so that a self-bias voltage (Vdc) generated in a high-frequency electrode becomes a constant value. This method is effective for film formation at the beginning of film formation or when the absolute value of the self-bias voltage is small.

しかし、基板の処理速度を上げる際の更なる高いパワー印加あるいは長時間にわたる処理が必要とされる膜形成時や量産装置では、セルフバイアス電圧の絶対値ならびに変化量が大きくなるため制御が困難であり、セルフバイアス電圧の変化および膜形成速度の低下に伴う特性の低下が発生していた。特にi型半導体層成膜時の膜形成速度の低下に伴う膜厚減少は太陽電池特性である短絡電流(Isc)の減少を引き起こし、変換効率の低下に大きく影響している。   However, in film formation and mass production equipment that require higher power application or longer processing time to increase the processing speed of the substrate, the absolute value and change amount of the self-bias voltage become large and control is difficult. In other words, the characteristics deteriorated as the self-bias voltage changed and the film formation rate decreased. In particular, a decrease in film thickness accompanying a decrease in film formation rate during the formation of an i-type semiconductor layer causes a decrease in short circuit current (Isc), which is a solar cell characteristic, and greatly affects the decrease in conversion efficiency.

このような問題は光活性層であるi型半導体層が光吸収を担うことから多くの膜厚を必要とし、それを形成する電極への膜付着が著しく早く、かつ多量である事に起因する。すなわちi型半導体層を形成する装置においては電極インピーダンスや排気コンダクタンス等の成膜条件の変化が激しいことを意味する。このような状況において、最終的に安定した特性の光起電力素子の量産を行うにはi型半導体層形成時の制御だけに頼る方法では限界がある。   Such a problem is caused by the fact that the i-type semiconductor layer, which is a photoactive layer, is responsible for light absorption, requires a large film thickness, and the film adheres to the electrode forming it extremely quickly and in large quantities. . That is, in an apparatus for forming an i-type semiconductor layer, it means that a change in film forming conditions such as electrode impedance and exhaust conductance is severe. Under such circumstances, there is a limit to a method that relies solely on the control at the time of forming the i-type semiconductor layer in order to finally produce a photovoltaic device having stable characteristics.

米国特許第4,400,409号特許明細書US Patent No. 4,400,409 Patent Specification 特開平11−233443号公報Japanese Patent Laid-Open No. 11-233443

本発明は、上述したような堆積膜形成装置における長時間成膜による経時的な特性低下を防止し、量産時における特性のばらつきを最小限に抑えることにより、光電変換効率の高い光起電力素子を安定して作製できる、生産性の高い光起電力素子の形成方法を提供することを目的とする。   The present invention provides a photovoltaic device having high photoelectric conversion efficiency by preventing deterioration of characteristics over time due to long-time film formation in the deposited film forming apparatus as described above, and minimizing variation in characteristics during mass production. It is an object of the present invention to provide a method for forming a photovoltaic element with high productivity that can be stably manufactured.

上記の目的を達成すべく本発明では、基板上に裏面電極、半導体層、透明電極の順で積層された構造からなる光起電力素子の形成方法において、前記半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、前記透明電極の形成条件を設定することを特徴とする。
また、本発明では、基板上に透明電極、半導体層、裏面電極の順で積層された構造からなる光起電力素子を少なくとも2個以上形成する方法において、第n(nは1以上の整数)番目の基板上に半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、第n+1番目の基板上に形成する透明電極の形成条件を設定することを特徴とする。
また、本発明の光起電力素子の形成方法において、前記透明電極の形成条件が、印加パワー、印加電圧、印加電流、形成時間、ガス流量、形成温度、堆積速度、またはベーキング時間の中から選ばれる少なくとも1つ以上であることを特徴とする。
In order to achieve the above object, in the present invention, in the method of forming a photovoltaic device having a structure in which a back electrode, a semiconductor layer, and a transparent electrode are laminated in this order on a substrate, self-generated when the semiconductor layer is formed. The transparent electrode forming condition is set based on a bias voltage value.
In the present invention, in a method of forming at least two photovoltaic elements having a structure in which a transparent electrode, a semiconductor layer, and a back electrode are laminated in this order on a substrate, the nth (n is an integer of 1 or more) The formation conditions of the transparent electrode formed on the (n + 1) th substrate are set based on the self-bias voltage value generated when the semiconductor layer is formed on the th substrate.
Further, in the method for forming a photovoltaic device of the present invention, the formation condition of the transparent electrode is selected from applied power, applied voltage, applied current, formation time, gas flow rate, formation temperature, deposition rate, or baking time. It is characterized by being at least one or more.

また、本発明では、基板上に裏面電極、半導体層、透明電極の順で積層された構造からなる光起電力素子の形成方法において、前記半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、前記透明電極の膜厚、または透過率を設定することを特徴とする。   According to the present invention, in the method for forming a photovoltaic device having a structure in which a back electrode, a semiconductor layer, and a transparent electrode are stacked in this order on a substrate, based on a self-bias voltage value generated when the semiconductor layer is formed. The film thickness or transmittance of the transparent electrode is set.

また、本発明では、基板上に透明電極、半導体層、裏面電極の順で積層された構造からなる光起電力素子を少なくとも2個以上形成する方法において、第n(nは1以上の整数)番目の基板上に半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、第n+1番目の基板上に形成する透明電極の膜厚、または透過率を設定することを特徴とする。   In the present invention, in a method of forming at least two photovoltaic elements having a structure in which a transparent electrode, a semiconductor layer, and a back electrode are laminated in this order on a substrate, the nth (n is an integer of 1 or more) The film thickness or transmittance of the transparent electrode formed on the (n + 1) th substrate is set based on the self-bias voltage value generated when the semiconductor layer is formed on the th substrate.

また、本発明の光起電力素子の形成方法において、前記半導体層を形成する際に生じるセルフバイアス電圧値と前記光起電力素子の短絡電流との関係に基づいて、前記透明電極の形成条件もしくは膜厚または透過率を設定することを特徴とする。   Further, in the method for forming a photovoltaic element of the present invention, based on the relationship between the self-bias voltage value generated when forming the semiconductor layer and the short-circuit current of the photovoltaic element, the formation conditions of the transparent electrode or The film thickness or transmittance is set.

本発明の光起電力素子の形成方法によれば、例えば堆積膜形成装置での長時間成膜による経時的な特性低下を防止し、量産時における特性のばらつきを最小限に抑えることができ、光電変換効率の高い光起電力素子を安定して生産性良く作製することができる。   According to the method for forming a photovoltaic element of the present invention, for example, it is possible to prevent deterioration of characteristics over time due to long-time film formation in a deposited film forming apparatus, and to minimize variation in characteristics during mass production. A photovoltaic element with high photoelectric conversion efficiency can be stably produced with high productivity.

以下に図を用いて、本発明について詳細に説明するが、本発明の光起電力素子形成方法はこれにより何ら限定されるものではない。   Hereinafter, the present invention will be described in detail with reference to the drawings. However, the photovoltaic element forming method of the present invention is not limited thereto.

図1は、本発明の光起電力素子の半導体層を形成するための堆積膜形成装置の一例を模式的に示す概略図である。   FIG. 1 is a schematic view schematically showing an example of a deposited film forming apparatus for forming a semiconductor layer of a photovoltaic element of the present invention.

図1において、放電空間である内反応容器100は外反応容器110の内部に設置されている。外反応容器110に設置されているヒーター102に密着するように基板101を設置し、不図示の排気装置を用いて排気管109から真空排気した後、基板101を所望の温度まで加熱する。基板温度が安定したところでガス導入バルブ107を開け、マスフローコントローラー108で流量を調整し、ガス導入管106を介してシリコン原子を含有する原料ガスを内反応容器100(放電空間)内に導入する。   In FIG. 1, an inner reaction vessel 100, which is a discharge space, is installed inside an outer reaction vessel 110. The substrate 101 is installed so as to be in close contact with the heater 102 installed in the outer reaction vessel 110, and after evacuating from the exhaust pipe 109 using an exhaust device (not shown), the substrate 101 is heated to a desired temperature. When the substrate temperature is stabilized, the gas introduction valve 107 is opened, the flow rate is adjusted by the mass flow controller 108, and the source gas containing silicon atoms is introduced into the inner reaction vessel 100 (discharge space) through the gas introduction tube 106.

次に、高周波電源104より高周波電力をカソード電極103に印加し、プラズマを生起させる。その際、容器壁と基板はともに接地されているためプラズマは反応容器内に一様に広がる。またカソード電極に生じるセルフバイアス電圧はセルフバイアス電圧読取器105で常時モニターされている。   Next, high frequency power is applied to the cathode electrode 103 from the high frequency power source 104 to generate plasma. At that time, since the vessel wall and the substrate are both grounded, the plasma spreads uniformly in the reaction vessel. The self-bias voltage generated at the cathode electrode is constantly monitored by a self-bias voltage reader 105.

このセルフバイアス電圧はカソード電極への膜堆積量が増加するにつれて、徐々に変化していく。特に量産装置の場合には、処理基板が連続して反応容器に投入されて長時間にわたり成膜されるため、後半に処理される基板の場合は成膜開始時の基板に比べてカソード電極への膜堆積量が多くなっており、セルフバイアス電圧値が大きく変化した状態で処理されている。   This self-bias voltage gradually changes as the amount of film deposition on the cathode electrode increases. In particular, in the case of a mass production apparatus, a processing substrate is continuously put into a reaction vessel and a film is formed over a long period of time. Therefore, in the case of a substrate processed in the latter half, the cathode electrode is compared to the substrate at the start of film formation. The film is deposited in a large amount, and the self-bias voltage value is greatly changed.

具体的には膜堆積量の増加により電極のインピーダンスが変化し、セルフバイアス電圧値の変化と共に膜形成速度が低下すると考えられる。そのため、反応容器クリーニング直後に処理された基板と成膜を繰り返した後に処理された基板とでは半導体層の膜厚に差ができており、特に非単結晶太陽電池においてはi型半導体層の膜厚低下がもたらす成膜後半での短絡電流(Isc)低下が顕著であった。   Specifically, it is considered that the impedance of the electrode changes due to an increase in the amount of film deposition, and the film formation rate decreases as the self-bias voltage value changes. Therefore, there is a difference in the film thickness of the semiconductor layer between the substrate processed immediately after cleaning the reaction vessel and the substrate processed after repeating the film formation, and particularly in the case of a non-single crystal solar cell, the film of the i-type semiconductor layer The decrease in short circuit current (Isc) in the latter half of the film formation caused by the decrease in thickness was significant.

そこで本発明の光起電力素子形成方法においてはこのセルフバイアス電圧値に基いて、膜厚減少に起因する短絡電流を見積もり、形成された半導体層に最適な膜厚または透過率を有する透明電極を形成することにより特性の低下を防止し光起電力素子として最終的に良好な状態を維持するというものである。   Therefore, in the photovoltaic element forming method of the present invention, based on this self-bias voltage value, a short-circuit current due to the film thickness reduction is estimated, and a transparent electrode having an optimal film thickness or transmittance is formed for the formed semiconductor layer. By forming, the deterioration of characteristics is prevented, and finally a good state as a photovoltaic element is maintained.

以下、本発明の光起電力素子形成方法で非単結晶太陽電池を作製した場合について述べる。   Hereinafter, the case where a non-single-crystal solar cell is produced by the photovoltaic element forming method of the present invention will be described.

まず、i型半導体層形成工程においてチャンバークリーニングを行わない状態で連続してi型半導体層の成膜を行いその際のセルフバイアス電圧値の変化を記録しておく。次にDCスッパタリング装置によりそれぞれの素子に同じ条件でITO(In23+SnO2)の透明電極を形成する。この作製された非単結晶太陽電池の短絡電流(Isc)を測定しi型半導体層の成膜時のセルフバイアス電圧と短絡電流(Isc)との関係を求める。さらにこの工程を透明電極の光透過量が上がる様に透明電極の形成条件を変更して複数回行い、透明電極の形成条件をパラメーターとしてi型半導体層の成膜時セルフバイアス電圧と短絡電流(Isc)との関係の組み合わせのデータセットを完成させる。そして実際の光起電力素子形成工程においてi型半導体層成膜中のセルフバイアス電圧を検出し記録し、このセルフバイアス電圧値データと先のデータセットから所望の短絡電流(Isc)になる透明電極の形成条件を選び、その条件に従って透明電極を形成することによりセルフバイアスの変化によるi型半導体層膜厚低下分が補償された短絡電流(Isc)を持つ太陽電池が得られる。 First, in the i-type semiconductor layer forming step, the i-type semiconductor layer is continuously formed without performing chamber cleaning, and the change in the self-bias voltage value at that time is recorded. Next, a transparent electrode of ITO (In 2 O 3 + SnO 2 ) is formed on each element under the same conditions by a DC sputtering apparatus. The short-circuit current (Isc) of the manufactured non-single-crystal solar cell is measured to determine the relationship between the self-bias voltage and the short-circuit current (Isc) when forming the i-type semiconductor layer. Further, this process is performed a plurality of times while changing the formation conditions of the transparent electrode so as to increase the light transmission amount of the transparent electrode, and the self-bias voltage and the short-circuit current (when forming the i-type semiconductor layer) using the transparent electrode formation conditions as parameters. A data set of a combination of the relationship with Isc) is completed. A transparent electrode that detects and records the self-bias voltage during the formation of the i-type semiconductor layer in the actual photovoltaic element formation step, and obtains a desired short-circuit current (Isc) from the self-bias voltage value data and the previous data set. A solar cell having a short-circuit current (Isc) in which a decrease in the film thickness of the i-type semiconductor layer due to a change in self-bias is compensated can be obtained by selecting the formation conditions of and forming a transparent electrode according to the conditions.

また透明電極をi型半導体層よりも先に形成する構成の光起電力素子においては、あるロットのi型半導体層成膜時のセルフバイアス値から求められる透明電極形成条件をその次のロットの透明電極形成時に適用することにより同様の効果が得られる。   Further, in a photovoltaic device having a configuration in which the transparent electrode is formed before the i-type semiconductor layer, the transparent electrode formation condition obtained from the self-bias value at the time of film formation of the i-type semiconductor layer of a lot is set to the next lot. The same effect can be obtained by applying at the time of forming the transparent electrode.

本発明に利用できるその他の透明電極の材料としてはSnO2,In23,ZnO,CdO,CdSnO4などの酸化金属や、Au,Al,Cu等の金属を極めて薄く半透明状に成膜した金属薄膜等が挙げられる。またこれらの形成方法としては、抵抗加熱蒸着法、電子ビーム加熱蒸着法、スプレー法等も用いることができ、所望に応じて適宜選択される。 As other transparent electrode materials that can be used in the present invention, an oxide metal such as SnO 2 , In 2 O 3 , ZnO, CdO, and CdSnO 4 and a metal such as Au, Al, and Cu are formed in a very thin and translucent form. The metal thin film etc. which were made are mentioned. As these forming methods, resistance heating vapor deposition, electron beam heating vapor deposition, spraying, and the like can also be used, and they are appropriately selected as desired.

ここで、調整をする透明電極形成条件について説明する。前述のとおり、i型半導体層成膜時のセルフバイアス電圧値の変化は膜形成速度の低下を示している。すなわち光活性層の膜厚が薄くなり光吸収効率がさがる事により短絡電流(Isc)の低下を招くことから透明電極の光透過量を増やせばよい。このためには透明電極の膜厚を薄く、透過率(本発明でいう透過率は吸収率と同じ様に単位膜厚あたりの透過率である。)を上げればよい。   Here, the transparent electrode forming conditions to be adjusted will be described. As described above, a change in the self-bias voltage value during the formation of the i-type semiconductor layer indicates a decrease in the film formation rate. That is, since the thickness of the photoactive layer is reduced and the light absorption efficiency is reduced, the short-circuit current (Isc) is reduced, so that the light transmission amount of the transparent electrode may be increased. For this purpose, the film thickness of the transparent electrode is made thin and the transmittance (the transmittance in the present invention is the transmittance per unit film thickness in the same way as the absorption rate) may be increased.

膜厚を薄くするには膜形成速度を低くする方法が適している。これにはスパッタ法では投入電力の電圧、電流を下げればよい。また蒸着法においては加熱用電力の電圧、電流を下げることにより膜形成速度を下げることができる。さらに膜形成速度を変えずに膜形成時間を短くしてもよい。もちろん速度と時間の両方を組み合わせて膜厚を薄くしても構わない。   A method of reducing the film formation rate is suitable for reducing the film thickness. For this, in the sputtering method, the voltage and current of input power may be lowered. In the vapor deposition method, the film formation rate can be lowered by lowering the voltage and current of the heating power. Furthermore, the film formation time may be shortened without changing the film formation speed. Of course, the film thickness may be reduced by combining both speed and time.

また酸化金属では成膜時において種々の成膜条件を変更することで透過率をコントロールする事が可能である。まず成膜温度を上げることによりアモルファス相から結晶相への変化が起こることから成膜温度を上げると透過率は上がる。また酸素原子の供給を多くすることにより酸素空孔が減りそのためフリーキャリヤが減少し透過率が高くなる。酸素原子の供給方法としてはO2ガス、H2Oの導入が適している。すなわちO2ガス、H2Oの導入量を増やすことにより透過率を上げることができる。また通常、成膜装置メンテナンス後は装置内の壁面には水分が吸着しているためメンテナンス後のベーキング時間を変えることにより膜中へのH2O導入量を変えることができる。すなわちベーキング時間を短くすることにより透過率を上げることができる。 In the case of metal oxide, the transmittance can be controlled by changing various film formation conditions during film formation. First, a change from an amorphous phase to a crystalline phase occurs when the film formation temperature is raised. Therefore, when the film formation temperature is raised, the transmittance increases. Further, by increasing the supply of oxygen atoms, oxygen vacancies are reduced, so that free carriers are reduced and the transmittance is increased. As a method for supplying oxygen atoms, introduction of O 2 gas or H 2 O is suitable. That is, the transmittance can be increased by increasing the amount of O 2 gas and H 2 O introduced. Usually, after maintenance of the film forming apparatus, moisture is adsorbed on the wall surface in the apparatus, so that the amount of H 2 O introduced into the film can be changed by changing the baking time after the maintenance. That is, the transmittance can be increased by shortening the baking time.

このように透明電極形成条件をi型半導体層の成膜時セルフバイアス電圧に従って変化させることにより、直接光活性層の膜厚低下量を測定することなしに、長時間成膜による堆積膜形成装置状態の変化に起因する経時的な素子の特性低下を防止し、量産時における素子特性のばらつきを最小限に抑えることができるものである。   In this way, by changing the transparent electrode formation conditions according to the self-bias voltage at the time of film formation of the i-type semiconductor layer, the deposited film forming apparatus for long-time film formation without directly measuring the film thickness reduction amount of the photoactive layer It is possible to prevent deterioration of device characteristics over time due to a change in state and to minimize variations in device characteristics during mass production.

図2は、上記の本発明の形成法により作製可能なpin型非単結晶太陽電池を模式的に表わしたものである。図2は光が図の上部から入射する構造の太陽電池であり、図に於いて201は基板、202は裏面電極、203はn型半導体層、204はi型半導体層、205はp型半導体層、206は透明電極、207は集電電極を表わす。   FIG. 2 schematically shows a pin-type non-single crystal solar cell that can be produced by the above-described forming method of the present invention. FIG. 2 shows a solar cell having a structure in which light enters from the upper part of the figure. In the figure, 201 is a substrate, 202 is a back electrode, 203 is an n-type semiconductor layer, 204 is an i-type semiconductor layer, and 205 is a p-type semiconductor. Reference numeral 206 denotes a transparent electrode, and 207 denotes a collecting electrode.

(実施例1)
図3に示した装置を用いて、図2の非単結晶太陽電池を連続的に作製する方法について、以下に説明する。
Example 1
A method for continuously producing the non-single crystal solar cell of FIG. 2 using the apparatus shown in FIG. 3 will be described below.

図3は、本発明において使用される非単結晶太陽電池を連続的に作製する堆積膜形成装置の一例を表す模式図であり、基板送り出し室301、n型半導体層作製用容器302、i型半導体層作製用容器303、p型半導体層作製用容器304及び基板巻き取り室305が、ガスゲートを介して接続された装置から構成されている。307、312、317、322、323は排気ポンプ、311、316、321はカソード電極であり、それぞれ電源310、315、320に接続されている。また、電極で生じるセルフバイアス電圧はセルフバイアス電圧読取器309、314、319で読み取ることができる。   FIG. 3 is a schematic view showing an example of a deposited film forming apparatus for continuously producing non-single-crystal solar cells used in the present invention, including a substrate delivery chamber 301, an n-type semiconductor layer production container 302, and an i-type. The semiconductor layer preparation container 303, the p-type semiconductor layer preparation container 304, and the substrate winding chamber 305 are constituted by devices connected via a gas gate. Reference numerals 307, 312, 317, 322, and 323 denote exhaust pumps, and 311, 316, and 321 denote cathode electrodes, which are connected to power sources 310, 315, and 320, respectively. Further, the self-bias voltage generated at the electrodes can be read by the self-bias voltage readers 309, 314, and 319.

各反応容器302、303、304の中にはそれぞれ308、313、318の内側反応容器があり、帯状基板306を挟んで成膜空間と反対側の空間に赤外線ランプヒーター324、325、326が設けられ、不図示の温度制御系で所望の温度に制御される。   Each reaction vessel 302, 303, 304 has an inner reaction vessel of 308, 313, 318, respectively, and infrared lamp heaters 324, 325, 326 are provided in a space opposite to the film formation space with the belt-like substrate 306 interposed therebetween. The temperature is controlled to a desired temperature by a temperature control system (not shown).

まず、この製造装置の基板送り出し機構を有する真空容器301に、脱脂洗浄を行い、裏面電極としてスパッタリング法により、銀薄膜を100nm、ZnO薄膜を1μm蒸着してあるSUS430BA製帯状基板306(幅300mm×厚さ0.2mm)が巻きつけられたボビンをセットし、該帯状基板306を、n型半導体層成膜容器302、i型半導体層成膜容器303、p型半導体層成膜容器304、帯状基板巻き取り機構を有する真空容器305まで通し、たるみのない程度に張力調整を行った。なお、この時基板とカソード電極間の距離は20mmとなるように設置されている。   First, a vacuum vessel 301 having a substrate delivery mechanism of this manufacturing apparatus is degreased and cleaned, and a SUS430BA belt-like substrate 306 (width 300 mm × width) in which a silver thin film is deposited by 100 nm and a ZnO thin film is deposited by 1 μm by sputtering as a back electrode. A bobbin wound with a thickness of 0.2 mm) is set, and the belt-like substrate 306 is formed into an n-type semiconductor layer deposition container 302, an i-type semiconductor layer deposition container 303, a p-type semiconductor layer deposition container 304, and a strip shape. The tension was adjusted to the extent that there was no sagging through a vacuum vessel 305 having a substrate winding mechanism. At this time, the distance between the substrate and the cathode electrode is set to 20 mm.

次に、各真空容器301、302、303、304、305を排気ポンプ307、312、317、322、323で1×10-4Pa以下まで真空引きした。成膜前の加熱処理として真空容器302、303、304へ不図示のガス導入管よりHeを各々500sccm導入し、真空容器301、302、303、304、305の内圧が130Paになるようスロットルバルブの開度を調節して、各真空容器を排気ポンプで排気した。なお、ここでsccmとは流量の単位で、1sccm=1cm3/min(標準状態)であり、以後流量の単位はsccmで表わす。その後、加熱用ランプヒーター324、325、326により、帯状基板ならびに真空容器内部材を400℃に加熱し、1時間この状態で放置した。 Next, each vacuum vessel 301, 302, 303, 304, 305 was evacuated to 1 × 10 −4 Pa or less by exhaust pumps 307, 312, 317, 322, 323. As a heat treatment before film formation, 500 sccm of He is introduced into each of the vacuum containers 302, 303, 304 from a gas introduction pipe (not shown), and the internal pressure of the vacuum containers 301, 302, 303, 304, 305 is adjusted to 130 Pa. Each vacuum vessel was evacuated with an exhaust pump with the opening degree adjusted. Here, sccm is a unit of flow rate, which is 1 sccm = 1 cm 3 / min (standard state), and hereinafter, the unit of flow rate is represented by sccm. Thereafter, the belt-shaped substrate and the vacuum vessel inner member were heated to 400 ° C. by the heating lamp heaters 324, 325, and 326, and left in this state for 1 hour.

次にn型半導体層成膜準備として、温度指示値が270℃になるよう、温度制御装置(不図示)を設定し、赤外線ランプヒーター324により帯状基板306を加熱した。不図示のガス導入口より、内側反応容器308内にSiH4ガスを100sccm、PH3/H2(1%)ガスを500sccm、H2ガスを700sccm導入した。放電室の圧力が130Paになるように不図示のコンダクタンス調整バルブの開度を調節して、真空ポンプ312で排気した。RF(13.56MHz)電源310の出力値が100Wになるように設定し、電極311を通じて内側反応容器308内に放電を生起させた。 Next, as a preparation for forming the n-type semiconductor layer, a temperature controller (not shown) was set so that the temperature indication value was 270 ° C., and the strip substrate 306 was heated by the infrared lamp heater 324. SiH 4 gas was introduced into the inner reaction vessel 308 at 100 sccm, PH 3 / H 2 (1%) gas at 500 sccm, and H 2 gas at 700 sccm from a gas introduction port (not shown). The opening of a conductance adjustment valve (not shown) was adjusted so that the pressure in the discharge chamber was 130 Pa, and the vacuum pump 312 was evacuated. The output value of the RF (13.56 MHz) power supply 310 was set to 100 W, and discharge was generated in the inner reaction vessel 308 through the electrode 311.

i型半導体層成膜準備として、温度指示値が300℃になるよう、温度制御装置(不図示)を設定し、赤外線ランプヒーター325により帯状基板306を加熱した。不図示のガス導入口より、内側反応容器313内にSiH4ガスを800sccm、GeH4ガスを900sccm、H2ガスを3000sccm導入した。放電室の圧力が130Paになるようにコンダクタンス調整バルブの開度を調節して、真空ポンプ317で排気した。RF電源315の出力値が1000Wになるように設定し電極316を通じて内側反応容器313内に放電を生起させた。なお、電極316に生じるセルフバイアス電圧はセルフバイアス電圧読取器314でモニターした。 In preparation for forming the i-type semiconductor layer, a temperature control device (not shown) was set so that the temperature indication value was 300 ° C., and the strip substrate 306 was heated by the infrared lamp heater 325. From a gas introduction port (not shown), 800 sccm of SiH 4 gas, 900 sccm of GeH 4 gas, and 3000 sccm of H 2 gas were introduced into the inner reaction vessel 313. The opening of the conductance adjustment valve was adjusted so that the pressure in the discharge chamber was 130 Pa, and the vacuum pump 317 was evacuated. The output value of the RF power source 315 was set to 1000 W, and discharge was generated in the inner reaction vessel 313 through the electrode 316. The self-bias voltage generated at the electrode 316 was monitored by a self-bias voltage reader 314.

p型半導体層成膜準備として、温度指示値が150℃になるよう、温度制御装置(不図示)を設定し、赤外線ランプヒーター326により帯状基板306を加熱した。不図示のガス導入口より、内側反応容器318内にSiH4ガスを10sccm、BF3/H2(1%)ガスを500sccm、H2ガスを5000sccm導入した。放電室の圧力が130Paになるようにコンダクタンス調整バルブの開度を調節して、真空ポンプ322で排気した。RF電源320の出力値が2000Wになるように設定し、電極321を通じて内側反応容器318内に放電を生起させた。 As preparation for forming the p-type semiconductor layer, a temperature control device (not shown) was set so that the temperature indication value was 150 ° C., and the strip substrate 306 was heated by the infrared lamp heater 326. From a gas inlet port (not shown), 10 sccm of SiH 4 gas, 500 sccm of BF 3 / H 2 (1%) gas, and 5000 sccm of H 2 gas were introduced into the inner reaction vessel 318. The opening of the conductance adjustment valve was adjusted so that the pressure in the discharge chamber was 130 Pa, and the vacuum pump 322 was used to evacuate. The output value of the RF power source 320 was set to 2000 W, and discharge was generated in the inner reaction vessel 318 through the electrode 321.

各層の成膜準備後引き続いて、帯状基板306を1000mm/minの速度で搬送させ、帯状基板にn型半導体層、i型半導体層、p型半導体層を作製開始した。ここで成膜開始後30分でのi型半導体層を形成する際に電極316に生じるセルフバイアス電圧値は−0.2Vであった。その後約10時間には電極316に生じるセルフバイアス電圧値が−1.6Vとなり最終的に約20時間後には−2.45Vで成膜が終了した。図4に電極316に生じるセルフバイアス電圧値の時間変化のグラフを示す。   Subsequently, after preparation of each layer, the strip substrate 306 was transported at a speed of 1000 mm / min, and an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer were produced on the strip substrate. Here, the self-bias voltage value generated in the electrode 316 when forming the i-type semiconductor layer 30 minutes after the start of film formation was -0.2V. About 10 hours thereafter, the self-bias voltage value generated at the electrode 316 became −1.6 V. Finally, about 20 hours later, the film formation was completed at −2.45 V. FIG. 4 shows a graph of the time change of the self-bias voltage value generated at the electrode 316.

前記帯状基板の1ロール分を搬送させた後、全てのプラズマ励起、全てのガス供給、全てのランプヒーターの通電、帯状基板の搬送を停止した。次に、チャンバーリーク用のN2ガスをチャンバーに導入し(導入用部材は不図示)大気圧に戻し、真空容器305内の前記帯状基板を取り出した。 After one roll of the belt-shaped substrate was transported, all plasma excitation, all gas supply, energization of all lamp heaters, and transport of the belt-shaped substrate were stopped. Next, N 2 gas for chamber leakage was introduced into the chamber (introducing member is not shown), the pressure was returned to atmospheric pressure, and the strip substrate in the vacuum vessel 305 was taken out.

そして前記帯状基板のp型半導体層上に図5に示すDCスパッタリング装置を用いITO(In23+SnO2)の透明導電膜を表1に示す条件で以下の手順で連続的に成膜し透明電極を形成した。 Then, a transparent conductive film made of ITO (In 2 O 3 + SnO 2 ) is continuously formed on the p-type semiconductor layer of the strip substrate by the following procedure under the conditions shown in Table 1 using the DC sputtering apparatus shown in FIG. A transparent electrode was formed.

Figure 2006237180
Figure 2006237180

装置をメンテナンス等の為に大気開放した後、帯状基板のロール502を基板送り出し室501にセットし、透明導電膜成膜室506、507、508、509、510、511それぞれに帯状基板504を貫通させ、基板巻き取り室516のロール514に固定する。続いて装置内の圧力が0.1Pa以下になるまで排気した。この後透明導電膜形成室506、507、508、509、510、511にガス供給管551、552、553、554、555、556から不活性ガスとしてアルゴンガスを表1に示す量供給した。またゲート515へもアルゴンガスを30sccm供給した。この状態で不図示の排気バルブの開度を調整して装置内の圧力を表1に示す圧力に保った。透明導電膜成膜室506、507、508、509、510、511のそれぞれに設けられた100Wの赤外線ランプ6本を備えたヒータユニット541、542、543、544、545、546とステンレス製の反射板により基板成膜面の裏面に接触させた熱電対を用いながら表1に示す温度になるよう制御しながら加熱した。続いてサーボモータを動作し巻き取りロール514を回転させて帯状基板504の搬送を開始した。   After the apparatus is opened to the atmosphere for maintenance or the like, a belt-like substrate roll 502 is set in the substrate delivery chamber 501 and the transparent conductive film deposition chambers 506, 507, 508, 509, 510 and 511 are penetrated through the belt-like substrate 504. And fixed to the roll 514 of the substrate winding chamber 516. Then, it exhausted until the pressure in an apparatus became 0.1 Pa or less. Thereafter, argon gas as an inert gas was supplied to the transparent conductive film forming chambers 506, 507, 508, 509, 510, and 511 from the gas supply pipes 551, 552, 553, 554, 555, and 556 as shown in Table 1. Also, 30 sccm of argon gas was supplied to the gate 515. In this state, the opening of an exhaust valve (not shown) was adjusted to maintain the pressure in the apparatus at the pressure shown in Table 1. Heater units 541, 542, 543, 544, 545, and 546 with six 100 W infrared lamps provided in each of the transparent conductive film forming chambers 506, 507, 508, 509, 510, and 511 and stainless steel reflections Heating was performed while controlling the temperature as shown in Table 1 using a thermocouple brought into contact with the back surface of the substrate deposition surface by a plate. Subsequently, the servo motor was operated to rotate the take-up roll 514, and the conveyance of the belt-like substrate 504 was started.

透明導電膜成膜室506、507、508、509、510、511に帯状基板504を搬送した。純度99.99重量%、25cm×25cmの大きさのITOターゲット521、522、523、524、525、526にDC電源531、532、533、534、535、536用いてDC電圧を印加して表1に示した電力になるように制御しながらアルゴンプラズマを生起しスパッタリングを行った。   The belt-like substrate 504 was transferred to the transparent conductive film deposition chambers 506, 507, 508, 509, 510, and 511. DC voltage is applied to ITO targets 521, 522, 523, 524, 525, and 526 having a purity of 99.99% by weight and a size of 25 cm × 25 cm using DC power sources 531, 532, 533, 534, 535, and 536. An argon plasma was generated while performing control so that the power shown in FIG.

ここで透明導電膜の膜厚を調整するために表1に示した搬送スピードを2500mm/min一定値にせず、変化させることにより透明電極形成時間を変えて成膜を行った。具体的には図4に示したi型半導体層の成膜時セルフバイアス電圧値に従い搬送スピードを2950mm/minから2500mm/minに変化させた。これは、帯状基板504はロール状に巻き取られているため、最初に透明導電膜が成膜される部分はi型半導体層成膜時にセルフバイアスが下がっている最後の部分にあたりi型半導体層が薄くなっている。そのため透明導電膜成膜の搬送速度を上げ透明導電膜の膜厚を薄くしている。また透明導電膜成膜の最後の部分はi型半導体層成膜時には先頭の部分にあたりi型半導体層は正常な膜厚なので透明導電膜の膜厚を厚くするために透明導電膜成膜の搬送スピードを上げている。   Here, in order to adjust the film thickness of the transparent conductive film, the transport speed shown in Table 1 was not set to a constant value of 2500 mm / min, but the film was formed by changing the transparent electrode formation time by changing it. Specifically, the conveyance speed was changed from 2950 mm / min to 2500 mm / min in accordance with the self-bias voltage value at the time of film formation of the i-type semiconductor layer shown in FIG. This is because, since the strip-shaped substrate 504 is wound up in a roll shape, the portion where the transparent conductive film is first formed is the last portion where the self-bias is lowered during the formation of the i-type semiconductor layer. Is thinner. Therefore, the transport speed of the transparent conductive film is increased to reduce the film thickness of the transparent conductive film. In addition, the last part of the transparent conductive film formation is the first part when the i-type semiconductor layer is formed, and the i-type semiconductor layer is a normal film thickness. I'm speeding up.

透明電極を形成した帯状基板504は巻き取り室516で巻き取った。なお透明導電膜の表面を傷つけないようにポリエステルフィルムの合紙513を巻き取り時基板と基板の間にはさみ込んだ。   The belt-like substrate 504 on which the transparent electrode was formed was wound up in a winding chamber 516. In order to prevent the surface of the transparent conductive film from being damaged, a polyester film interleaf 513 was sandwiched between the substrates during winding.

さらに集電電極としてAlを真空蒸着により1μm厚みで形成し非単結晶太陽電池を作製した。   Furthermore, a non-single crystal solar cell was manufactured by forming Al as a current collecting electrode by vacuum deposition to a thickness of 1 μm.

(比較例1)
透明電極形成時に搬送スピードを2500mm/minで一定にしながら成膜をおこなった以外は、実施例1と同様にして非単結晶太陽電池を作製した。
(Comparative Example 1)
A non-single-crystal solar cell was produced in the same manner as in Example 1 except that the film formation was performed while keeping the transport speed constant at 2500 mm / min when forming the transparent electrode.

評価として、実施例1、比較例1の試料にソーラーシミュレータを用いてAM−1.5の太陽光スペクトルの光を100mW/cm2の強度で照射し、電圧電流曲線を求めることにより太陽電池の初期変換効率を測定した。 As an evaluation, the samples of Example 1 and Comparative Example 1 were irradiated with light of the sunlight spectrum of AM-1.5 at an intensity of 100 mW / cm 2 using a solar simulator, and a voltage-current curve was obtained. Initial conversion efficiency was measured.

図6は実施例1ならびに比較例1で得られた太陽電池をある一定の成膜時間毎に抜き取り、その短絡電流(Isc)をプロットしたものであり、短絡電流(Isc)を縦軸、成膜時間を横軸として示している。ここで短絡電流Isc(normalized)は、実施例1の成膜開始30分後の短絡電流を1として規格化して表わした。   FIG. 6 is a graph in which the solar cells obtained in Example 1 and Comparative Example 1 are extracted every certain film formation time and the short-circuit current (Isc) is plotted. The short-circuit current (Isc) is plotted on the vertical axis. The membrane time is shown on the horizontal axis. Here, the short-circuit current Isc (normalized) is expressed by standardizing the short-circuit current 30 minutes after the start of film formation in Example 1 as 1.

比較例1で作製された太陽電池の短絡電流は成膜時間が経過するに伴い4.1%低下したのに対し、実施例1で作製された太陽電池の短絡電流は成膜開始から最後の20時間の間においてほとんど低下しておらず、低下率は0.74%内にすべて収まり、比較例1よりも素子特性の維持に著しい効果が見られた。   The short-circuit current of the solar cell produced in Comparative Example 1 decreased by 4.1% as the film formation time elapses, whereas the short-circuit current of the solar cell produced in Example 1 lasted from the start of film formation. Almost no reduction was observed during 20 hours, and the reduction rate was all within 0.74%, and a remarkable effect was observed in maintaining device characteristics as compared with Comparative Example 1.

(実施例2)
本例では、透明電極の形成条件を以下のように変更した以外は、全て実施例1と同様にして非単結晶太陽電池を作製した。
(Example 2)
In this example, a non-single crystal solar cell was produced in the same manner as in Example 1 except that the conditions for forming the transparent electrode were changed as follows.

本例では、透明電極の膜厚を調整するために投入電力を変化させて堆積速度を制御し搬送スピードは一定にして成膜を行った。i型半導体層成膜時の成膜開始時から終了時の間におけるセルフバイアス電圧値の変化に従い、DC印加電圧を調整することにより表1に示した投入電力を1.0345W/cm2から1.2W/cm2へと上げていった以外は表1の条件に従いITO(In23+SnO2)の透明導電膜の成膜を行った。1ロール分の成膜が終了した後、実施例1と同様に集電電極を形成し、太陽電池を作製した。 In this example, in order to adjust the film thickness of the transparent electrode, the deposition power was controlled by changing the input power, and the film was formed at a constant transfer speed. The applied power shown in Table 1 is adjusted from 1.0345 W / cm 2 to 1.2 W by adjusting the DC applied voltage in accordance with the change in the self-bias voltage value from the start to the end of film formation during the formation of the i-type semiconductor layer. A transparent conductive film of ITO (In 2 O 3 + SnO 2 ) was formed according to the conditions in Table 1 except that the film thickness was increased to / cm 2 . After film formation for one roll was completed, a collecting electrode was formed in the same manner as in Example 1 to produce a solar cell.

この太陽電池を実施例1と同様の方法で評価した結果、実施例2で作製された太陽電池の短絡電流は成膜開始から最後の20時間の間においてほとんど低下しておらず、低下率は1.02%内にすべて収まり、比較例1よりも素子特性の維持に著しい効果が見られた。   As a result of evaluating this solar cell in the same manner as in Example 1, the short-circuit current of the solar cell produced in Example 2 hardly decreased during the last 20 hours from the start of film formation, and the rate of decrease was All were within 1.02%, and a remarkable effect was observed in maintaining device characteristics as compared with Comparative Example 1.

(実施例3)
本例では、透明電極の形成条件を以下のように変更した以外は、全て実施例1と同様にして非単結晶太陽電池を作製した。
(Example 3)
In this example, a non-single crystal solar cell was produced in the same manner as in Example 1 except that the conditions for forming the transparent electrode were changed as follows.

本例では、透明電極の透過率を調整するために基板温度を変化させて結晶化度を制御し膜厚は一定にして成膜を行った。i型半導体層成膜時の成膜開始時から終了時の間におけるセルフバイアス電圧値の変化に従い、ヒータユニット541、542、543、544、545、546の使用する赤外線ランプの本数を調整することにより表1に示した基板温度を235℃から200℃へと下げていく以外は表1の条件に従いITO(In23+SnO2)の透明導電膜の成膜を行った。1ロール分の成膜が終了した後、実施例1と同様に集電電極を形成し、太陽電池を作製した。 In this example, in order to adjust the transmittance of the transparent electrode, the substrate temperature was changed to control the crystallinity, and the film thickness was kept constant. By adjusting the number of infrared lamps used by the heater units 541, 542, 543, 544, 545, and 546 according to the change in the self-bias voltage value from the start to the end of film formation during the formation of the i-type semiconductor layer, A transparent conductive film of ITO (In 2 O 3 + SnO 2 ) was formed according to the conditions in Table 1 except that the substrate temperature shown in 1 was lowered from 235 ° C. to 200 ° C. After film formation for one roll was completed, a collecting electrode was formed in the same manner as in Example 1 to produce a solar cell.

この太陽電池を実施例1と同様の方法で評価した結果、実施例3で作製された太陽電池の短絡電流は成膜開始から最後の20時間の間においてほとんど低下しておらず、低下率は0.89%内にすべて収まり、比較例1よりも素子特性の維持に著しい効果が見られた。   As a result of evaluating this solar cell by the same method as in Example 1, the short-circuit current of the solar cell produced in Example 3 hardly decreased during the last 20 hours from the start of film formation, and the rate of decrease was All were within 0.89%, and a remarkable effect was observed in maintaining device characteristics as compared with Comparative Example 1.

(実施例4)
本例では、透明電極の形成条件を以下のように変更した以外は、全て実施例1と同様にして非単結晶太陽電池を作製した。
Example 4
In this example, a non-single crystal solar cell was produced in the same manner as in Example 1 except that the conditions for forming the transparent electrode were changed as follows.

本例では、透明電極の透過率を調整するために酸素流量を変化させて膜中酸素濃度を制御し膜厚は一定にして成膜を行った。i型半導体層成膜時の成膜開始時から終了時の間におけるセルフバイアス電圧値の変化に従い、表1に示した酸素流量を0.32sccmから0.4sccmへと上げていく以外は表1の条件に従いITO(In23+SnO2)の透明導電膜の成膜を行った。1ロール分の成膜が終了した後、実施例1と同様に集電電極を形成し、太陽電池を作製した。 In this example, in order to adjust the transmittance of the transparent electrode, the oxygen flow rate was changed to control the oxygen concentration in the film, and the film thickness was kept constant. The conditions in Table 1 except that the oxygen flow rate shown in Table 1 is increased from 0.32 sccm to 0.4 sccm in accordance with the change in the self-bias voltage value from the start to the end of film formation when forming the i-type semiconductor layer. According to this, a transparent conductive film of ITO (In 2 O 3 + SnO 2 ) was formed. After film formation for one roll was completed, a collecting electrode was formed in the same manner as in Example 1 to produce a solar cell.

この太陽電池を実施例1と同様の方法で評価した結果、実施例4で作製された太陽電池の短絡電流は成膜開始から最後の20時間の間においてほとんど低下しておらず、低下率は0.61%内にすべて収まり、比較例1よりも素子特性の維持に著しい効果が見られた。   As a result of evaluating this solar cell in the same manner as in Example 1, the short-circuit current of the solar cell produced in Example 4 hardly decreased during the last 20 hours from the start of film formation, and the rate of decrease was All of them were within 0.61%, and a remarkable effect was observed in maintaining device characteristics as compared with Comparative Example 1.

(実施例5)
本例では、図7に示す基板側から光入射されるpin型非単結晶太陽電池の作製について述べる。図7は光が図の下部から入射する構造の太陽電池であり、図に於いて701は透光性基板、702は裏面電極、703はn型半導体層、704はi型半導体層、705はp型半導体層、706は透明電極を表わす。
(Example 5)
In this example, the production of a pin-type non-single-crystal solar cell in which light is incident from the substrate side shown in FIG. 7 will be described. FIG. 7 shows a solar cell having a structure in which light enters from the lower part of the figure. In the figure, 701 is a light-transmitting substrate, 702 is a back electrode, 703 is an n-type semiconductor layer, 704 is an i-type semiconductor layer, and 705 is A p-type semiconductor layer 706 represents a transparent electrode.

透光性基板701として大きさ150×150mm、厚み2mmの洗浄済みガラス基板を用い図8に示すバッジ式のDCスパッタリング装置で透明電極としてITO(In23+SnO2)の透明導電膜の成膜を行った。図8に於いて701は透光性基板、801は基板ホルダー、802はガス導入手段、803は加熱用ヒーター、804はITOターゲット、805はDCスパッタ電源を表わす。 A transparent glass substrate having a size of 150 × 150 mm and a thickness of 2 mm is used as the translucent substrate 701, and a transparent conductive film made of ITO (In 2 O 3 + SnO 2 ) is formed as a transparent electrode in the badge type DC sputtering apparatus shown in FIG. Membrane was performed. In FIG. 8, 701 is a translucent substrate, 801 is a substrate holder, 802 is a gas introduction means, 803 is a heater, 804 is an ITO target, and 805 is a DC sputtering power source.

まず基板ホルダー801に透光性基板701をセットし不図示のポンプで装置内を圧力0.1Pa以下まで排気した。次に不図示のマスフローコントローラを用いてArガス3.0sccm、O2ガス0.01sccmをガス導入手段802を介して装置内に導入して不図示の圧力コントローラで圧力を0.53Paに保った。その後加熱ヒーター803により透光性基板701を200℃に加熱した。温度が安定したところでDCスパッタ電源805からITOターゲット804に電圧を印加してプラズマを生起させ透光性基板701上にITO(In23+SnO2)の透明導電膜を120秒間成膜した。その際投入電力密度が1.2W/cm2になる様に印加電圧を調整した。 First, the translucent substrate 701 was set in the substrate holder 801, and the inside of the apparatus was evacuated to a pressure of 0.1 Pa or less by a pump (not shown). Next, Ar gas (3.0 sccm) and O 2 gas (0.01 sccm) were introduced into the apparatus through the gas introduction means 802 using a mass flow controller (not shown), and the pressure was maintained at 0.53 Pa using a pressure controller (not shown). . Thereafter, the translucent substrate 701 was heated to 200 ° C. by the heater 803. When the temperature was stabilized, a voltage was applied from the DC sputtering power source 805 to the ITO target 804 to generate plasma, and a transparent conductive film of ITO (In 2 O 3 + SnO 2 ) was formed on the translucent substrate 701 for 120 seconds. At that time, the applied voltage was adjusted so that the input power density was 1.2 W / cm 2 .

形成された透明電極706上に図9の半導体堆積膜形成装置を用いてpin半導体接合を形成した。   A pin semiconductor junction was formed on the formed transparent electrode 706 using the semiconductor deposited film forming apparatus shown in FIG.

図9は本発明において使用される非単結晶pin半導体接合を作製する堆積膜形成装置の一例を表す模式図であり、図9において、堆積膜形成装置はロードチャンバー901、p層RFチャンバー902、非晶質シリコンi層RFチャンバー903、n層RFチャンバー904、アンロードチャンバー905から構成されている。各チャンバー間は、ゲートバルブ906、907、908、909で各原料ガスが混合しないように分離されている。   FIG. 9 is a schematic view showing an example of a deposited film forming apparatus for producing a non-single crystal pin semiconductor junction used in the present invention. In FIG. 9, the deposited film forming apparatus includes a load chamber 901, a p-layer RF chamber 902, An amorphous silicon i-layer RF chamber 903, an n-layer RF chamber 904, and an unload chamber 905 are configured. The chambers are separated by gate valves 906, 907, 908, and 909 so that the source gases are not mixed.

RFチャンバー902は、p型層用加熱ヒーター910とp型層堆積室911を、RFチャンバー903はi型層用加熱ヒーター912とi型層堆積室913を、RFチャンバー904はn型層用加熱ヒーター914とn型層堆積室915を有している。透明導電膜の成膜を行った透光性基板701は基板ホルダー917に取り付けられ、搬送レール916上を外部から不図示の駆動ローラーによって移動する。   The RF chamber 902 is a p-type layer heater 910 and a p-type layer deposition chamber 911, the RF chamber 903 is an i-type layer heater 912 and an i-type layer deposition chamber 913, and the RF chamber 904 is an n-type layer heating. A heater 914 and an n-type layer deposition chamber 915 are provided. The translucent substrate 701 on which the transparent conductive film is formed is attached to a substrate holder 917, and moves on the transport rail 916 from the outside by a driving roller (not shown).

この堆積膜形成装置を使用して、表2に示す成膜条件で各半導体層を以下の手順で成膜した。   Using this deposited film forming apparatus, each semiconductor layer was formed by the following procedure under the film forming conditions shown in Table 2.

Figure 2006237180
Figure 2006237180

透光性基板701を基板ホルダー917にセットしロードチャンバー901のレール916上にセットした。そして、ロードチャンバー901内を不図示の真空ポンプにより数百mPa以下の真空度に排気した。   The translucent substrate 701 was set on the substrate holder 917 and set on the rail 916 of the load chamber 901. Then, the inside of the load chamber 901 was evacuated to a degree of vacuum of several hundred mPa or less by a vacuum pump (not shown).

次に、ゲートバルブ906を開け、基板ホルダー917をチャンバー902のp型層堆積室911に移動する。各ゲートバルブ906、907、908、909を閉じた状態で、表2のp層に示す原料ガスを不図示のガス導入手段にてp型層堆積室911に導入し不図示の圧力コントローラで表2のp層に示す圧力になる様に調整した。p型層用加熱ヒーター910により表2のp層に示す基板温度になるように透光性基板701を加熱した。温度が安定したところで不図示のRF電源から表2のp層に示す電力密度のRFを印加してプラズマを生起させて表2のp層に示す膜厚のp型層を堆積した。   Next, the gate valve 906 is opened, and the substrate holder 917 is moved to the p-type layer deposition chamber 911 in the chamber 902. With the gate valves 906, 907, 908, and 909 closed, the source gas shown in the p layer in Table 2 is introduced into the p-type layer deposition chamber 911 by a gas introduction means (not shown) and is expressed by a pressure controller (not shown). It adjusted so that it might become the pressure shown in p layer of 2. The translucent substrate 701 was heated by the p-type layer heater 910 so that the substrate temperature shown in the p layer in Table 2 was reached. When the temperature was stabilized, RF having a power density shown in the p layer in Table 2 was applied from an RF power source (not shown) to generate plasma, and a p-type layer having a thickness shown in the p layer in Table 2 was deposited.

堆積チャンバー902を十分に排気した後、ゲートバルブ907を開けて基板ホルダー917を堆積チャンバー903のi型層堆積室913に移動し、ゲートバルブ907を閉じた。   After exhausting the deposition chamber 902 sufficiently, the gate valve 907 was opened, the substrate holder 917 was moved to the i-type layer deposition chamber 913 of the deposition chamber 903, and the gate valve 907 was closed.

各ゲートバルブ906、907、908、909を閉じた状態で、表2のi層に示す原料ガスを不図示のガス導入手段にてi型層堆積室913に導入し不図示の圧力コントローラで表2のi層に示す圧力になる様に調整した。i型層用加熱ヒーター912により表2のi層に示す基板温度になるように透光性基板701を加熱した。温度が安定したところで不図示のRF電源から表2のi層に示す電力密度のRFを印加してプラズマを生起させて表2のi層に示す膜厚のi型層を堆積した。このときセルフバイアス電圧値は成膜開始時には−0.230Vで終了時には−0.237Vであった。   With the gate valves 906, 907, 908, 909 closed, the source gas shown in the i layer in Table 2 is introduced into the i-type layer deposition chamber 913 by a gas introduction means (not shown), and is displayed by a pressure controller (not shown). It adjusted so that it might become the pressure shown to i layer of 2. The translucent substrate 701 was heated by the i-type layer heater 912 so that the substrate temperature shown in the i layer in Table 2 was reached. When the temperature was stabilized, RF having a power density shown in the i layer in Table 2 was applied from an RF power source (not shown) to generate plasma, and an i-type layer having a thickness shown in the i layer in Table 2 was deposited. At this time, the self-bias voltage value was -0.230 V at the start of film formation and -0.237 V at the end.

堆積チャンバー903を十分に排気した後、ゲートバルブ908を開けて基板ホルダー917を堆積チャンバー904のn型層堆積室915に移動し、ゲートバルブ908を閉じた。   After exhausting the deposition chamber 903 sufficiently, the gate valve 908 was opened, the substrate holder 917 was moved to the n-type layer deposition chamber 915 of the deposition chamber 904, and the gate valve 908 was closed.

各ゲートバルブ906、907、908、909を閉じた状態で、表2のn層に示す原料ガスを不図示のガス導入手段にてn型層堆積室915に導入し不図示の圧力コントローラで表2のn層に示す圧力になる様に調整した。n型層用加熱ヒーター914により表2のn層に示す基板温度になるように透光性基板701を加熱した。温度が安定したところで不図示のRF電源から表2のn層に示す電力密度のRFを印加してプラズマを生起させて表2のn層に示す膜厚のn型層を堆積した。   With each gate valve 906, 907, 908, 909 closed, the source gas shown in the n layer of Table 2 is introduced into the n-type layer deposition chamber 915 by a gas introduction means (not shown) and is expressed by a pressure controller (not shown). It adjusted so that it might become the pressure shown to 2 n layer. The translucent substrate 701 was heated by the n-type layer heater 914 so that the substrate temperature shown in the n layer of Table 2 was reached. When the temperature was stabilized, RF having a power density shown in the n layer in Table 2 was applied from an RF power source (not shown) to generate plasma, and an n-type layer having a thickness shown in the n layer in Table 2 was deposited.

上記と同様にして堆積チャンバー904を十分に排気した後、ゲートバルブ909を開けて基板ホルダー917をアンロードチャンバー905へ移動した。   After the deposition chamber 904 was sufficiently evacuated in the same manner as described above, the gate valve 909 was opened and the substrate holder 917 was moved to the unload chamber 905.

ゲートバルブを全て閉じ、アンロードチャンバー905内へ窒素ガスを封入して、基板を冷却する。その後、アンロードチャンバー905の取り出し扉を開けて基板ホルダー917を取り出した。   All the gate valves are closed, nitrogen gas is sealed in the unload chamber 905, and the substrate is cooled. Thereafter, the takeout door of the unload chamber 905 was opened, and the substrate holder 917 was taken out.

以上のようにして透明電極とpin半導体接合が形成された透光性基板701に裏面電極702としてZnOを2μm、Alを1μmを順に不図示のDCスパッタ装置で成膜して太陽電池を作製した。この太陽電池をロットNo.1とした。   A solar cell was fabricated by forming a film of ZnO 2 μm and Al 1 μm in this order on a transparent substrate 701 on which a transparent electrode and a pin semiconductor junction were formed as described above, using a DC sputtering apparatus (not shown) in this order. . This solar cell is designated as Lot No. It was set to 1.

続けてロットNo.2以降の太陽電池の作製を連続して行ったがその時、事前の実験よりi型半導体成膜時にセルフバイアス電圧値が3.56V低下した時には透明電極の膜厚を15.2%薄くすると太陽電池の短絡電流(Isc)が初期の短絡電流と同じになることがわかっているので、透明電極形成時に以下の式に従い成膜時間T(n)の調整を行った。
T(n+1)=((−0.152)×(|Vs0−Vs(n)|/3.56)+1)×120 [秒]
ここでT(n+1)はロットNo.n+1の透明電極成膜時間、Vs0はロットNo.1のi型半導体層成膜開始時のセルフバイアス電圧値、Vs(n)はロットNo.nのi型半導体層成膜終了時のセルフバイアス電圧値を表す。また、成膜時間の調整は1秒単位で行い1秒未満は切り上げた。
Next, lot no. 2 and subsequent solar cells were manufactured continuously. At that time, when the self-bias voltage value decreased by 3.56 V during the film formation of the i-type semiconductor from the previous experiment, the thickness of the transparent electrode was reduced by 15.2%. Since the short-circuit current (Isc) of the battery is known to be the same as the initial short-circuit current, the film formation time T (n) was adjusted according to the following formula when forming the transparent electrode.
T (n + 1) = ((− 0.152) × (| Vs 0 −Vs (n) | /3.56) +1) × 120 [seconds]
Here, T (n + 1) is the lot number. n + 1 transparent electrode deposition time, Vs 0 is lot no. 1 is a self-bias voltage value at the start of film formation of the i-type semiconductor layer, and Vs (n) is a lot number. The self-bias voltage value at the end of n-type i-type semiconductor layer deposition is represented. The film formation time was adjusted in units of 1 second and rounded up to the nearest 1 second.

上記の式に従いロットNo.2の透明電極成膜時間T(2)を計算行い
T(2)=((−0.152)×(|−0.230−(−0.237)|/3.56)+1)×120=119.96
となるため成膜時間は120秒とした。
Lot no. The transparent electrode deposition time T (2) of 2 is calculated, and T (2) = ((− 0.152) × (| −0.230 − (− 0.237) | /3.56) +1) × 120 = 119.96
Therefore, the film formation time was 120 seconds.

この様にしてロットNo.500まで作製したところロットNo.499のi型半導体層成膜終了時のセルフバイアス電圧値は−3.54Vとなったので
T(500)=((−0.152)×(|−0.230−(−3.54)|/3.56)+1)×120=103.05
からロットNo.500の透明電極成膜時間は104秒になった。
In this way, lot no. Lot no. Since the self-bias voltage value at the end of 499 i-type semiconductor layer deposition was −3.54 V, T (500) = ((− 0.152) × (| −0.230 − (− 3.54) | /3.56) +1) × 120 = 103.05
To lot no. The film formation time for 500 transparent electrodes was 104 seconds.

(比較例2)
すべてのロットNo.の透明電極成膜時間を120秒に固定した以外は実施例5と全く同様にロットNo.500まで太陽電池の作製をおこなった。
(Comparative Example 2)
All lot numbers The transparent electrode formation time of the transparent electrode was fixed at 120 seconds and lot no. Solar cells were made up to 500.

評価として、実施例5、比較例2の試料にソーラーシミュレータを用いてAM−1.5の太陽光スペクトルの光を100mW/cm2の強度で照射し、電圧電流曲線を求めることにより太陽電池の初期変換効率を測定した。 As an evaluation, the sample of Example 5 and Comparative Example 2 was irradiated with light of the sunlight spectrum of AM-1.5 with an intensity of 100 mW / cm 2 using a solar simulator, and a voltage-current curve was obtained. Initial conversion efficiency was measured.

比較例2で作製された太陽電池の短絡電流はロットNo.1の短絡電流に対しロットNo.500の短絡電流が4.7%低下したのに対し、実施例5で作製された太陽電池の短絡電流はすべてのロットでほとんど低下しておらず、低下率は0.68%内にすべて収まり、比較例2よりも素子特性の維持に著しい効果が見られた。   The short circuit current of the solar cell produced in Comparative Example 2 is the lot no. 1 for the short-circuit current of 1. While the short circuit current of 500 decreased by 4.7%, the short circuit current of the solar cell manufactured in Example 5 hardly decreased in all lots, and the decrease rate was all within 0.68%. As compared with Comparative Example 2, a remarkable effect was observed in maintaining the device characteristics.

本発明の光起電力素子の半導体層を形成するための堆積膜形成装置の一例を模式的に示す概略図である。It is the schematic which shows typically an example of the deposited film formation apparatus for forming the semiconductor layer of the photovoltaic element of this invention. 本発明の形成方法により作製される基板の反対側から光入射されるpin型非単結晶太陽電池の構成を模式的に示す説明図である。It is explanatory drawing which shows typically the structure of the pin type non-single-crystal solar cell which injects light from the other side of the board | substrate produced by the formation method of this invention. 本発明の光起電力素子形成方法において使用される半導体膜形成装置の一例を示す概略図である。It is the schematic which shows an example of the semiconductor film formation apparatus used in the photovoltaic element formation method of this invention. 本発明の実施例1おいてi型半導体層成膜時のセルフバイアス電圧値の推移をある一定の成膜時間毎にプロットした図である。It is the figure which plotted the transition of the self-bias voltage value at the time of film-forming of i-type semiconductor layer for every fixed film-forming time in Example 1 of this invention. 本発明の光起電力素子形成方法において使用される透明導電膜形成装置の一例を示す概略図である。It is the schematic which shows an example of the transparent conductive film formation apparatus used in the photovoltaic element formation method of this invention. 本発明の実施例1、比較例1において作製された太陽電池セルをある一定の成膜時間毎に抜き取り、その短絡電流Iscを規格化した値をプロットした図である。It is the figure which extracted the photovoltaic cell produced in Example 1 of this invention, and the comparative example 1 for every fixed film-forming time, and plotted the value which normalized the short circuit current Isc. 本発明の形成方法により作製される基板側から光入射されるpin型非単結晶太陽電池の構成を模式的に示す説明図である。It is explanatory drawing which shows typically the structure of the pin type non-single-crystal solar cell which injects light from the substrate side produced by the formation method of this invention. 本発明の形成方法において使用される透明導電膜形成装置の一例を示す概略図である。It is the schematic which shows an example of the transparent conductive film formation apparatus used in the formation method of this invention. 本発明の光起電力素子形成方法において使用されるバッチ式の非単結晶pin半導体接合を作製する堆積膜形成装置の一例を示す概略図である。It is the schematic which shows an example of the deposited film formation apparatus which produces the batch type non-single-crystal pin semiconductor junction used in the photovoltaic element formation method of this invention.

符号の説明Explanation of symbols

100 内反応容器
101 基板
102 ヒーター
103 カソード電極
104 高周波電源
105 セルフバイアス電圧読取器
106 ガス導入管
107 ガス導入バルブ
108 マスフローコントローラー
109 排気管
110 外反応容器
201 基板
202 裏面電極
203 n型半導体層
204 i型半導体層
205 p型半導体層
206 透明電極
207 集電電極
208 光の入射方向
301 基板送り出し室
302 n型半導体層作製用容器
303 i型半導体層作製用容器
304 p型半導体層作製用容器
305 基板巻き取り室
306 帯状基板
307、312、317、322、323 排気ポンプ
308、313、318 内側反応容器
309、314、319 セルフバイアス電圧読取器
310、315、320 RF電源
311、316、321 カソード電極
324、325、326 ヒーター
501 基板送り出し室
502 帯状基板ロール
503 ローラー
504 帯状基板
506〜511 透明導電膜成膜室
512 ステアリングローラー
513 合紙
514 帯状基板ロール
515 ゲート
516 基板巻き取り室
517 マグネットローラー
521〜526 ITOターゲット
531〜536 DC電源
541〜546 加熱ヒーター
551〜556 ガス供給管
560 真空ポンプ
701 透光性基板
702 裏面電極
703 n型半導体層
704 i型半導体層
705 p型半導体層
706 透明電極
707 光の入射方向
801 基板ホルダー
802 ガス導入手段
803 加熱用ヒーター
804 ITOターゲット
805 DCスッパタ電源
901 ロードチャンバー
902 p層RFチャンバー
903 非晶質シリコンi層RFチャンバー
904 n層RFチャンバー
905 アンロードチャンバー
906〜909 ゲートバルブ
910 p型層用加熱ヒーター
911 RFプラズマCVDp層堆積室
912 非晶質i型層用加熱ヒーター
913 RFプラズマCVD非晶質i型層堆積室
914 n型層用加熱ヒーター
915 RFプラズマCVDn型層堆積室
916 ホルダー搬送レール
917 基板ホルダー
DESCRIPTION OF SYMBOLS 100 Reaction container 101 Substrate 102 Heater 103 Cathode electrode 104 High frequency power supply 105 Self-bias voltage reader 106 Gas introduction pipe 107 Gas introduction valve 108 Mass flow controller 109 Exhaust pipe 110 Outer reaction container 201 Substrate 202 Back electrode 203 N-type semiconductor layer 204 i Type semiconductor layer 205 p type semiconductor layer 206 transparent electrode 207 current collecting electrode 208 light incident direction 301 substrate delivery chamber 302 n type semiconductor layer preparation container 303 i type semiconductor layer preparation container 304 p type semiconductor layer preparation container 305 substrate Winding chamber 306 Strip substrate 307, 312, 317, 322, 323 Exhaust pump 308, 313, 318 Inner reaction vessel 309, 314, 319 Self-bias voltage reader 310, 315, 320 RF power source 311, 3 16, 321 Cathode electrodes 324, 325, 326 Heater 501 Substrate delivery chamber 502 Strip substrate roll 503 Roller 504 Strip substrate 506-511 Transparent conductive film deposition chamber 512 Steering roller 513 Interleaf 514 Strip substrate roll 515 Gate 516 Substrate take-up chamber 517 Magnet roller 521-526 ITO target 531-536 DC power source 541-546 Heater 551-556 Gas supply pipe 560 Vacuum pump 701 Translucent substrate 702 Back electrode 703 n-type semiconductor layer 704 i-type semiconductor layer 705 p-type semiconductor layer 706 Transparent electrode 707 Light incident direction 801 Substrate holder 802 Gas introduction means 803 Heater 804 ITO target 805 DC sputtering power supply 901 Load chamber 90 p-layer RF chamber 903 amorphous silicon i-layer RF chamber 904 n-layer RF chamber 905 unload chamber 906 to 909 gate valve 910 heater for p-type layer 911 RF plasma CVD p-layer deposition chamber 912 heating for amorphous i-type layer Heater 913 RF plasma CVD amorphous i-type layer deposition chamber 914 Heater for n-type layer 915 RF plasma CVD n-type layer deposition chamber 916 Holder transport rail 917 Substrate holder

Claims (6)

基板上に裏面電極、半導体層、透明電極の順で積層された構造からなる光起電力素子の形成方法において、前記半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、前記透明電極の形成条件を設定することを特徴とする光起電力素子の形成方法。   In a method for forming a photovoltaic device having a structure in which a back electrode, a semiconductor layer, and a transparent electrode are stacked in this order on a substrate, based on a self-bias voltage value generated when the semiconductor layer is formed, A method for forming a photovoltaic element, characterized in that formation conditions are set. 基板上に透明電極、半導体層、裏面電極の順で積層された構造からなる光起電力素子を少なくとも2個以上形成する方法において、第n(nは1以上の整数)番目の基板上に半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、第n+1番目の基板上に形成する透明電極の形成条件を設定することを特徴とする光起電力素子の形成方法。   In a method of forming at least two photovoltaic elements having a structure in which a transparent electrode, a semiconductor layer, and a back electrode are stacked in this order on a substrate, the semiconductor is formed on the nth (n is an integer of 1 or more) substrate. A method for forming a photovoltaic element, comprising setting conditions for forming a transparent electrode formed on an (n + 1) th substrate based on a self-bias voltage value generated when forming a layer. 前記透明電極の形成条件が、印加パワー、印加電圧、印加電流、形成時間、ガス流量、形成温度、堆積速度、またはベーキング時間の中から選ばれる少なくとも1つ以上であることを特徴とする請求項1又は2に記載の光起電力素子の形成方法。   The formation condition of the transparent electrode is at least one selected from application power, application voltage, application current, formation time, gas flow rate, formation temperature, deposition rate, and baking time. A method for forming a photovoltaic element according to 1 or 2. 基板上に裏面電極、半導体層、透明電極の順で積層された構造からなる光起電力素子の形成方法において、前記半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、前記透明電極の膜厚、または透過率を設定することを特徴とする光起電力素子の形成方法。   In a method for forming a photovoltaic device having a structure in which a back electrode, a semiconductor layer, and a transparent electrode are stacked in this order on a substrate, based on a self-bias voltage value generated when the semiconductor layer is formed, A method for forming a photovoltaic element, characterized by setting a film thickness or transmittance. 基板上に透明電極、半導体層、裏面電極の順で積層された構造からなる光起電力素子を少なくとも2個以上形成する方法において、第n(nは1以上の整数)番目の基板上に半導体層を形成する際に生じるセルフバイアス電圧値に基づいて、第n+1番目の基板上に形成する透明電極の膜厚、または透過率を設定することを特徴とする光起電力素子の形成方法。   In a method of forming at least two photovoltaic elements having a structure in which a transparent electrode, a semiconductor layer, and a back electrode are stacked in this order on a substrate, the semiconductor is formed on the nth (n is an integer of 1 or more) substrate. A method for forming a photovoltaic element, comprising setting a film thickness or a transmittance of a transparent electrode formed on an (n + 1) th substrate based on a self-bias voltage value generated when forming a layer. 前記半導体層を形成する際に生じるセルフバイアス電圧値と前記光起電力素子の短絡電流との関係に基づいて、前記透明電極の形成条件もしくは膜厚または透過率を設定することを特徴とする請求項1乃至5のいずれかに記載の光起電力素子の形成方法。   The formation condition, film thickness, or transmittance of the transparent electrode is set based on a relationship between a self-bias voltage value generated when forming the semiconductor layer and a short-circuit current of the photovoltaic element. Item 6. A method for forming a photovoltaic device according to any one of Items 1 to 5.
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