JP2006235445A - Data electrode drive circuit and image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower a frequency of a clock signal for reading image data. <P>SOLUTION: A white area and a rewriting area are set in a display image and the same bitmap data (white) is displayed to each pixel of pixel columns included in the white area. Thus, for example, when data such as a novel composed of character strings of a plurality of lines is displayed, a character string part is set as a writing area, a spacing part is set as the white area to display a background color (white) of the character string part, furthermore, the novel is displayed by using bitmap data of only the character string part, namely, the bitmap data omitting the spacing part. As a result, the number of pieces of data to be acquired is reduced for the bitmap data of the omitted spacing part and the frequency of the clock signal for reading the bit map data is lowered. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data electrode driving circuit for driving data electrodes arranged on a display panel, and an image display device using the data driving circuit.

  Conventionally, there is a DDS driving method as a high-speed driving method for a cholesteric liquid crystal panel that performs black and white display by switching the alignment state of a cholesteric liquid crystal that is a display body (see, for example, Patent Document 1). In such a data electrode driving circuit for DDS driving, generally, bit map data for one pixel row of a display target image is read in accordance with a read clock signal, and cholesteric based on the read data. A voltage pattern for displaying the display target image by DDS driving the liquid crystal is applied to each data electrode.

Further, in the DDS driving method, the selection period for enabling optimum display is relatively short, the selection period becomes long, and the contrast of the display target image is reduced unless the optimum selection period is reached.
US Pat. No. 5,748,277

However, since the conventional driving circuit reads all bitmap data for one pixel row during the selection period in the DDS driving method, for example, a high-definition display (for example, the total number of data electrodes 4000). Line), if the selection period is shortened (for example, 0.1 ms), the frequency of the clock signal for reading the bitmap data is increased (for example, 40 MHz), and the power consumption may increase. There was a possibility that reading could not be performed well.
An object of the present invention is to solve the above-mentioned unsolved problems of the prior art, and a data electrode driving circuit capable of reducing the frequency of a clock signal for reading image data, and the data electrode driving It is an object of the present invention to provide an image display device using a circuit.

  In order to solve the above problems, a data electrode driving circuit of the present invention is a data electrode driving circuit for driving a data electrode arranged on a display panel, and each pixel of a pixel column in the same direction as the direction of the data electrode. Acquisition means for acquiring image data of the second area among image data of a display target image including a first area in which all the pixels are of the same color and a second area in which each pixel of the pixel row is of a plurality of colors; The image processing apparatus includes a complementing unit that complements the image data acquired by the acquisition unit, and an application unit that applies a voltage to each data electrode based on the image data supplemented by the complementing unit. .

The storage unit stores data indicating the first area and data indicating the second area, and the acquisition unit refers to the data stored in the storage unit, thereby Image data may be acquired.
On the other hand, in order to solve the above problems, an image display device according to the present invention is an image display device having the data electrode driving circuit according to claim 1, wherein the data indicating the first region and the first Generating data indicating two areas, storing the generated data in the storage means of the data electrode driving circuit, generating image data of the second area, and generating the generated image data Image data storage means to be acquired by the acquisition means of the data electrode driving circuit is provided.

  According to such a configuration, the same image data (the same color) can be displayed on each pixel of the pixel column included in the first region. Therefore, for example, when displaying data such as a novel consisting of a plurality of lines of character strings, the character string portion is set to the second area, the line spacing portion is set to the first area, and the background color of the character string portion is set. Further, the novel can be displayed by using image data of only the character string portion, that is, image data in which the inter-line portion is omitted. As a result, the number of data to be acquired can be reduced by the amount of data in the omitted line portion, and the frequency of the clock signal for reading image data can be lowered.

Hereinafter, embodiments in which a data electrode driving circuit and an image display device according to the present invention are applied to an electronic book reader will be described with reference to the drawings.
<Configuration of electronic book reader>
FIG. 1 is a block diagram showing an internal configuration of an electronic book reader 1 to which the present invention is applied. As shown in FIG. 1, the electronic book reader 1 includes a CPU (Central Processing Unit) 2, a VRAM (Video Random Access Memory) 3, a display controller 4, and a display 5.

The CPU 2 reads various programs and data such as a basic control program and application program stored in a storage device (not shown), expands the various programs and data in a work area, and includes each unit 3 included in the electronic book reader 1. 8 control is executed.
Further, when there is an instruction to rewrite the display state of the display 5, the CPU 2 generates bitmap data of the display target image and stores the bitmap data in the VRAM 3.
When there is a write request for bitmap data from the CPU 2, the VRAM 3 stores the bitmap data. Further, when there is a request for reading bitmap data, the VRAM 3 outputs the requested bitmap data to the display controller 4.

 The display controller 4 executes a display state rewriting process to be described later when there is a display state rewriting command of the display 5. Then, when the display state rewriting process is executed, the display controller 4 first reads the bitmap data stored in the VRAM 3 into the display 5 (scanning electrode driving circuit 7 (described later), data electrode driving circuit 8). (Hereinafter also referred to as “rewrite area”) and an area that is not read (hereinafter also referred to as “white area”). Next, a command to erase the display on the display 5 is output to the display 5 (scanning electrode driving circuit 7 (described later), data electrode driving circuit 8). In addition, a numerical sequence (hereinafter also referred to as “rewrite column instruction data”) indicating a pixel column in the vertical direction in plan view included in the rewrite area is output to the display 5 (data electrode), and further, the bitmap of the rewrite area is displayed. Data is sequentially output to the display 5 (data electrode driving circuit 8) from a pixel row on the upper side in plan view (a pixel group in a row extending in the horizontal direction in plan view). In the rewrite column instruction data, the pixel column included in the rewrite region is associated with the numerical value “1”, the pixel column included in the white region is associated with the numerical value “0”, and the pixel on the left side in plan view It is arranged in order from the numerical value corresponding to the column.

  Further, the display controller 4 detects the number of pixel columns in the vertical direction in plan view included in the rewrite area, that is, the number of bitmap data to be read during the selection period in DDS driving. Then, the display controller 4 divides the selection period by the detected number of data, and uses the division result as one period to generate a clock signal for reading bitmap data (hereinafter also referred to as “read clock signal”). Generate.

The display 5 includes a cholesteric liquid crystal panel 6, a scan electrode drive circuit 7, and a data electrode drive circuit 8.
The cholesteric liquid crystal panel 6 is disposed in the center of the display 5 in plan view. The cholesteric liquid crystal panel 6 includes a cholesteric liquid crystal layer (not shown) in which cholesteric liquid crystal is sealed, a plurality of scanning electrodes (not shown) extending in a lateral direction in plan view on the upper surface side of the cholesteric liquid crystal layer, and a cholesteric liquid crystal panel. A plurality of data electrodes (not shown) extending in the vertical direction in plan view are provided on the lower surface side of the liquid crystal layer, and pixels are formed at intersections between the scan electrodes and the data electrodes.

The scan electrode drive circuit 7 is arranged on the left side in plan view of the cholesteric liquid crystal panel 6 and is connected to each left end in plan view of each scan electrode. The scan electrode driving circuit 7 repeatedly applies a voltage pattern for rewriting the cholesteric liquid crystal layer by DDS driving to the scan electrodes.
The data electrode driving circuit 8 is arranged on the upper side of the cholesteric liquid crystal panel 6 and, as shown in FIG. 2, an area discrimination register 9, a data shift register 10, a data latch 11, a data generation circuit 12, and a level shifter 13 It is comprised including.

  The area discrimination register 9 includes a plurality of DFFs (delay flip-flops) 14 provided corresponding to the respective data electrodes. When the rewrite sequence instruction data is output from the display controller 4, the area determination register 9 applies to the data electrode on the left side of the plurality of DFFs 14 when a significant edge of the read clock signal appears. The rewrite sequence instruction data is acquired one by one from the top in order from the associated one. That is, when there is a rewrite command, each DFF 14 stores a numerical value “1” “0” indicating whether the associated data electrode (pixel array) is a rewrite area or a white area. The

The data shift register 10 includes a plurality of shift register components 15 provided corresponding to the respective data electrodes. When the bitmap data is output from the display controller 4, the data shift register 10 refers to the DFF 14 of the area determination register 9 and each time a significant edge of the read clock signal appears, a plurality of shifts are generated. Pixels on the left side of the bitmap data in plan view are sequentially arranged in the order from the register configuration unit 15 corresponding to the data electrode on the left side in plan view and the pixel electrode (data electrode) included in the pixel rewrite area. Are obtained for each pixel. That is, when there is a rewrite command, bitmap data of the associated data electrode (pixel column) is stored in each shift register configuration unit 15 corresponding to the pixel column (data electrode) included in the rewrite area. .
Here, each shift register configuration unit 15 includes a DFF 16 and a selector circuit 17.

  The DFF 16 is a left side in plan view of bitmap data output from the display controller 4 (in the DFF 16 of the shift register configuration unit 15 in the second and subsequent stages, the bitmap data output from the shift register configuration unit 15 in the previous stage). Are obtained for one pixel, and the rest are output to the selector circuit 17 and a latch configuration unit 18 (described later) of the data latch 11.

  The selector circuit 17 refers to the DFF 14 corresponding to the same data electrode among the DFFs 14 included in the area determination register 9, and converts the bitmap data output from the DFF 16 or the bitmap data input to the DFF 16 to the next-stage shift register. Output to the component 15. Specifically, when the numerical value “1” (numerical value indicating the rewrite area) is stored in the DFF 14, the bitmap data output from the DFF 16 is output, and the numerical value “0” (numerical value indicating the white area) is set. If stored, the bitmap data input to the DFF 16 is output.

The data latch 11 includes a plurality of latch components 18 provided corresponding to the respective data electrodes. Then, each time a significant edge of a predetermined latch signal appears, the data latch 11 is associated with a pixel column (data electrode) included in the pixel rewriting area among the plurality of latch constituent portions 18. Bitmap data for one pixel stored in the DFF 16 of the shift register configuration unit 15 provided in association with the same data electrode is latched. Further, in the data latch 11 associated with the pixel column included in the white area, the white bitmap data latched by the data latch 11 is latched again. In other words, the data latch 11 latches bitmap data (a white region complemented) that is obtained by complementing the bitmap data stored in the data shift register 10.
Here, each latch component 18 includes a selector circuit 19 and a DEF 20.

  The selector circuit 19 refers to the DFF 14 corresponding to the same data electrode among the DFFs 14 included in the area determination register 9, and is a bit for one pixel stored in the DFF 16 of the shift register configuration unit 15 corresponding to the same data electrode. Map data or bitmap data for one pixel that has been output from the DFF 20 until then is output to the data generation circuit 12. Specifically, when the numerical value “1” (numerical value indicating the rewrite area) is stored in the DFF 14, the bitmap data output from the DFF 16 is output, and the numerical value “0” (numerical value indicating the white area) is set. If it is stored, the bitmap data stored in the DFF 20 is output.

The DFF 20 acquires the bitmap data output from the selector circuit 19. The DFF 16 stores bitmap data indicating white as an initial state.
The data generation circuit 12 outputs voltage pattern data for rewriting the cholesteric liquid crystal layer by DDS driving so that bitmap data for one pixel stored in the DFF 20 of the data latch 11 is displayed on the corresponding pixel. Generated for each data electrode.

The level shifter 13 acquires the voltage pattern data generated by the data generation circuit 12, and applies the voltage pattern indicated by the acquired data to each data electrode.
The display 5 generates a potential difference between the scan electrode and the data electrode by the voltage applied to the scan electrode and the data electrode, applies a voltage to each pixel of the cholesteric liquid crystal panel 6 and performs DDS driving. The orientation state (white state, black state) of the cholesteric liquid crystal in each pixel is changed, and the display target image is displayed on the cholesteric liquid crystal panel 6. In addition, when a command for displaying white on all pixels of the display 5 is output from the CPU 2, the display 5 applies a predetermined voltage to the scan electrode and the data electrode, and the scan electrode and the data electrode are completed by the applied voltage. A potential difference is generated, and the cholesteric liquid crystal in each pixel is changed to a white state, and white is displayed on all the pixels of the display 5.

<Operation of display controller>
Next, the rewriting process executed by the display controller 4 will be described. This rewriting process is executed when there is a content switching display request. As shown in FIG. 3, first, in step S1, the display target image is displayed based on the bitmap data stored in the VRAM 3. A region in which the pixel column in the vertical direction in the plan view is only white is set as a white display region, and a region including black in the pixel column is set as a rewrite region.
Next, the process proceeds to step S <b> 2, and a command to display white on all the pixels of the display 5 is output to the display 5 (scanning electrode driving circuit 7 and data electrode driving circuit 8).

Next, the process proceeds to step S3, and in order from the left in the plan view of the display target image, it is determined whether or not the pixel row in the vertical direction in the plan view is set as a white area in step S1, and the white area is set. The numerical value “0” is associated with the pixel row, and the numerical value “1” is associated with the rewrite area. And the numerical sequence which arrange | positions the matched numerical value in the said matched order is output to the display 5 (data electrode drive circuit 8).
Next, the process proceeds to step S4, where the bitmap data of the rewrite area set in step S1 is read from the VRAM 3, and the read bitmap data is displayed in order from the pixel row on the upper side in the plan view in the display 5 ( After the output to the data electrode drive circuit 8), the calculation process is terminated.

<Specific operation of electronic book reader>
Next, the operation of the electronic book reader 1 of the present embodiment will be described based on a specific situation.
First, as shown in FIG. 4A, it is assumed that a vertically written novel is selected as content, and a rewrite command for displaying the first page of the selected content on the display 5 is output to the CPU 2. Then, the CPU 2 generates bitmap data of the image of the first page, and the bitmap data is stored in the VRAM 3. Further, the display controller 4 executes the display state rewriting process, and as shown in FIG. 3, first, in step S1, based on the bitmap data stored in the VRAM 3 as shown in FIG. 4B. A region in which the pixel column in the vertical direction in plan view of the target image of the first page is only white is set as a white display region, and a region including black or gradation color in the pixel column is set as a rewrite region.

  In step S2, a command for displaying white on all pixels of the display 5 is output to the display 5 (scanning electrode driving circuit 7, data electrode driving circuit 8). Then, a predetermined voltage is applied to the scan electrode and the data electrode by the scan electrode drive circuit 7 and the data electrode drive circuit 8, a potential difference is generated by the applied voltage, and the cholesteric liquid crystal in each pixel is changed to a white state. The white color is displayed on all the pixels of the display 5. Note that step S2 is intended to input white data as an initial state to the DFF 16 of the shift register configuration unit 15 of the data electrode drive circuit 8, so that only data input is performed and voltage application to the display 5 is performed. It does not have to be done.

  Further, in step S3, it is determined in order from the left side in the plan view of the display target image whether or not the pixel column in the vertical direction in the plan view is set as a white region. When it is associated with the pixel column and set as a rewrite area, the numerical value “1” is associated. Then, a numerical sequence in which the associated numerical values are arranged in the associated order is output to the data electrode drive circuit 8 (region determination register 9) of the display 5. Then, every time a significant edge of the read clock signal appears by the area discrimination register 9, the rewrite column instruction data is sequentially written from the DFF 14 corresponding to the data electrode on the left side in the plan view. Get one by one from the top. As a result, each DFF 14 has a numerical value “1” or “1” indicating whether the associated data electrode (pixel array) is a rewrite area (area where bitmap data is rewritten) or a white area. “0” is stored.

  Further, in step S4, the bitmap data of the set rewrite area is read from the VRAM 3, and the bitmap data is the data electrode (data shift register 10) of the display 5 in order from the pixel row on the upper side in plan view. Is output. At that time, the number of pixel columns in the vertical direction in the plan view included in the rewrite area is detected, the selection period is divided by the number, and a read clock signal is generated with the division result as one period. The data shift register 10 refers to the DFF 14 of the area determination register 9 and each time a significant edge of the read clock signal appears, the data electrode on the left side of the plurality of shift register components 15 in plan view. One pixel on the left side of the bitmap data in plan view is sequentially arranged in order from the shift register configuration unit 15 associated with the pixel row (data electrode) included in the set pixel rewrite area. Get every minute. As a result, bitmap data of the associated data electrode (pixel column) is stored in each shift register configuration unit 15 corresponding to the pixel column (data electrode) included in the rewrite area. Since the DFF 16 is not selected by the selector circuit 17 in the shift register configuration unit 15 corresponding to the pixel column (data electrode) included in the white area, the initial state is maintained.

  In addition, each time a significant edge of a predetermined latch signal appears by the data latch 11, one of the plurality of latch components 18 that is associated with a pixel column (data electrode) included in the pixel rewrite area is Bitmap data for one pixel stored in the DFF 16 of the shift register configuration unit 15 provided in association with the same data electrode is latched. Further, in the data latch 11 associated with the pixel column included in the white area, the white bitmap data that has been latched by the data latch 11 is latched again. Further, the voltage pattern data for rewriting the cholesteric liquid crystal layer by DDS driving is displayed on each data electrode so that the bitmap data stored in the DFF 20 of the data latch 11 is displayed on the corresponding pixel by the data generation circuit 12. Generated for each. Then, the level shifter 13 acquires the voltage pattern data generated by the data generation circuit 12, and the voltage pattern indicated by the data is applied to each data electrode.

  At that time, a voltage pattern for rewriting the cholesteric liquid crystal layer by DDS driving is repeatedly applied to each scanning electrode by the scanning electrode driving circuit 7. In the display 5, a potential difference is generated between the scan electrode and the data electrode due to the voltage applied to the scan electrode and the data electrode, and a voltage is applied to each pixel of the cholesteric liquid crystal panel 6 to perform DDS driving. The orientation state (white state, black state) of the cholesteric liquid crystal in each pixel is changed, and the image of the first page is displayed on the cholesteric liquid crystal panel 6.

  Thus, according to the electronic book reader 1 of the present embodiment, the same bitmap data (white) can be displayed on each pixel of the pixel column included in the white region. Therefore, for example, when displaying data such as a novel consisting of a plurality of lines of character strings, the character string portion is set as a writing area, the line spacing portion is set as a white area, and the background color (white color of the character string portion is set. ) Is displayed, and further, the novel can be displayed by using bitmap data of only the character string portion, that is, bitmap data from which the inter-line portion is omitted. As a result, the number of data to be acquired can be reduced by the amount of the bitmap data of the omitted line portion, and the frequency of the clock signal for reading the bitmap data can be lowered.

For example, if the total number of data electrodes is 4000 lines, the frequency of the clock signal is about 4/5 if the white area is about 800 lines. In particular, when the display target image is a document image, the white ratio in the image is about 70%, which is more effective.
Further, when the frequency of the clock signal is lowered, the power consumption for display rewriting can be reduced, and the operations of the scan electrode driving circuit 7 and the data electrode driving circuit 8 can be stabilized.

  As described above, in the above embodiment, the data shift register 10 in FIG. 2 constitutes the acquisition means of the claims, and similarly, the data latch 11 in FIG. 2 constitutes the complement means, and the data generation circuit in FIG. 12 and the level shifter 13 constitute application means, the area discrimination register in FIG. 2 constitutes storage means, steps S1 and S3 in FIG. 3 constitute area data storage means, and step S4 in FIG. 3 stores image data. Configure the means.

The data electrode driving circuit and the image display device of the present invention are not limited to the contents of the above embodiment, and can be appropriately changed without departing from the spirit of the present invention.
Moreover, although the example which forms the data electrode drive circuit 8 with one circuit was shown, it is not restricted to this. For example, a plurality of small driving circuits may be connected in cascade, and when data reading is completed by one driving circuit, data reading may be automatically started by the next driving circuit. By doing so, the number of data buses for reading image data can be reduced. By the way, according to the method of individually providing data buses to a plurality of small drive circuits and individually reading data, the frequency of the clock signal for reading image data can be lowered, but the number of data buses Increases, making pattern mounting difficult.

It is a block diagram which shows the internal structure of an electronic book reader. FIG. 2 is a block diagram showing an internal configuration of a data electrode driving circuit of FIG. 1. It is a flowchart which shows a rewriting process. It is explanatory drawing for demonstrating operation | movement of an electronic book reader.

Explanation of symbols

1 is an electronic book reader, 2 is a CPU, 3 is a VRAM, 4 is a display controller, 5 is a display, 6 is a cholesteric liquid crystal panel, 7 is a scan electrode drive circuit, 8 is a data electrode drive circuit, 9 is a region discrimination register, 10 is a data shift register, 11 is a data latch, 12 is a data generation circuit, 13 is a level shifter, 14 is a DFF, 15 is a shift register component, 16 is a DFF, 17 is a selector circuit, 18 is a latch component, and 19 Selector circuit, 20 is DFF

Claims (3)

A data electrode driving circuit for driving a data electrode arranged on a display panel,
Of the image data of the display target image including a first region in which all the pixels in the pixel column in the same direction as the direction of the data electrode have the same color and a second region in which each pixel in the pixel column has a plurality of colors An acquisition means for acquiring the image data of the second region, a complement means for complementing the image data acquired by the acquisition means, and a voltage applied to each data electrode based on the image data supplemented by the complement means. And a data electrode driving circuit.   Storage means for storing data indicating the first area and data indicating the second area is provided, and the acquisition means refers to the data stored in the storage means, so that image data of the second area is stored. The data electrode driving circuit according to claim 1, wherein: An image display device comprising the data electrode drive circuit according to claim 1 or 2,
Generating data indicating the first area and data indicating the second area, and storing the generated data in a storage means of the data electrode driving circuit; and image data of the second area. An image display device comprising: image data storage means for generating and causing the acquisition means of the data electrode driving circuit to acquire the generated image data.

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