JP2006276626A - Image display apparatus and data electrode driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce clock frequency for reading data while preventing the deterioration of visibility in driving a display body. <P>SOLUTION: In transferring bit map data of a display screen to a display 5, an electronic book reader 1 successively transfers odd-numbered pixel data at first out of data of one line and drives data electrodes corresponding to the odd-numbered pixels and data electrodes corresponding to adjacent even-numbered pixels by the transferred odd-numbered pixel data. After executing the processing for all lines of a display screen, even-numbered pixel data are successively transferred to respective lines and data electrodes corresponding to the even-ordered pixels are driven by the pixel data of the newly transferred even-numbered pixel data. Thereby clock frequency for reading data can be reduced while preventing the deterioration of visibility in driving the display 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image display device that displays data by driving data electrodes disposed on a display panel, and a data electrode driving circuit thereof.

  Conventionally, there is a DDS driving method as a high-speed driving method for a cholesteric liquid crystal panel that performs black and white display by switching the alignment state of a cholesteric liquid crystal that is a display body (see, for example, Patent Document 1). In such a data electrode driving circuit for DDS driving, generally, bit map data for one pixel row of a display target image is read in accordance with a read clock signal, and cholesteric based on the read data. A voltage pattern for displaying the display target image by DDS driving the liquid crystal is applied to each data electrode.

In addition, in the DDS driving method, the selection period enabling optimum display is relatively short, and if the selection period becomes long and the optimum selection period is not reached, the contrast of the display target image is reduced. Will end up.
US Pat. No. 5,748,277

  However, since the conventional driving circuit reads all bitmap data for one pixel row during the selection period in the DDS driving method, for example, a high-definition display (for example, the total number of data electrodes 4000). Line), if the selection period is shortened (for example, 0.1 ms), the frequency of the clock signal for reading the bitmap data is increased (for example, 40 MHz), and the power consumption may increase. There was a risk that reading could not be performed well.

Here, a display technique based on interlace scanning is known as a technique capable of reducing the amount of input data per unit time and reducing the clock frequency for reading bitmap data.
When performing interlaced scanning, one frame is divided into an odd field and an even field, an odd line is scanned when an odd field is displayed, and an even line is scanned when an even field is displayed.

However, in the cholesteric liquid crystal panel, since the drawing speed is slow, when the display is performed by interlace scanning, the process of drawing the odd field and the even field in order is recognized by the user.
Further, since the cholesteric liquid crystal panel is a memory-type display body, when the screen is rewritten, the image of the previous frame is left and a new frame is written. Therefore, when the first field of one frame is written, the remaining image of the previous frame and the image of the new field are displayed in an overlapping manner.

As described above, in the case of cholesteric liquid crystal, visibility is significantly reduced when interlace scanning is performed.
Such a situation is particularly problematic in a display body with a slow drawing speed such as a cholesteric liquid crystal.
An object of the present invention is to reduce a clock frequency for reading data while preventing a decrease in visibility when driving a display body.

In order to solve the above problems, the present invention provides:
A pixel data transmission unit (for example, the display controller 4 in FIG. 1) that transmits pixel data for each line in the display body, and the pixel data transmitted by the pixel data transmission unit is received to drive the data electrode of each pixel. And an image display device including a data electrode driving circuit (for example, the data electrode driving circuit 8 in FIG. 1) for displaying the pixels of the line, wherein the data electrode driving circuit includes a predetermined number of adjacent data electrodes. Data input means (for example, the first-stage data latch circuit 13 in FIG. 2) for sequentially inputting pixel data corresponding to each of the one set of data electrodes to the one set of data electrodes, and the data In each of the electrodes, pixel data corresponding to a predetermined data electrode input first is displayed first, and among the pixel data corresponding to the one set of data electrodes, When pixel data corresponding to another data electrode is input, electrode control means (for example, the second-stage data latch circuit 12 in FIG. 2) that displays the input pixel data on the other data electrode is provided. The pixel data transmitting means sequentially transmits pixel data corresponding to a predetermined data electrode of each of the one set of data electrodes to each set of data electrodes.

  With such a configuration, when transferring the pixel data of the display screen to the display body, among the data for one line, first, predetermined pixel data in each set of data electrodes is sequentially transferred, and the transferred pixel data To drive the same set of adjacent data electrodes in addition to the data electrodes corresponding to the pixel. Next, the other pixel data of each set of data electrodes is sequentially transferred, and the data electrodes corresponding to the pixels are sequentially driven by the newly transferred other pixel data.

  Therefore, when the screen is displayed, the first pixel data is displayed on a predetermined number of adjacent data electrodes, so that the resolution is 1 / N in the line direction (scanning electrode direction) (N is one set). The number of electrodes in the data electrode) is displayed, then the other pixel data is sequentially transferred, and the data electrode corresponding to each pixel is driven, so that an image of the original resolution is finally obtained. Is displayed.

Therefore, when the display body is driven, the first transferred pixel in each set of data electrodes is not displayed superimposed on the image of the previous frame. Since pixel data only needs to be transferred at a speed of 1 / N, the clock frequency for reading data can be reduced.
The pixel data transmitting means outputs pixel data in the same input order in each set of the data electrodes for one line of the display screen in the arrangement order of each set of the data electrodes. A line unit display process for outputting one line of data is sequentially executed for each line of the display screen.

With such a configuration, for each line of the display screen, the first pixel in each set of data electrodes is displayed for the entire line, and the second and subsequent pixels in each set are sequentially displayed to display one line. Can do.
As for which data electrode the input pixel data is to be associated with, the selection signal is input from the outside, or the format of the input data is determined, and the display body side automatically uses a predetermined pattern according to the format. It is possible to select them automatically.

In addition, the pixel data transmission means performs group-unit display processing for sequentially outputting pixel data in the same input order in each set of the data electrodes for the lines of the entire display screen over the entire input order for each set of the data electrodes. It is characterized by doing.
With such a configuration, it is possible to display the entire display screen by displaying the first pixel in each set of data electrodes for all lines of the display screen and sequentially displaying the second and subsequent pixels in each set. .

Even in this case, as to which data electrode the input pixel data is to be associated with, a selection signal is input from the outside, a format of the input data is determined, and a predetermined pattern according to the format It is possible for the display body side to select automatically.
The pixel data transmission unit transmits the pixel data in the order corresponding to the arrangement of the data electrodes in the one set of data electrodes, and the data input unit receives the pixel data transmitted by the pixel data transmission unit. The electrode control means sequentially inputs the pixel data input to the set of data electrodes each time pixel data is input to the predetermined data electrode corresponding to the pixel data. It is characterized by repeating the process of displaying on the other data electrode to which no data electrode and corresponding pixel data are input.

With such a configuration, in each set of data electrodes, the pixel data that has not been input is displayed with the pixel data input immediately before in each set, and the pixels of the previous frame are not left. Since pixels of a new frame can be displayed, it is possible to prevent a decrease in visibility when the display screen is rewritten.
The electrode control means includes first storage means (for example, each latch circuit in the second-stage data latch circuit 12 in FIG. 2) provided corresponding to each of the one set of data electrodes, and the first control means. Selection means (for example, each selector in the data latch circuit 12 in the second stage in FIG. 2) for selecting data to be input to each of the storage means, and the data input means corresponds to the one set of data electrodes. Second storage means (for example, each latch circuit in the first stage data latch circuit 13 in FIG. 2) for sequentially storing the pixel data input to the first storage means, and the selection means includes pixel data Either the pixel data sequentially stored in the second storage means or the output data of the first storage means itself according to a predetermined selection signal inputted in synchronization with the first storage means. It is characterized in that input to.

With such a configuration, it is possible to realize the data electrode driving circuit for the above-described image display device while reducing the number of elements of the latch circuit from the configuration of the conventionally used data electrode driving circuit.
The present invention also provides:
A data electrode driving circuit for driving the data electrodes of each pixel in response to the input of pixel data for each line in the display body and displaying the pixels of the line, wherein a predetermined number of adjacent data electrodes are set as one set. , Data input means for sequentially inputting each pixel data corresponding to each of the one set of data electrodes to the one set of data electrodes, and a pixel corresponding to a predetermined data electrode input first in each of the data electrodes When the pixel data corresponding to the other data electrode is input from among the pixel data corresponding to the one set of data electrodes, the input pixel data is displayed on the other data electrode. And an electrode control means.

  With such a configuration, when the first pixel data is displayed on a predetermined number of adjacent data electrodes, first, the resolution is 1 / N in the line direction (scanning electrode direction), where N is a set of data electrodes. The number of electrodes) is displayed, and then other pixel data is sequentially transferred, and the data electrodes corresponding to the respective pixels are driven, so that an image of the original resolution is finally displayed.

Therefore, when the display body is driven, the first transferred pixel in each set of data electrodes is not displayed superimposed on the image of the previous frame. Since pixel data only needs to be transferred at a speed of 1 / N, the clock frequency for reading data can be reduced.
Further, the data input means sequentially inputs pixel data inputted in an order corresponding to the arrangement of the data electrodes in the one set of data electrodes to the one set of data electrodes, and the electrode control means In each set of data electrodes, each time pixel data is input, the input pixel data is displayed on a predetermined data electrode corresponding to the pixel data and another data electrode where the corresponding pixel data is not input. It is characterized by repeating the processing.

  The electrode control means includes first storage means provided corresponding to each of the one set of data electrodes, and selection means for selecting data to be input to each of the first storage means, The data input means includes second storage means for sequentially storing pixel data to be input to the first storage means corresponding to the one set of data electrodes, and the selection means is input in synchronization with the pixel data. In accordance with a predetermined selection signal, pixel data sequentially stored in the second storage means or output data of the first storage means itself is input to the first storage means. .

  Thus, according to the present invention, when driving the display body, it is possible to reduce the clock frequency for reading data while preventing the visibility from being lowered.

Embodiments of an image display device to which a data electrode driving circuit according to the present invention is applied will be described below with reference to the drawings.
First, the configuration will be described.
Here, a case where the image display device according to the present invention is configured as an electronic book reader will be described as an example.

FIG. 1 is a block diagram showing a functional configuration of an electronic book reader 1 according to the present invention.
In FIG. 1, an electronic book reader 1 includes a CPU (Central Processing Unit) 2, a VRAM (Video Random Access Memory) 3, a display controller 4 and a display 5.
The CPU 2 reads various programs and data such as a basic control program and application program stored in a storage device (not shown), develops these various programs and data in a work area, and executes control of the entire electronic book reader 1. .

When the user inputs a rewrite instruction for the display state of the display 5, the CPU 2 generates bitmap data of the display target image and stores the bitmap data in the VRAM 3.
When there is a write request for bitmap data from the CPU 2, the VRAM 3 stores the bitmap data. Further, when there is a request for reading bitmap data from the display controller 4, the VRAM 3 outputs the requested bitmap data to the display controller 4.

  When the user inputs a rewrite instruction for the display state of the display 5, the display controller 4 sequentially outputs one frame of data to the data electrode drive circuit 8 of the display 5 from the data of the line positioned on the display screen. To do. At this time, the display controller 4 first outputs odd-numbered pixel data in order, and then outputs even-numbered pixel data in order, among the data for one line in synchronization with the clock signal. By repeating such an output procedure for each line of data, the entire data of one frame is output.

The display 5 includes a cholesteric liquid crystal panel 6, a scan electrode drive circuit 7, and a data electrode drive circuit 8.
The cholesteric liquid crystal panel 6 is disposed in the center of the display 5 in plan view. The cholesteric liquid crystal panel 6 includes a cholesteric liquid crystal layer (not shown) in which cholesteric liquid crystal is sealed, a plurality of scanning electrodes (not shown) extending in a lateral direction in plan view on the upper surface side of the cholesteric liquid crystal layer, and a cholesteric liquid crystal panel. A plurality of data electrodes (not shown) extending in the vertical direction in plan view are provided on the lower surface side of the liquid crystal layer, and pixels are formed at intersections between the scan electrodes and the data electrodes.

The scan electrode drive circuit 7 is arranged on the left side in plan view of the cholesteric liquid crystal panel 6 and is connected to each left end in plan view of each scan electrode. Then, the scan electrode driving circuit 7 repeatedly applies a voltage pattern for rewriting the cholesteric liquid crystal layer by DDS driving to the scan electrodes.
The data electrode driving circuit 8 is arranged on the upper side of the cholesteric liquid crystal panel 6 and applies a voltage corresponding to the data input by the display controller 4 to the data electrodes of the cholesteric liquid crystal panel 6.

FIG. 2 is a block diagram showing an internal configuration of the data electrode driving circuit 8.
In FIG. 2, the data electrode driving circuit 8 includes a pixel electrode driving circuit 9, a level shifter 10, a voltage selection signal generation circuit 11, a second stage data latch circuit 12, a first stage data latch circuit 13, and an enable signal transfer circuit 14. It is comprised including.
The pixel electrode driving circuit 9 includes transistors (electrical switches) corresponding to actual voltage values applied to the data electrodes. Based on the voltage selection signal boosted by the level shifter 9, these transistor groups An actual voltage value to be applied to the data electrode is generated by turning on the one corresponding to the required voltage value.

The level shifter 10 boosts a low voltage signal indicating a predetermined voltage value input by the voltage selection signal generation circuit 11 to a voltage value capable of turning on a transistor corresponding to each voltage value in the pixel electrode driving circuit 9 in the next stage. To do.
In response to the state signal corresponding to the DDS driving period input by the display controller 4, the voltage selection signal generation circuit 11 receives the pixel value input by the second-stage data latch circuit 12 during the DDS driving selection period. A low voltage signal indicating a predetermined voltage value to be applied to each data electrode is generated according to the signal indicating, and output to the level shifter 10. In addition, the voltage selection signal generation circuit 11 generates a low voltage signal indicating a predetermined voltage value in a period other than the selection period of DDS driving according to the state signal, and the generated low voltage signal is sent to the level shifter 10. Output.

The second-stage data latch circuit 12 includes latch circuits corresponding to the data electrodes arranged on the cholesteric liquid crystal panel 6. These latch circuits have a circuit configuration in which two corresponding to adjacent data electrodes are set as one set (hereinafter, the latch circuit A on the left side of the plan view is referred to as “latch circuit A”, and This is referred to as “latch circuit B”).
The latch circuit A includes a selector C at the previous stage on the data input side, and the selector C receives the data signal input from the data latch circuit 13 at the first stage and the output of the latch circuit A. The Then, the selector C selects one of these two inputs according to the selection signal of the display controller 4 and outputs it to the latch circuit A.

The latch circuit B receives a data signal from the first-stage data latch circuit 13 that is common to the selector C.
The latch circuits A and B latch the input data in synchronization with the latch pulse signal input from the display controller 4.
Under such a circuit configuration, the selector C selects the input from the first-stage data latch circuit 13 in the initial state, and the latch circuits A and B receive from the first-stage data latch circuit 13. First, pixel data corresponding to the latch circuit A is input. At this time, pixel data (pixel data corresponding to the latch circuit A) input from the first-stage data latch circuit 13 is latched in the latch circuits A and B.

  Then, at the timing when the line is next selected, the display controller 4 causes the selector C to select the output of the latch circuit A, and the pixel data corresponding to the latch circuit B is received from the first-stage data latch circuit 13. Entered. Then, the latch circuit A latches the pixel data currently latched (pixel data corresponding to the latch circuit A) again, and the latch circuit B latches the pixel data corresponding to the newly input latch circuit B. It will be.

The first-stage data latch circuit 13 includes latch circuits D one by one corresponding to the latch circuits A and B in the second-stage data latch circuit 12.
Each latch circuit D receives a data signal from the display controller 4 in common, and each latch circuit D receives an enable signal corresponding to each from the enable signal transfer circuit 14. That is, each latch circuit D latches data input from the display controller 4 when the enable signal is input from the enable signal transfer circuit 14.

The enable signal transfer circuit 14 includes one DFF circuit E corresponding to each latch circuit D in the first stage data latch circuit 13.
Each DFF circuit E has a circuit configuration for transferring data in series, and a common shift clock signal is input thereto.
When the enable signal from the display controller 4 is input to the DFF circuit E on the left in plan view and the shift clock signal is input to each DFF circuit E, the enable signal is sequentially supplied to the DFF circuits E connected on the right side. Will be transferred.

  With such a configuration, in the data electrode driving circuit 8, when pixel data is input in synchronization with the clock signal in a state where the enable signal is input, it is first input with the first latch pulse signal. Pixel data (odd-numbered pixel data corresponding to the latch circuit A) is latched in common with the latch circuits A and B, and the next input pixel data (corresponding to the latch circuit B) with the second latch pulse signal. (Even-numbered pixel data) is newly latched by the latch circuit B.

Next, the operation will be described.
In the electronic book reader 1, when an instruction to rewrite the display state of the display 5 is input by pressing a page turning button (not shown) by the user, the CPU 2 generates bitmap data of the display target image, and the VRAM 3 To store. Then, the CPU 2 notifies the display controller 4 of input of a rewrite instruction.

Then, the display controller 4 reads the bitmap data from the VRAM 3 and selects one line of scanning electrodes located at the top of the display screen. The display controller 4 outputs an enable signal and then outputs one line of data to the data electrode drive circuit 8 of the display 5.
The display controller 4 repeats such a procedure for the second and subsequent lines of the display screen.

  At this time, the display controller 4 sequentially outputs the data of the odd-numbered pixels for each line of data in the first cycle to display one line, and is positioned odd-numbered for all the lines of the display screen. When the pixel data is written and displayed, the data of the even-numbered pixels is sequentially output in the second period, and the display of the entire display screen is completed.

FIG. 3 is a timing chart showing the states of the latch pulse signal, the clock signal, and the data signal when the display controller 4 outputs the bitmap data to the data electrode driving circuit 8 in two steps. In FIG. 3, the signal timing in the conventional case is also shown as a comparative example.
As shown in FIG. 3, the latch pulse signal is input twice until the display controller 4 completes the writing of the data for one line, and the clock is not transmitted until the first latch pulse signal (first period). In synchronization with the signal, the first, third, fifth,... And odd-numbered pixel data of the line are output. As a result, the pixel data (odd-numbered pixel data) corresponding to the latch circuit A is latched in each set of latch circuits A and B in the second-stage data latch circuit 12.

  Then, the voltage selection signal generation circuit 11 outputs a low voltage signal indicating a voltage value corresponding to the input pixel data to the level shifter 10, and the level shifter 10 boosts the low voltage signal to the pixel electrode driving circuit 9. A voltage that can turn on the transistor is used. Further, the pixel electrode drive circuit 9 applies a predetermined voltage to each data electrode by turning on the transistor corresponding to the predetermined voltage value.

As a result, an image of odd-numbered pixel data is displayed for one line.
Then, when the display controller 4 finishes the above-described process of outputting odd-numbered pixel data for the entire line of the display screen and outputting the first latch pulse signal, the second latch pulse signal of each line is (Period 2), the second, fourth, sixth,... And even-numbered pixel data of the line are output in synchronization with the clock signal. As a result, in each set of latch circuits A and B, the latch circuit A latches again the pixel data latched in the first cycle, and the latch circuit B latches the pixel data latched in the second cycle (even-numbered pixel data). ) Is latched.

That is, when a latch pulse signal is input twice for each line of the display screen, pixel data for one line (pixel data in a state where odd-numbered and even-numbered pixels are appropriately arranged) is in the second stage. The data latch circuit 12 is set in each latch circuit.
Then, the voltage selection signal generation circuit 11 outputs a low voltage signal indicating a voltage value corresponding to the input pixel data to the level shifter 10, and the level shifter 10 boosts the low voltage signal to the pixel electrode driving circuit 9. A voltage that can turn on the transistor is used. Further, the pixel electrode drive circuit 9 applies a predetermined voltage to each data electrode by turning on the transistor corresponding to the predetermined voltage value.

By executing such a procedure between the display controller 4 and the display 5, an image for one screen of the display screen is displayed.
As described above, when transferring the bitmap data of the display screen to the display 5, the electronic book reader 1 according to the present embodiment first transfers the odd-numbered pixel data among the data for one line in order. Then, the transferred odd-numbered pixel data drives the data electrode corresponding to the pixel and the data electrode corresponding to the adjacent even-numbered pixel. Then, after performing such processing for all the lines on the display screen, the even-numbered pixel data is sequentially transferred to each line in turn, and the newly-transferred even-numbered pixel data is transferred to the pixels. Drive the corresponding data electrode.

Therefore, when the screen is displayed, the odd-numbered pixel data is displayed on the two adjacent data electrodes, so that the resolution is halved in the line direction (scanning electrode direction) first. Then, even-numbered pixel data is transferred, and the data electrode corresponding to each even-numbered pixel is driven to display an image of the original resolution.
Therefore, when the display 5 is driven, since odd-numbered pixels in one line are not overlapped with the image of the previous frame, it is possible to prevent a reduction in visibility and to store one-line bitmap data. Since it suffices to transfer at half the speed, the clock frequency for reading data can be reduced.

In addition, for the entire display screen, an image in which the resolution of one line is halved is displayed in the first cycle, and then an image in full resolution is displayed in the second cycle.
Therefore, by displaying the entire image roughly in half the time, it becomes possible to improve visibility and give the user a sense of security.
In the present embodiment, the display controller 4 outputs the odd-numbered pixel data for one line on the display screen for all the lines on the display screen, and then the even-numbered pixel data for each line. The output is described as completely displaying the image of all lines on the display screen, but after outputting the odd-numbered pixel data for each line, the even-numbered pixel data for the line is output, It is also possible to use a writing procedure in which the display of the next line is displayed after the image of the line is completely displayed.

Further, in the present embodiment, it has been described that one line is divided and written into odd-numbered pixels and even-numbered pixels twice, but the number of times of dividing one line can be arbitrarily set.
FIG. 4 is a diagram showing an internal configuration of the data electrode driving circuit 8 when writing a pixel by dividing one line into three times.

The data electrode driving circuit 8 in FIG. 4 has a circuit configuration in which the latch circuit corresponding to three adjacent data electrodes is one set in the second-stage data latch circuit 12 (hereinafter, one set of latch circuits). Of these, the left one in plan view is called “latch circuit a”, the middle one is called “latch circuit b”, and the right one in plan view is called “latch circuit c”).
The latch circuits a and b are respectively provided with selectors d and e at the previous stage on the data input side. The selector d receives the data signal input from the data latch circuit 13 at the first stage and the latch circuit a. Output is input. Then, the selector d selects one of these two inputs in accordance with the selection signal from the display controller 4 and outputs it to the latch circuit a.

The selector e receives the data signal input from the first-stage data latch circuit 13 and the output of the latch circuit b. Then, the selector e selects one of these two inputs in accordance with the selection signal from the display controller 4 and outputs it to the latch circuit b.
The latch circuit c receives a data signal from the first-stage data latch circuit 13 that is common to the selectors d and e.

The latch circuits a to c latch the input data in synchronization with the latch pulse signal input from the display controller 4.
Under such a circuit configuration, the selectors d and e select the input from the first stage data latch circuit 13 in the initial state, and the latch circuits a to c include the first stage data latch circuit. 13. First, a pixel corresponding to the latch circuit a is input. At this time, pixel data (pixel data corresponding to the latch circuit a) input from the first-stage data latch circuit 13 is latched in the latch circuits a to c.

At the timing when the line is next selected, the display controller 4 causes the selector d to select the output of the latch circuit a and causes the selector e to select the input from the first-stage data latch circuit 13.
In this state, pixel data corresponding to the latch circuit b is input from the first-stage data latch circuit 13. Then, the latch circuit a latches the pixel data currently latched (pixel data corresponding to the latch circuit a) again, and the latch circuits b and c receive the pixel data corresponding to the newly input latch circuit b. Will be latched.

Further, at the timing when the line is next selected, the display controller 4 causes the selector d to select the output of the latch circuit a and causes the selector e to select the output of the latch circuit b.
In this state, pixel data corresponding to the latch circuit c is input from the first-stage data latch circuit 13. Then, the latch circuit a latches the pixel data currently latched (pixel data corresponding to the latch circuit a) again, and the latch circuit b performs the pixel data currently latched (pixel data corresponding to the latch circuit b). ) Is latched again, and the latch circuit c latches the pixel data corresponding to the newly input latch circuit c.

The first-stage data latch circuit 13 in FIG. 4 includes one latch circuit f corresponding to each of the latch circuits a to c in the second-stage data latch circuit 12.
A data signal from the display controller 4 is commonly input to each latch circuit f, and corresponding enable signals from the enable signal transfer circuit 14 are input to each latch circuit f. That is, each latch circuit f latches data input from the display controller 4 when an enable signal is input from the enable signal transfer circuit 14.

Since the other parts in FIG. 4 are the same as those in FIG. 2, the description thereof is omitted here.
With such a configuration, in the data electrode driving circuit 8, as shown in the timing chart of FIG. 5, when pixel data is input in synchronization with the clock signal in the state where the enable signal is input, the first time With the latch pulse signal, the pixel data (first, fourth, seventh... Pixel data corresponding to the latch circuit A) input first is latched in common with the latch circuits a to c. The next input pixel data (second, fifth, eighth,... Pixel data corresponding to the latch circuit b) is newly latched in the latch circuits b and c by the second latch pulse signal. Will be. Further, the pixel data (the third, sixth, ninth,... Pixel data corresponding to the latch circuit c) inputted next by the third latch pulse signal is newly inputted to the latch circuit c. It will be latched.

Thus, for example, when the display controller 4 outputs data to the data electrode drive circuit 8 by dividing one line into three times, the clock frequency of data transfer can be reduced to 1/3.
Note that, here, among the pixels corresponding to one set of latch circuits, data has been described as being transferred in the order of left, center, and right pixels from the left side of the display screen in plan view. It is also possible to transfer pixel data.

  In the present embodiment, the selection signal to be input to the selector in the second-stage data latch circuit 12 is input from the display controller 4. However, when the input pattern of pixel data in the line is constant. It is also possible to generate a predetermined selection signal in the data electrode driving circuit 8 and obtain the same result as in the present embodiment.

It is a block diagram which shows the function structure of the electronic book reader 1 which concerns on this invention. 3 is a block diagram showing an internal configuration of a data electrode drive circuit 8. FIG. 4 is a timing chart showing states of a latch pulse signal, a clock signal, and a data signal when the display controller 4 outputs the bitmap data to the data electrode driving circuit 8 in two steps. It is a figure which shows the internal structure of the data electrode drive circuit 8 in the case of writing a pixel by dividing 1 line into 3 times. 4 is a timing chart showing states of a latch pulse signal, a clock signal, and a data signal when the display controller 4 outputs bit map data to the data electrode driving circuit 8 in three steps.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic book reader, 2 CPU, 3 VRAM, 4 Display controller, 5 Display, 6 Cholesteric liquid crystal panel, 7 Scan electrode drive circuit, 8 Data electrode drive circuit, 9 Pixel electrode drive circuit, 10 Level shifter, 11 Voltage selection signal generation circuit , 12 Second stage data latch circuit, 13 First stage data latch circuit, 14 Enable signal transfer circuit

Claims (8)

Pixel data transmitting means for transmitting pixel data for each line in the display body and data for receiving the pixel data transmitted by the pixel data transmitting means, driving the data electrode of each pixel, and displaying the pixels of the line An image display device including an electrode drive circuit,
The data electrode driving circuit includes:
A data input means for inputting a predetermined number of adjacent data electrodes into one set and sequentially inputting pixel data corresponding to each of the one set of data electrodes to the set of data electrodes;
In each of the data electrodes, pixel data corresponding to a predetermined data electrode input first is displayed first, and pixel data corresponding to another data electrode among pixel data corresponding to the one set of data electrodes is displayed. When input, the other data electrode comprises electrode control means for displaying the input pixel data,
The pixel data transmitting means sequentially transmits pixel data corresponding to a predetermined data electrode of each of the set of data electrodes to each set of data electrodes.   The pixel data transmission means outputs pixel data in the same input order in each set of the data electrodes for one line of the display screen in the arrangement order of each set of the data electrodes, and outputs the pixel data in the entire input order. 2. The image display device according to claim 1, wherein the line unit display process for outputting one line is sequentially executed for each line of the display screen.   The pixel data transmitting means executes group-unit display processing for sequentially outputting pixel data of the same input order in each set of the data electrodes for the lines of the entire display screen over the entire input order for each set of the data electrodes. The image display device according to claim 1. The pixel data transmission means transmits pixel data in an order corresponding to the arrangement of the data electrodes in the one set of data electrodes,
The data input means sequentially inputs the pixel data transmitted by the pixel data transmission means to the one set of data electrodes,
Each time the pixel data is input to the one set of data electrodes, the electrode control means displays the input pixel data as a predetermined data electrode corresponding to the pixel data and a corresponding pixel data not input. The image display device according to claim 1, wherein the process of displaying on another data electrode is repeated. The electrode control means includes
First storage means provided corresponding to each of the set of data electrodes;
Selecting means for selecting data to be input to each of the first storage means,
The data input means includes
Second storage means for sequentially storing pixel data to be input to the first storage means corresponding to the one set of data electrodes;
The selecting means selects either pixel data sequentially stored in the second storage means or output data of the first storage means itself according to a predetermined selection signal input in synchronization with the pixel data. 5. The image display device according to claim 1, wherein the image display device inputs the first storage unit. A data electrode driving circuit for driving the data electrode of each pixel corresponding to the input of pixel data for each line in the display body and displaying the pixels of the line,
A data input means for setting a predetermined number of adjacent data electrodes as one set and sequentially inputting each pixel data corresponding to each of the one set of data electrodes to the one set of data electrodes;
In each of the data electrodes, pixel data corresponding to a predetermined data electrode input first is displayed first, and pixel data corresponding to another data electrode among pixel data corresponding to the one set of data electrodes is displayed. When input, electrode control means for displaying the input pixel data in the other data electrode,
A data electrode driving circuit comprising: The data input means sequentially inputs pixel data input in an order corresponding to the arrangement of the data electrodes in the set of data electrodes to the set of data electrodes,
Each time the pixel data is input to the one set of data electrodes, the electrode control means displays the input pixel data as a predetermined data electrode corresponding to the pixel data and a corresponding pixel data not input. 7. The data electrode driving circuit according to claim 6, wherein a process of displaying on another data electrode is repeated. The electrode control means includes
First storage means provided corresponding to each of the set of data electrodes;
Selecting means for selecting data to be input to each of the first storage means,
The data input means includes
Second storage means for sequentially storing pixel data to be input to the first storage means corresponding to the one set of data electrodes;
The selecting means selects either pixel data sequentially stored in the second storage means or output data of the first storage means itself according to a predetermined selection signal input in synchronization with the pixel data. 8. The data electrode driving circuit according to claim 6, wherein the data electrode driving circuit inputs the first storage means.

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