JP2006230100A - Semiconductor device for parallel monitor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for parallel monitor circuits having multiple monitor circuits wherein power consumption can be reduced. <P>SOLUTION: A transistor TRn bypasses a charging current when the voltage of each of capacitors connected in series exceeds a preset reference voltage. A parallel monitor circuit having this transistor is provided on a capacitor-by-capacitor basis. A power saving setting circuit is provided which circuit stops the parallel monitor circuits, and establishes low power consumption mode when the voltage between capacitor terminals is equal to or lower than a predetermined voltage lower than a full charge voltage or the initialization voltage for the capacitors. The power saving setting circuit includes first and second resistors Rn2 and Rn3 and a switch Mn2 connected in series; a comparison circuit CMPn that compares the voltage at the junction point between the first and second resistors with the voltage of a reference voltage circuit Vrn; and a circuit (NMOS transistor Mn1) that turns off the switch Mn2 and stops the operations of the comparison circuit CMPn and the reference voltage circuit Vrn, when the voltage between capacitor terminals becomes lower than the predetermined voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for a parallel monitor circuit in which a plurality of parallel monitor circuits are integrated in order to uniformly charge a plurality of electric double layer capacitors connected in series.

  The electric double layer capacitor can be rapidly charged as compared with a secondary battery that takes time to charge. Moreover, the electric double layer capacitor has an advantage not found in a secondary battery that it can store a large amount of energy. However, since the rated voltage of the electric double layer capacitor is as low as about 3V, usually a plurality of capacitor cells are connected in series to ensure a necessary voltage of 3V or more.

  When charging a plurality of large-capacitance capacitors connected in series in this way, there is a problem of nonuniform charging caused by a capacitance difference between the capacitors, self-charging, self-discharging, or the like.

  As a countermeasure, a charge equalization circuit called “parallel monitor” as disclosed in JP 2000-217250 A (Patent Document 1) is used.

  FIG. 2 is a diagram showing one of the parallel monitor circuits disclosed in Japanese Patent Laid-Open No. 2000-217250 (Patent Document 1). A parallel monitor circuit is provided for each capacitor cell connected in series. Next, one of the parallel monitor circuits will be described.

  Each parallel monitor circuit includes a capacitor C, a reference voltage Vr, a comparator CMP, and a bypass switch element Tr.

  When the capacitor C is charged from a DC power supply (not shown) and the voltage of the capacitor C exceeds the reference voltage Vr, the output of the comparator CMP outputs a high level, and the bypass switch element Tr is turned on. Then, the charging current of the capacitor C flows to the bypass switch element Tr. When the voltage of the capacitor C drops to the reference voltage Vr, the output of the comparator CMP outputs a low level, and the bypass switch element Tr is turned off. In this way, the voltage of the capacitor C is clamped to the same voltage as the reference voltage Vr.

  Since all the capacitors connected in series perform the same operation as described above, it is possible to prevent a specific capacitor from being overcharged due to uneven charging and being deteriorated or destroyed.

  Furthermore, in Japanese Patent Laid-Open No. 2000-217250 (Patent Document 1), another set of parallel monitor circuits similar to the parallel monitor circuit shown in FIG. 2 is added, and the reference voltage of the added parallel monitor circuit is set to the full value of the capacitor C. It also has an initialization function that is set lower than the charging voltage and aligns the voltages of the capacitors C at the initial stage of charging. By having the initialization function, charging loss can be reduced and charging efficiency can be increased.

  However, the conventional parallel monitor circuit is not integrated by a semiconductor device, and is constructed by collecting discrete components, resulting in a large circuit scale and high cost. Therefore, integration by a semiconductor device has been desired.

  However, since the number of capacitors connected in series varies depending on the application, making a semiconductor device with a different number of parallel monitor circuits integrated in accordance with the application will result in high-mix low-volume production. The cost merit of the semiconductor device cannot be utilized, and the cost of the semiconductor device becomes too high to be practical. Further, even if a semiconductor device in which only one parallel monitor circuit is integrated is produced, the circuit scale of the entire parallel monitor circuit cannot be made very small, and there is almost no merit of integration.

  Therefore, when 5 to 10 parallel monitor circuits are integrated in one semiconductor device and charge control of more capacitors than the integrated number is performed, a large number of the same semiconductor devices are connected in cascade, so that many A semiconductor device that controls charging of a capacitor is conceivable. This makes it possible to mass-produce semiconductor devices, and to reduce the circuit scale and cost of the entire parallel monitor circuit.

JP 2000-217250 A

  However, in practice, it is not always the case that all the parallel monitor circuits included in the semiconductor device are used up. For example, three semiconductor devices each including five parallel monitor circuits are used to charge 12 capacitors. In this case, three unused parallel monitor circuits are generated.

  In the case of a semiconductor device including a plurality of parallel monitor circuits, a parallel monitor circuit that is not used can normally charge a capacitor connected to another parallel monitor circuit by short-circuiting the capacitor connection terminal. However, even in such a case, power is wasted because the parallel monitor circuit that is not used is also supplied with power.

  Even in the parallel monitor circuit to which the capacitor is connected, the parallel monitor circuit detects the full charge of the capacitor, and thus consumes power wastefully from the start of charge to full charge.

  Furthermore, as described in the background art, it is known that the parallel monitor circuit improves the charging efficiency by performing the initialization to start charging after aligning the charging voltage of each capacitor to a predetermined voltage in the initial stage of charging. ing. Until the voltage to be initialized is reached, the parallel monitor circuit does not need to operate as in the case of full charge described above.

  The present invention has been made in consideration of the above-described circumstances, and an object thereof is to provide a semiconductor device for a parallel monitor circuit having a plurality of parallel monitor circuits capable of reducing power consumption.

  In order to achieve the above object, the present invention has the following configuration. Hereinafter, the structure for each claim will be described.

a) According to the first aspect of the present invention, when charging a plurality of capacitors connected in series by applying a DC power supply, the voltages of the capacitors are set in advance in order to charge the plurality of capacitors equally. A parallel monitor circuit semiconductor device provided for each of the capacitors, wherein a parallel monitor circuit that bypasses a charging current when the reference voltage exceeds a predetermined reference voltage, wherein a voltage between terminals of the capacitor is lower than a full charge voltage of the capacitor. It is characterized in that a power saving setting circuit for stopping the operation of the parallel monitor circuit and shifting to the low power consumption mode when the voltage is lower than the voltage is provided.

b) According to the second aspect of the present invention, when charging a plurality of capacitors connected in series by applying a DC power supply, the respective voltages of the capacitors are set in advance in order to charge the plurality of capacitors equally. The parallel monitor circuit semiconductor device is provided for each capacitor with a parallel monitor circuit that bypasses the charging current when the reference voltage is exceeded, and the capacitor inter-terminal voltage is the initializing operation of the capacitor (at the initial charging stage). Power saving setting for stopping the operation of the parallel monitor circuit and shifting to the low power consumption mode when the voltage is lower than a predetermined voltage lower than the initializing voltage when performing the operation of aligning the charging voltage of each capacitor to a predetermined voltage) It is characterized by having a circuit.

c) According to the invention of claim 3, the power saving setting circuit includes a first and second resistors and a switch connected in series, a voltage at a connection point of the first and second resistors, and a voltage of the reference voltage circuit. And a circuit that turns off the switch and stops the operation of the comparison circuit and the reference voltage circuit when the voltage between the terminals of the capacitor becomes lower than a predetermined voltage.
d) The invention according to claim 4 uses an electric double layer capacitor as the capacitor.

  According to the present invention, when the capacitor connection terminals are short-circuited, the voltage of the capacitor is a predetermined voltage (a predetermined voltage lower than the full charge voltage of the capacitor, or initialization when performing the capacitor initialization operation) Until the voltage reaches a predetermined voltage lower than the voltage), the operation of the comparison circuit and the reference voltage circuit included in the parallel monitor circuit is stopped to set the power consumption to a minimum, and the capacitor voltage detection resistor is supplied with power. Since the operation is stopped, the power consumption of the parallel monitor circuit can be minimized, and the charging efficiency can be further increased. This is particularly effective when an electric double layer capacitor is used as the capacitor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a parallel monitor circuit diagram according to an embodiment of the present invention.

  In the present invention, a plurality of parallel monitor circuits are included in one semiconductor device. However, FIG. 1 shows the configuration of an arbitrary one of the parallel monitor circuits n included in the semiconductor device. FIG.

  As shown in the figure, any one parallel monitor circuit n (n is an integer and corresponds to n of the capacitor Cn) includes a resistor Rn2, a resistor Rn3, an NMOS transistor Mn2, and a reference voltage circuit Vrn connected in series. And a comparison circuit CMPn, an inverter INVn, a constant current load In and an NMOS transistor Mn1 connected in series, a resistor Rn1 and a transistor TRn connected in series, and a capacitor (electric double layer capacitor) Cn.

  Further, the terminal Celln of the parallel monitor circuit n provided on the highest voltage side is connected to the power supply voltage Vdd, and the terminal Celln-1 of the parallel monitor circuit 1 provided on the lowest voltage side is grounded.

  Of the resistors Rn2 and Rn3 connected in series, the drain of the NMOS transistor Mn2 is connected to the other end of the resistor Rn3 that is not connected to the resistor Rn2.

  Further, the other end of the resistor Rn2 that is not connected to the resistor Rn3 is connected to the positive connection terminal Celln of the capacitor Cn, and the source of the NMOS transistor Mn2 is connected to the negative connection terminal Celln-1 of the capacitor Cn. When the NMOS transistor Mn2 is connected and is on, a voltage proportional to the capacitor Cn terminal voltage is output from the intersection of the resistors Rn2 and Rn3.

  The voltage at the intersection of the resistors Rn2 and Rn3 is applied to the non-inverting input (+) of the comparison circuit CMPn. A reference voltage (Vrn) that is an output of the reference voltage circuit Vrn is applied to the inverting input (−). The reference voltage (Vrn) is set to the same voltage as the voltage at the intersection of the resistor Rn2 and the resistor Rn3 when the capacitor Cn is fully charged.

  The output of the comparison circuit CMPn is connected to the base of the transistor TRn via the terminal OUTn. The collector of the transistor TRn is connected to the positive terminal of the capacitor Cn via the resistor Rn1, and the emitter is connected to the negative terminal of the capacitor Cn.

  The gate of the NMOS transistor Mn1 is connected to the positive terminal of the capacitor Cn via the terminal Celln, the drain of the NMOS transistor Mn1 is connected to the power source Vdd via the constant current load In, and the source of the NMOS transistor Mn1 is connected to the terminal Celln-1. To the negative terminal of the capacitor Cn. The drain of the NMOS transistor Mn1 is also connected to the input of the inverter INVn.

  The output of the inverter INVn is connected to the CE terminal of the comparison circuit CMPn and the reference voltage circuit Vrn and the gate of the NMOS transistor Mn2. The CE terminals of the comparison circuit CMPn and the reference voltage circuit Vrn are terminals for controlling the operation of both circuits. In this embodiment, when a low level is applied to the CE terminal, the operations of both circuits are stopped and the consumption of both circuits is reduced. Minimize power.

  The parallel monitor circuit n of FIG. 1 is a circuit built in the semiconductor device on the left side with terminals Celln, OUTn, and Celln-1 as boundaries, and the right side is an external circuit.

Next, the operation of the parallel monitor circuit n according to the present invention will be described in detail.
(A) The embodiment of claim 2 When the terminal Celln and the terminal Celln-1 are short-circuited or the voltage across the capacitor Cn is lower than the threshold voltage of the NMOS transistor Mn1, the NMOS transistor Mn1 is turned off. The input of INVn is high level and the output is low level.

  Then, since the NMOS transistor Mn2 is turned off, power supply to the series circuit of the resistors Rn2 and Rn3 is stopped. Further, since the CE terminals of the comparison circuit CMPn and the reference voltage circuit Vrn are at a low level, the operations of the comparison circuit CMPn and the reference voltage circuit Vrn are stopped, and the power consumption is minimized.

  At this time, the output of the comparison circuit CMPn is designed to be in a high impedance state, and since the base current of the transistor TRn cannot be supplied, the transistor TRn is turned off.

  When the charging of the capacitor Cn proceeds and the terminal voltage of the capacitor Cn exceeds the threshold voltage of the NMOS transistor Mn1, the NMOS transistor Mn1 is turned on, and the input of the inverter INVn becomes low level, so that the output of the inverter INVn becomes high level.

  Then, since the NMOS transistor Mn2 is turned on, power is supplied to the series circuit of the resistors Rn2 and Rn3, and a voltage proportional to the capacitor Cn voltage is output from the intersection of both resistors.

  When the output of the inverter INVn becomes high level, the CE terminals of the comparison circuit CMPn and the reference voltage circuit Vrn become high level, so that the comparison circuit CMPn and the reference voltage circuit Vrn operate. At this time, since the voltage at the intersection of the resistors Rn2 and Rn3 is still lower than the reference voltage value (Vrn1), the output of the comparison circuit CMPn remains at a low level, and the transistor TRn remains off.

(B) Embodiment of Claim 1 This embodiment has substantially the same configuration as the embodiment of (a), and only the reference voltage value (Vrn2) and the threshold voltage of the NMOS transistor Mn1 are different.

  In this embodiment, when the charging progresses and the voltage across the capacitor Cn reaches a predetermined voltage slightly lower than the fully charged voltage, the NMOS transistor Mn1 is turned on, and the comparison circuit CMPn and the reference voltage circuit Vrn start operating.

  When the voltage at the intersection of the resistors Rn2 and Rn3 exceeds the reference voltage value (Vrn2), the output of the comparison circuit CMPn becomes high level. Then, the transistor TRn is turned on, and the charging current of the capacitor Cn is bypassed via the resistor Rn1. For this reason, overcharge of the capacitor Cn can be prevented.

  As described above, until the voltage of the capacitor Cn reaches a predetermined voltage, that is, the threshold voltage of the NMOS transistor Mn1, the operations of the comparison circuit CMPn and the reference voltage circuit Vrn included in the parallel monitor circuit n are stopped to consume power. Since the power supply to the series circuit of the resistor Rn2 and the resistor Rn3 is stopped, the capacitor connection terminal Celln and Celln-1 are short-circuited, or the charging voltage of the capacitor Cn is When it is low, the power consumption of the parallel monitor circuit can be minimized. As a result, the charging efficiency can be increased.

  Although not shown in FIG. 1, it is possible to provide both a parallel monitor circuit for performing an initialization operation and a parallel monitor circuit for charging up to a full charge voltage. The parallel monitor circuit for performing the initialization operation sets the threshold voltage of the NMOS transistor Mn1 to be equal to or lower than the capacitor voltage for initialization, and the parallel monitor circuit for charging to the full charge voltage satisfies the threshold voltage of the NMOS transistor Mn1. A predetermined voltage slightly lower than the charging voltage is set. Thereby, power saving of both parallel monitor circuits can be achieved.

  In FIG. 1, a semiconductor device having a plurality of parallel monitor circuits is connected to each terminal of a plurality of capacitors connected in series via an external circuit unit. An electric double layer capacitor module with low power consumption can be realized by integrating and integrating the circuit unit and the parallel monitor circuit having the configuration as in the above embodiment.

It is a circuit diagram of a parallel monitor showing an embodiment of the present invention. It is a circuit diagram of the parallel monitor for demonstrating a prior art.

Explanation of symbols

CMPn: comparison circuit Vrn: reference voltage circuit Mn1, Mn2: NMOS transistor TRn: transistor Cn: capacitor INVn: inverter Rn1-3: resistance In: current source (constant current load)

Claims (4)

When charging a plurality of capacitors connected in series by applying a DC power supply, charging is performed when each voltage of the capacitors exceeds a preset reference voltage in order to charge the plurality of capacitors equally. A parallel monitoring circuit semiconductor device in which a parallel monitoring circuit for bypassing current is provided for each capacitor,
A power saving setting circuit is provided that stops the operation of the parallel monitor circuit and shifts to a low power consumption mode when a voltage between terminals of the capacitor is equal to or lower than a predetermined voltage lower than a full charge voltage of the capacitor. A semiconductor device for a parallel monitor circuit. When charging a plurality of capacitors connected in series by applying a DC power supply, charging is performed when each voltage of the capacitors exceeds a preset reference voltage in order to charge the plurality of capacitors equally. A parallel monitoring circuit semiconductor device in which a parallel monitoring circuit for bypassing current is provided for each capacitor,
Power saving setting for stopping the operation of the parallel monitor circuit and shifting to the low power consumption mode when the voltage between the terminals of the capacitor is equal to or lower than an initialization voltage when performing the initialization operation of the capacitor A parallel monitoring circuit semiconductor device comprising a circuit.   The power saving setting circuit includes first and second resistors and a switch connected in series, a comparison circuit that compares a voltage at a connection point of the first and second resistors with a voltage of a reference voltage circuit, 3. The circuit according to claim 1, further comprising a circuit for turning off the switch and stopping the operation of the comparison circuit and the reference voltage circuit when a voltage between terminals of the capacitor becomes lower than a predetermined voltage. The semiconductor device for a parallel monitor circuit as described.   4. The semiconductor device for a parallel monitor circuit according to claim 1, wherein the capacitor is an electric double layer capacitor.

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