JP3954081B1 - Power storage device - Google Patents

Abstract

Power consumption of a voltage monitoring circuit connected to each electric double layer capacitor in a capacitor bank is reduced.
A capacitor bank including an electric double layer capacitor C in series and a voltage monitoring circuit 11 connected in parallel between terminals of each electric double layer capacitor C and operating by obtaining power from the electric double layer capacitor C. And a control means 30 for setting the capacitor bank 10 to the charge mode, the discharge mode, and the standby mode. And a charge monitoring comparator for stopping further discharge when the voltage of the electric double layer capacitor C reaches a low voltage side threshold value in the discharge mode. When the capacitor bank 10 is in the standby mode, the charge monitoring comparator and the discharge monitoring comparator are In both cases, the operating power supply is stopped.
[Selection] Figure 1

Description

  The present invention relates to a power storage device having a capacitor bank formed by connecting a plurality of electric double layer capacitors in series, and more specifically, minimizes power consumed by a voltage monitoring circuit connected to each electric double layer capacitor. It is related to the technology to suppress.

  An electric double layer capacitor not only has a large capacitance, but also can be rapidly charged compared to a secondary battery, can handle instantaneous high-power discharge, and has a semi-permanent charge / discharge cycle life. It is considered promising as an uninterruptible power supply (UPS) for facilities and power storage devices for electric vehicles, and in some fields, it has already entered the stage of practical application.

  In this type of electric storage device using an electric double layer capacitor, a plurality of electric double layer capacitors are usually connected in series in order to increase the withstand voltage, and this is referred to as a “capacitor bank” in this specification. ing.

  By the way, when a plurality of electric double layer capacitors are connected in series as described above, each of them does not necessarily have the same characteristics. For example, the capacitor capacitance and leakage current characteristic values have a certain tolerance in manufacturing. In addition, temperature non-uniformity may occur inside the capacitor bank during use.

  In such a case, it is described in Patent Document 1 and Patent Document 2 in order to equalize the charge / discharge voltage of each electric double layer capacitor so that the maximum energy can be stored without exceeding the rated voltage of the capacitor. As shown, a voltage monitoring circuit is connected to each electric double layer capacitor.

  Since this voltage monitoring circuit is connected in parallel between the terminals of the electric double layer capacitor, it is referred to as a “parallel monitoring circuit” in Patent Document 2 and the like. Sometimes called a parallel monitor circuit.

  The parallel monitor circuit includes, as a basic configuration, first and second comparators that monitor a charging voltage. The first comparator is for monitoring the initialization voltage, and the output of the first comparator controls on / off of the switching element for bypassing the charging current connected in parallel between the terminals of the electric double layer capacitor.

  That is, the first comparator turns on the switching element when the voltage of the electric double layer capacitor reaches a predetermined initialization voltage. Thereby, since the charging current for the electric double layer capacitor flows through the bypass circuit of the switching element, the charging voltage of each electric double layer capacitor can be made equal to the initialization voltage.

  The second comparator is for monitoring the upper limit voltage. The upper limit voltage is higher than the initialization voltage, and is set to, for example, a rated voltage (full charge voltage). The first comparator and the second comparator are alternatively selected by the control means so that one of them operates. When the second comparator is selected, the electric double layer capacitor is charged to the upper limit voltage.

  Discharge that causes the voltage of the electric double layer capacitor to be negative is not a practical use state in practice, and in some cases, deteriorates the characteristics of the capacitor. Therefore, the parallel monitor circuit is provided with a third comparator for detecting the lower limit voltage of the electric double layer capacitor at the time of discharging, and when any of the electric double layer capacitors in the capacitor bank reaches the lower limit voltage, the discharge of the capacitor bank is performed. It has also been stopped.

Japanese Patent Application Laid-Open No. 06-261452 Japanese Patent No. 3306325

  As described above, the conventional parallel monitor circuit includes the first comparator for initialization, the second comparator for monitoring the upper limit voltage, and the third comparator for monitoring the lower limit voltage. The operating power supply is obtained from the electric double layer capacitor to be monitored. Therefore, for example, in a capacitor bank applied to an energy-saving device that requires severe power storage efficiency, it is necessary to suppress the power consumed by the parallel monitor as much as possible.

  Originally, the monitoring function of the third comparator for monitoring the lower limit voltage is unnecessary during charging, whereas the functions of the first comparator for initialization and the second comparator for monitoring the upper limit voltage are unnecessary during discharging.

  However, in the conventional parallel monitor circuit, a reference voltage circuit (initialization voltage, upper limit voltage, and lower limit voltage circuit included in each comparator) is included in each comparator even during charging, discharging and during standby. ) And a current is always consumed by a comparator circuit composed of, for example, an IC element.

  Therefore, especially when the standby time is long, not only is the power consumption non-negligible, but the discharge energy is insufficient during use, for example in applications such as uninterruptible power supplies (UPS) and electric vehicles. The function as a capacitor bank may not be fulfilled.

  Accordingly, an object of the present invention is to provide a power storage device including a capacitor bank in which a plurality of electric double layer capacitors are connected in series, and a voltage monitoring circuit (parallel monitoring circuit) is connected to each electric double layer capacitor. Is to reduce power consumption in the voltage monitoring circuit as much as possible.

  In order to solve the above-described problems, the present invention provides a capacitor bank formed by connecting a plurality of electric double layer capacitors in series and a parallel connection between terminals of each electric double layer capacitor. And a voltage monitoring circuit that operates by obtaining power from the electric double layer capacitor, and the capacitor bank is set in a charging mode and a discharging mode based on an output signal from the voltage monitoring circuit and / or an instruction signal from the operation unit. Alternatively, in the power storage device including a control unit that is in any of the standby modes, the voltage monitoring circuit includes a high voltage side threshold value and a low voltage side threshold value that are arbitrarily set for use with respect to the electric double layer capacitor. In the voltage monitoring circuit, the voltage of the electric double layer capacitor reaches the high voltage side threshold in the charging mode. A charge monitoring comparator that outputs a signal that restricts charging at the time, and a discharge that outputs a signal that stops further discharge when the voltage of the electric double layer capacitor reaches the low-voltage side threshold value in the discharge mode A monitoring comparator, and when the capacitor bank is in the standby mode, the control means sets both the charge monitoring comparator and the discharge monitoring comparator to a stopped state in which no operating power is consumed. It is characterized by that.

  In a preferred aspect of the present invention, as described in claim 2, when the capacitor bank is in the discharge mode, the control means sets the discharge monitoring comparator in an operating state, and In a mode in which the charge monitoring comparator is set to a stop state in which the operating power is not consumed, and the control unit is configured to set the charge monitoring comparator when the capacitor bank is in the charging mode. A mode in which the comparator is in an operating state and the discharge monitoring comparator is in a stopped state in which no operating power is consumed.

  According to a fourth aspect of the present invention, the high voltage side threshold includes an initialization voltage for aligning the charging voltage of the electric double layer capacitor, and an upper limit voltage allowed for the electric double layer capacitor ( ≧ initialization voltage) are included, and the discharge monitoring comparator may include two comparators, the initialization voltage monitoring comparator and the upper limit voltage monitoring comparator. .

  According to the present invention, when the capacitor bank is in the standby mode that is neither the charge mode nor the discharge mode, both the charge monitoring comparator and the discharge monitoring comparator included in the voltage monitoring circuit consume operating power. By stopping the operation of the voltage monitoring circuit, that is, by stopping all operations of the voltage monitoring circuit, the current consumption in the voltage monitoring circuit becomes almost zero, thereby preventing a wasteful loss of energy stored in the electric double layer capacitor. be able to.

  Next, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic block diagram showing an overall configuration of a power storage device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a voltage monitoring circuit, and FIG. 3 is a graph showing a capacitor voltage controlled by the voltage monitoring circuit. is there.

  As shown in FIG. 1, the power storage device of the present invention includes a capacitor bank 10 formed by connecting a plurality (three in this example) of electric double layer capacitors C1, C2, and C3 in series. When there is no need to distinguish each electric double layer capacitor, the reference symbol is simply C. As each electric double layer capacitor C, a capacitor cell in which unit capacitor cells are arbitrarily connected in series and parallel may be used.

  For each electric double layer capacitor C1, C2, C3 included in the capacitor bank 10, a parallel monitor circuit 11 as a voltage monitoring circuit is connected between the terminals. The capacitor bank 10 is connected to a charging power source 22 through a charging circuit 21 and is connected to a predetermined load 24 through a discharging circuit 23. The charging method for the capacitor bank 10 is preferably constant current charging from the viewpoint of charging efficiency.

  The charging circuit 21 and the discharging circuit 23 are controlled by the control circuit 30. In this case, the control circuit 30 has three control modes in which the capacitor bank 10 is set to a standby mode that is neither a charge mode, a discharge mode, or any of them. The control circuit 30 can be configured with simple hardware capable of determining each mode of charging, discharging, and standby, or a microcomputer or the like may be used.

  The control circuit 30 is connected to each parallel monitor circuit 11 via the signal transmission circuit 31. The signal transmission circuit 31 is a kind of interface circuit, but each parallel monitor circuit 11 preferably has a voltage conversion function because the common potential is different. Further, when the number of electric double layer capacitors C increases and the capacitor bank becomes a high voltage, it is necessary to separate the control circuit 30 and each parallel monitor circuit 11 by a photocoupler or the like.

  As shown in FIG. 2, the parallel monitor circuit 11 includes three comparators U1, U2, and U3, and a transistor TR1 that is included in the bypass circuit that bypasses the charging current for the electric double layer capacitor C during charging together with the current limiting resistor R. Prepare.

  The control circuit 30 controls the electric double layer capacitor C in each of charging, discharging, and standby modes as shown in the graph of FIG. 3 based on the instruction signal from the operation unit 32 and / or the output from the parallel monitor circuit 11. To do.

  The comparator U1 is a comparator that initializes the electric double layer capacitor C so that the charging voltages of the electric double layer capacitors C1, C2, and C3 are equal to a predetermined initialization voltage Vini that is set in advance. When the voltage of the electric double layer capacitor C reaches the initialization voltage Vini, the transistor TR1 is turned on to bypass the charging current, and the electric double layer capacitor C operates so as not to be charged more than the initialization voltage Vini.

  The transistor TR1 is turned on only when the output of the comparator U1 becomes Hi while the initialization instruction is issued from the control circuit 30. When the initialization instruction has not been issued from the control circuit 30, it remains off even if the output of the comparator U1 becomes Hi.

  The comparator U2 is a comparator that detects whether the voltage of the electric double layer capacitor C has reached an upper limit voltage (for example, a nominal rated voltage (also referred to as a full charge voltage)) Vfull at the time of charging. When the voltage reaches the upper limit voltage Vfull, an upper limit voltage signal (overvoltage signal) is output to the control circuit 30.

  When this upper limit voltage signal is output, the control circuit 30 limits charging. This charging restriction includes a state where charging is stopped and a relaxed charging state where charging is performed by narrowing the charging current. Normally, the initialization voltage Vini is set to a voltage lower than the upper limit voltage Vfull, but may be set to Vini = Vfull. In such a case, one comparator is sufficient for the comparators U1 and U2.

  The comparator U3 is a comparator that detects a lower limit voltage (minimum voltage) Vbottom of the discharge voltage so that the voltage of the electric double layer capacitor C is not reversely charged at the time of subsequent charging, for example. When the voltage reaches the lower limit voltage Vbottom, the lower limit voltage signal is output to the control circuit 30.

  The control circuit 30 controls the voltage of the capacitor bank 10 or each electric double layer capacitor C based on the output signals from these three comparators U1, U2, U3 as shown in the graph of FIG. Whether the charging voltage Vini or the upper limit voltage Vfull is charged or at which point the standby mode is set depends on an instruction from the operation unit 32.

  As can be seen from the graph of FIG. 3, when there is an initialization instruction at the time of charging, it is charged to the initialization voltage Vini, but when there is no initialization instruction, it is charged to the upper limit voltage Vfull. On the other hand, when the capacitor voltage reaches the lower limit voltage Vbottom during discharge, the discharge is stopped.

  It is normal usage to charge and discharge within the range of the upper limit voltage Vfull and the lower limit voltage Vbottom, and when it is outside this range, the charge / discharge is forcibly stopped. Therefore, it is necessary to monitor the upper limit voltage Vfull during charging, and it is necessary to monitor the lower limit voltage Vbottom during discharging.

  The comparators U1, U2, and U3 are connected in parallel between the terminals of the electric double layer capacitor C, and the operation power source is obtained from the electric double layer capacitor C. The control circuit 30 includes circuit activation signals EN1, EN2, and EN3 that are output to the comparators U1, U2, and U3 according to the operation mode of the capacitor bank 10 in order to suppress power consumption in the parallel monitor circuit 11 as much as possible.

  That is, when the capacitor bank 10 is in the standby mode, the capacitor voltage does not change greatly. Therefore, the control circuit 30 turns off the circuit activation signals EN1, EN2, and EN3 for the comparators U1, U2, and U3 in parallel. The monitoring operation of the monitor circuit 11 is stopped. As a result, the current consumption in the parallel monitor circuit 11 becomes substantially zero, so that a wasteful loss of energy stored in the electric double layer capacitor C is prevented.

  Next, when the capacitor bank 10 is in the discharge mode, the voltage of the capacitor only decreases, so that overvoltage monitoring and initialization operation are not necessary. Therefore, in the discharge mode, the circuit activation signals EN1 and EN2 for the comparators U1 and U2 are turned off, and only the circuit activation signal EN3 for the comparator U3 is turned on. When the lower limit voltage is detected by the comparator U3 during this discharge, the control circuit 30 stops discharging the capacitor bank 10 and prevents the deterioration of the capacitor characteristics due to use at a deep depth.

  Next, when the capacitor bank 10 is in the charging mode, it is not necessary to monitor the lower limit voltage. Therefore, the circuit activation signal EN3 for the comparator U3 is preferably turned off, and the circuit activation signals EN1 and EN2 for the comparators U1 and U2 are turned off. Turn on.

  Thus, when there is no initialization instruction, charging is performed to the upper limit voltage Vfull under overvoltage monitoring by the comparator U2, and when there is an initialization instruction, the comparator U1 reaches the initialization voltage Vini. Charging is performed.

  Note that when this power storage device is applied particularly to a large power uninterruptible power supply device or an inverter device, the power consumed by the parallel monitor circuit 11 is small compared to the stored energy during charging. The circuit activation signal EN3 for the comparator U3 may be turned on.

  The present invention has been described based on the illustrated example. However, when the initialization voltage Vini is set to the upper limit voltage Vfull, one of the comparators U1 and U2 can be omitted. In addition to the comparator function, for example, an element having an arithmetic function or the like may be used for the comparators U1, U2, and U3.

1 is a schematic block diagram showing an overall configuration of a power storage device according to the present invention. The circuit diagram which shows the structure of a voltage monitoring circuit. The graph which shows the capacitor voltage controlled by a voltage monitoring circuit.

Explanation of symbols

10 capacitor bank 11 voltage monitoring circuit (parallel monitoring circuit)
21 Charging Circuit 22 Charging Power Supply 23 Discharging Circuit 24 Load 30 Control Circuit 31 Signal Transmission Circuit C (C1, C2, C3) Electric Double Layer Capacitor U1, U2, U3 Comparator

Claims (4)

A capacitor bank formed by connecting a plurality of electric double layer capacitors in series; a voltage monitoring circuit connected in parallel between the terminals of each of the electric double layer capacitors; In a power storage device comprising a control means for setting the capacitor bank to a charging mode, a discharging mode or a standby mode which is neither of them based on an output signal from a voltage monitoring circuit and / or an instruction signal from an operation unit,
The voltage monitoring circuit includes a high voltage side threshold value and a low voltage side threshold value that are arbitrarily set for use with respect to the electric double layer capacitor,
The voltage monitoring circuit includes a charge monitoring comparator that outputs a signal for limiting charging when the voltage of the electric double layer capacitor reaches the high-voltage side threshold in the charging mode, and the electric power in the discharging mode. A discharge monitoring comparator that outputs a signal to stop further discharge when the voltage of the double layer capacitor reaches the low voltage side threshold,
When the capacitor bank is in the standby mode, the control means places both the charge monitoring comparator and the discharge monitoring comparator in a stopped state in which no operating power is consumed.   The control means sets the discharge monitoring comparator to an operating state when the capacitor bank is in the discharging mode, and sets the charging monitoring comparator to a stopped state in which no operating power is consumed. The power storage device according to 1.   The control means sets the charge monitoring comparator to an operating state when the capacitor bank is in the charging mode, and sets the discharge monitoring comparator to a stopped state in which no operating power is consumed. The power storage device according to 1. The high voltage side threshold value includes two threshold values: an initialization voltage for aligning the charging voltage of the electric double layer capacitor and an upper limit voltage (≧ initialization voltage) allowed for the electric double layer capacitor. And
4. The discharge monitoring comparator includes two comparators, the initialization voltage monitoring comparator and the upper limit voltage monitoring comparator, respectively. 5. Power storage device.

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