JP2006222213A - Surge protecting semiconductor device and its manufacturing method - Google Patents

Surge protecting semiconductor device and its manufacturing method Download PDF

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JP2006222213A
JP2006222213A JP2005033103A JP2005033103A JP2006222213A JP 2006222213 A JP2006222213 A JP 2006222213A JP 2005033103 A JP2005033103 A JP 2005033103A JP 2005033103 A JP2005033103 A JP 2005033103A JP 2006222213 A JP2006222213 A JP 2006222213A
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Kazuhiro Onishi
一洋 大西
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a surge protecting semiconductor device with higher surge resistance. <P>SOLUTION: A second p-type region 8 is electrically floating. The p-type region 8 is formed to generate a depletion layer DL covering at least a surface layer S23 of a joint J23 between a first p-type region 3 and an n-type semiconductor substrate 2 while no voltage is applied to a back electrode 7 (zero bias) or large voltage is applied by ESD. When static surge (ESD) enters from the back electrode 7, the ESD current flows into the first p-type region 3 only from a region not covered with the depletion layer DL in the joint J23. Therefore, no ESD current flows to the surface layer S23 with reduced surge resistance due to a surface defect. If the ESD enters from a first front electrode 5, a current path is limited by the depletion layer DL, and as a result the ESD can be discharged from the back electrode 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はサージ保護用半導体素子およびその製造方法に関する。   The present invention relates to a semiconductor device for surge protection and a method for manufacturing the same.

静電気放電（以下、ＥＳＤ（Electro Static Discharge）と記す。）は、半導体装置の破壊や破損を招く一大要因である。半導体装置をＥＳＤ等のサージから保護するために、従来からサージ保護用半導体素子が用いられている。   Electrostatic discharge (hereinafter referred to as ESD (Electro Static Discharge)) is a major factor that causes destruction and breakage of semiconductor devices. In order to protect a semiconductor device from a surge such as ESD, a semiconductor element for surge protection has been conventionally used.

例えば発光ダイオード（ＬＥＤ：Light Emitting Diode）は、ＧａＡｓ（砒素化ガリウム）やＧａＮ（窒化ガリウム）等の化合物半導体でなるために、サージに対して非常に弱い。よって、サージが侵入した場合にも、耐電圧を越える電圧がＬＥＤに印加されないようにするために、ＬＥＤにサージ保護用半導体素子を並列接続して同封したＬＥＤパッケージが提案されている（例えば特許文献１、特許文献２参照）。   For example, a light emitting diode (LED) is very weak against surge because it is made of a compound semiconductor such as GaAs (gallium arsenide) or GaN (gallium nitride). Therefore, in order to prevent a voltage exceeding the withstand voltage from being applied to the LED even when a surge enters, an LED package is proposed in which a semiconductor element for surge protection is connected in parallel to the LED (for example, a patent). Reference 1 and Patent Reference 2).

図４は、従来のサージ保護用半導体素子１００の一例を示している。このサージ保護用半導体素子１００は、Ｎ型半導体基板１０２、Ｐ型領域１０３、絶縁膜１０４、第１の表面電極１０５、第２の表面電極１０６および、裏面電極１０７を備えている。ＰＮ接合されたＰ型領域１０３とＮ型半導体基板１０２、および、これらの表面に設けられた第１の表面電極１０５と裏面電極１０７でツェナーダイオードが構成されている。   FIG. 4 shows an example of a conventional surge protection semiconductor element 100. The surge protection semiconductor element 100 includes an N-type semiconductor substrate 102, a P-type region 103, an insulating film 104, a first surface electrode 105, a second surface electrode 106, and a back electrode 107. The PN junction P-type region 103 and N-type semiconductor substrate 102, and the first surface electrode 105 and the back surface electrode 107 provided on these surfaces constitute a Zener diode.

図５は、このサージ保護用半導体素子１００を同封したＬＥＤパッケージ１３０を示している（括弧内の数字はここでは無視する）。また、図５（ｂ）は、図５（ａ）の回路図である。サージ保護用半導体素子１００は、正電圧の供給を受けるフレーム１１０ａ上に配置されて、ＬＥＤ１２０と共に透明樹脂部１１２で封止されている。第１の表面電極１０５は、ワイヤ１１１によってフレーム１１０ｂ（アース）に接続されている。ＬＥＤ１２０は、そのＰ側電極およびＮ側電極が、それぞれ第２の表面電極１０６および第１の表面電極１０５と電気的に接続されている。   FIG. 5 shows an LED package 130 in which the surge protection semiconductor element 100 is enclosed (the numbers in parentheses are ignored here). FIG. 5B is a circuit diagram of FIG. The semiconductor element 100 for surge protection is disposed on a frame 110 a that receives a positive voltage and is sealed with a transparent resin portion 112 together with the LED 120. The first surface electrode 105 is connected to the frame 110 b (earth) by a wire 111. The LED 120 has its P-side electrode and N-side electrode electrically connected to the second surface electrode 106 and the first surface electrode 105, respectively.

フレーム１１０ａを通って裏面電極１０７にＥＳＤが侵入した場合には、図４に示すＮ型半導体基板１０２とＰ型領域１０３の接合部でツェナー降伏が生じるために、第１の表面電極１０５から外部にＥＳＤによる大電流を逃すことができる。よって、第２の表面電極１０６に接続されたＬＥＤ１２０等の保護対象物の破壊や損傷を防止することができる。   When ESD enters the back electrode 107 through the frame 110a, Zener breakdown occurs at the junction between the N-type semiconductor substrate 102 and the P-type region 103 shown in FIG. In addition, a large current due to ESD can be missed. Accordingly, it is possible to prevent destruction or damage of the protection target object such as the LED 120 connected to the second surface electrode 106.

なお、ＬＥＤ１２０を発光させるための通常電圧は、Ｎ型半導体基板１０２とＰ型領域１０３との降伏電圧以下の電圧になっているので、通常電圧印加時には、裏面電極１０７と第１の表面電極１０５間は導通せず、裏面電極１０７と第２の表面電極１０６間のみで導通するようになっている。
特開平１０−２５６６１０号公報 特開２００２−１８５０４９号公報 Note that the normal voltage for causing the LED 120 to emit light is equal to or lower than the breakdown voltage between the N-type semiconductor substrate 102 and the P-type region 103. Therefore, when the normal voltage is applied, the back electrode 107 and the first front electrode 105 are used. There is no conduction between the back electrode 107 and the second front electrode 106.
JP-A-10-256610 JP 2002-185049 A

ところで、ＬＥＤ等保護すべき素子に対するサージ保護効果を高めるためには、サージ保護用半導体素子のサージ耐量を向上させる必要がある。   By the way, in order to enhance the surge protection effect for the elements to be protected such as LEDs, it is necessary to improve the surge resistance of the semiconductor element for surge protection.

従って本発明の目的は、サージ耐量がより高いサージ保護用半導体素子を提供することにある。   Therefore, an object of the present invention is to provide a semiconductor element for surge protection having a higher surge resistance.

本発明に係るサージ保護用半導体素子は、第１導電型の半導体基板と、半導体基板の表面から内部に形成した第１の第２導電型領域と、第１の第２導電型領域から所定の距離だけ離れた位置で第１の第２導電型領域を周回する第２の第２導電型領域と、第１の第２導電型領域の表面と第２の第２導電型領域よりも外側の半導体基板表面の一部とを露出して、半導体基板表面を覆う絶縁膜と、絶縁膜から露出した第１の第２導電型領域に設けた第１の表面電極と、絶縁膜から露出した半導体基板表面に設けた第２の表面電極と、半導体基板の裏面に設けた裏面電極とを備え、第２の第２導電型領域と半導体基板との接合部で発生した空乏層が、第１の第２導電型領域と半導体基板との接合部のうち、少なくとも表面欠陥が存在する領域を覆うことを特徴とする。   A semiconductor device for surge protection according to the present invention includes a first conductivity type semiconductor substrate, a first second conductivity type region formed inside from the surface of the semiconductor substrate, and a predetermined amount from the first second conductivity type region. A second second conductivity type region that circulates the first second conductivity type region at a position separated by a distance; a surface of the first second conductivity type region; and an outer side of the second second conductivity type region. An insulating film that exposes a part of the surface of the semiconductor substrate and covers the surface of the semiconductor substrate, a first surface electrode provided in the first second conductivity type region exposed from the insulating film, and a semiconductor exposed from the insulating film A depletion layer generated at a junction between the second second conductivity type region and the semiconductor substrate is provided with a second surface electrode provided on the substrate surface and a back electrode provided on the back surface of the semiconductor substrate. Of the junction between the second conductivity type region and the semiconductor substrate, cover at least the region having surface defects. The features.

第１の第２導電型領域と第２の第２導電型領域との間の距離ｄ１は、半導体基板の誘電率をε、半導体基板と第２の第２導電型半導体領域との電位差をＶ、電子電荷量をｑ、第１の第２導電型領域と第２の第２導電型領域との間の領域における第１導電型不純物濃度をＮDとするときに、

Figure 2006222213
を満たすようにすればよい。 The distance d1 between the first second conductivity type region and the second second conductivity type region is expressed as follows: the dielectric constant of the semiconductor substrate is ε, and the potential difference between the semiconductor substrate and the second second conductivity type region is V. When the electron charge amount is q and the first conductivity type impurity concentration in the region between the first second conductivity type region and the second second conductivity type region is N D ,
Figure 2006222213
 It only has to satisfy.

本発明に係るサージ保護用半導体素子において、第１の第２導電型領域の平面形状は円形状であり、第２の第２導電型領域の平面形状は、第１の第２導電型領域と中心を同じにする環状であることが望ましい。   In the semiconductor device for surge protection according to the present invention, the planar shape of the first second conductivity type region is circular, and the planar shape of the second second conductivity type region is the same as that of the first second conductivity type region. It is desirable for the ring to have the same center.

本発明に係るサージ保護用半導体素子の製造方法は、第１導電型の半導体基板の表面から内部に、第１の第２導電型領域を形成する工程と、第１の前記第２導電型領域から所定の距離だけ離れた位置で第１の第２導電型領域を周回する第２の第２導電型領域を形成する工程と、第１の第２導電型領域の表面と第２の第２導電型領域よりも外側の半導体基板表面の一部とを露出して、半導体基板を覆う絶縁膜を形成する工程と、絶縁膜から露出した第１の第２導電型領域と半導体基板表面とに、第１および第２の表面電極を形成する工程と、半導体基板の裏面に裏面電極を形成する工程とを備え、第２の第２導電型領域と半導体基板との接合部で発生した空乏層が、第１の第２導電型領域と半導体基板との接合部のうち、少なくとも表面欠陥が存在する領域を覆うように、第２の第２導電型領域を形成することを特徴とする。   A method for manufacturing a semiconductor device for surge protection according to the present invention includes the step of forming a first second conductivity type region from the surface of a first conductivity type semiconductor substrate to the inside, and the first second conductivity type region. Forming a second second conductivity type region that circulates the first second conductivity type region at a position away from the first distance by a predetermined distance, a surface of the first second conductivity type region, and a second second Exposing a part of the surface of the semiconductor substrate outside the conductive type region to form an insulating film covering the semiconductor substrate; a first second conductive type region exposed from the insulating film; and a surface of the semiconductor substrate A depletion layer generated at a junction between the second second conductivity type region and the semiconductor substrate, comprising: forming the first and second surface electrodes; and forming a back electrode on the back surface of the semiconductor substrate. However, at least a surface defect is present in the junction between the first second conductivity type region and the semiconductor substrate. To cover the area to be stationary, and forming a second second conductivity type region.

本発明に係るサージ保護用半導体素子では、基板表面近傍におけるＰＮ接合部分が空乏層で覆われているために、この部分にサージ電流が流れ込むことがない。基板表面には、製造中に受けたストレスによって欠陥（表面欠陥）が発生しているので、基板表面におけるＰＮ接合部のサージ耐量は、基板表面以外におけるＰＮ接合部のサージ耐量よりも低くなっている。本発明に係るサージ保護用半導体素子では、サージ耐量が低い部分への電流の流入を防止することによって、サージ保護用半導体素子全体のサージ耐量を向上させている。よって、本発明に係るサージ保護用半導体素子を用いれば、ＬＥＤ等の保護対象物に対するサージ保護効果をより高めることができる。   In the semiconductor element for surge protection according to the present invention, since the PN junction portion in the vicinity of the substrate surface is covered with the depletion layer, no surge current flows into this portion. Since defects (surface defects) are generated on the surface of the substrate due to stress received during manufacturing, the surge resistance of the PN junction on the substrate surface is lower than the surge resistance of the PN junction other than on the substrate surface. Yes. In the semiconductor element for surge protection according to the present invention, the surge resistance of the entire semiconductor element for surge protection is improved by preventing the current from flowing into the portion where the surge resistance is low. Therefore, if the semiconductor element for surge protection according to the present invention is used, the surge protection effect for a protection object such as an LED can be further enhanced.

（第１の実施形態）
図１（ａ）および（ｂ）は、本発明の実施形態に係るサージ保護用半導体素子１の断面図および、Ｎ型半導体基板２の平面図を示している。このサージ保護用半導体素子１は、Ｎ型半導体基板２、第１のＰ型領域３、第２のＰ型領域８、絶縁膜４、第１の表面電極５、第２の表面電極６および、裏面電極７を備えている。ＰＮ接合されたＮ型半導体基板２と第１のＰ型領域３、および、これらの表面に設けられた第１の表面電極５および裏面電極７でツェナーダイオードが構成されている。 (First embodiment)
FIGS. 1A and 1B show a cross-sectional view of a surge protection semiconductor element 1 according to an embodiment of the present invention and a plan view of an N-type semiconductor substrate 2. The surge protection semiconductor element 1 includes an N-type semiconductor substrate 2, a first P-type region 3, a second P-type region 8, an insulating film 4, a first surface electrode 5, a second surface electrode 6, and A back electrode 7 is provided. A Zener diode is constituted by the PN-junction N-type semiconductor substrate 2 and the first P-type region 3, and the first surface electrode 5 and the back electrode 7 provided on the surface thereof.

Ｎ型半導体基板２は、シリコン基板にリンなどのＮ型不純物が添加された基板である。第１のＰ型領域３および第２のＰ型領域８は、いずれもＮ型半導体基板２の表面から内部に形成された、ボロンなどのＰ型不純物濃度が高い領域である。図１（ｂ）に示すように、第１のＰ型領域３の平面形状は、半径がＲ１の円形状になっている。また、第２のＰ型領域８の平面形状は、内径がＲ２（＞Ｒ１）で第１のＰ型領域と中心を同じにする円環状になっている。なお、第１のＰ型領域３および第２のＰ型領域８の平面形状は、図１（ｂ）に示す形状に限定されるわけではないが、円に近い形状であることが望ましい。   The N-type semiconductor substrate 2 is a substrate in which an N-type impurity such as phosphorus is added to a silicon substrate. Each of the first P-type region 3 and the second P-type region 8 is a region formed in the inside from the surface of the N-type semiconductor substrate 2 and having a high concentration of P-type impurities such as boron. As shown in FIG. 1B, the planar shape of the first P-type region 3 is a circular shape having a radius R1. The planar shape of the second P-type region 8 is an annular shape having an inner diameter of R2 (> R1) and having the same center as the first P-type region. Note that the planar shapes of the first P-type region 3 and the second P-type region 8 are not limited to the shape shown in FIG. 1B, but are preferably close to a circle.

図１（ａ）に示すように、第１の表面電極５は、第１のＰ型領域３上に配置されている。第２の表面電極６は、Ｎ型半導体基板２表面のうち、第２のＰ型領域８よりも外側に配置されている。裏面電極７は、Ｎ型半導体基板２の裏面に形成されている。Ｎ型半導体基板２の表面のうち、第１の表面電極５および第２の表面電極６が形成されていない領域は、周辺部を除いて絶縁膜４で覆われている。   As shown in FIG. 1A, the first surface electrode 5 is disposed on the first P-type region 3. The second surface electrode 6 is disposed outside the second P-type region 8 on the surface of the N-type semiconductor substrate 2. The back electrode 7 is formed on the back surface of the N-type semiconductor substrate 2. Of the surface of the N-type semiconductor substrate 2, a region where the first surface electrode 5 and the second surface electrode 6 are not formed is covered with the insulating film 4 except for the peripheral portion.

第２のＰ型領域８は、第１の表面電極５、第２の表面電極６および、裏面電極７のいずれにも接しておらず、電気的に浮遊状態にある。よって、裏面電極７への電圧非印加時（ゼロバイアス時）にも、ＥＳＤによる大電圧印加時にも、Ｎ型半導体基板２と第２のＰ型領域８との接合部Ｊ２８から空乏層ＤＬが伸びている。   The second P-type region 8 is not in contact with any of the first surface electrode 5, the second surface electrode 6, and the back electrode 7, and is in an electrically floating state. Therefore, the depletion layer DL is formed from the junction J28 between the N-type semiconductor substrate 2 and the second P-type region 8 both when no voltage is applied to the back electrode 7 (at the time of zero bias) and when a large voltage is applied by ESD. It is growing.

第２のＰ型領域８は、接合部Ｊ２８から発生した空乏層ＤＬが、Ｎ型半導体基板２と第１のＰ型領域３との接合部Ｊ２３のうち、絶縁膜４直下の部分（図２（ａ）における表層部Ｓ２３）を覆うように予め設計しておく。このような空乏層ＤＬは、第２のＰ型領域８のＰ型不純物濃度、第１のＰ型領域３と第２のＰ型領域８との間の距離ｄ１、および、第２のＰ型領域の深さｄ３を適当に設計することによって発生させることができる。なお、第２のＰ型領域８の深さｄ３は、Ｎ型半導体基板２において表面欠陥が存在している深さよりも深くなっている必要が有る。   In the second P-type region 8, the depletion layer DL generated from the junction J 28 is a portion immediately below the insulating film 4 in the junction J 23 between the N-type semiconductor substrate 2 and the first P-type region 3 (FIG. 2). It is designed in advance so as to cover the surface layer part S23) in (a). Such a depletion layer DL includes the P-type impurity concentration of the second P-type region 8, the distance d1 between the first P-type region 3 and the second P-type region 8, and the second P-type region. It can be generated by appropriately designing the depth d3 of the region. The depth d3 of the second P-type region 8 needs to be deeper than the depth at which surface defects exist in the N-type semiconductor substrate 2.

第２のＰ型領域８とＮ型半導体基板２との接合部から発生する空乏層ＤＬの幅Ｗは、第１のＰ型領域３と第２のＰ型領域８との間に位置するＮ型半導体基板２の不純物濃度ＮD［ｃｍ-3］と次式（１）に示す関係になっている。

Figure 2006222213
ここで、εは、Ｎ型半導体基板２の誘電率［Ｆ／ｃｍ］、Ｖは、Ｎ型半導体基板２と第２のＰ型領域８との電位差［Ｖ］、ｑは電子電荷量（＝１．６０２×１０-19［Ｃ］）である。第１のＰ型領域３と第２のＰ型領域８との間の距離ｄ１を２μｍとし、Ｎ型半導体基板２の不純物濃度を１０19ｃｍ-3、Ｎ型半導体基板２の誘電率をε＝１．０５×１０-15［Ｆ／ｃｍ］とし、Ｎ型半導体基板２と第２のＰ型領域８との電位差をＶ＝１．１［Ｖ］としたときに、空乏層の幅Ｗを、距離ｄ１と同じ２μｍにするためには、各部を例えば下記のように設計すればよい。 The width W of the depletion layer DL generated from the junction between the second P-type region 8 and the N-type semiconductor substrate 2 is N located between the first P-type region 3 and the second P-type region 8. The impurity concentration N D [cm −3 ] of the type semiconductor substrate 2 has the relationship shown in the following formula (1).
Figure 2006222213
 Here, ε is a dielectric constant [F / cm] of the N-type semiconductor substrate 2, V is a potential difference [V] between the N-type semiconductor substrate 2 and the second P-type region 8, and q is an electron charge amount (= 1.602 × 10 −19 [C]). The distance d1 between the first P-type region 3 and the second P-type region 8 is 2 μm, the impurity concentration of the N-type semiconductor substrate 2 is 10 19 cm −3 , and the dielectric constant of the N-type semiconductor substrate 2 is ε = 1.05 × 10 −15 [F / cm] and the potential difference between the N-type semiconductor substrate 2 and the second P-type region 8 is V = 1.1 [V], the width W of the depletion layer Is set to 2 μm, which is the same as the distance d1, for example, each part may be designed as follows.

第１のＰ型領域の不純物濃度を、１０20ｃｍ-3、その深さｄ４を５μｍとし、第２のＰ型領域の不純物濃度を１０20ｃｍ-3、その深さｄ３を１０μｍとする。このとき、Ｎ型半導体基板２のうち第１のＰ型領域３と第２のＰ型領域８との間の領域では、第１のＰ型領域３および第２のＰ型領域８から拡散してきたＰ型不純物によってＮ型不純物濃度が相殺されるので、そのＮ型不純物濃度は１０14ｃｍ-3程度になる。このときに、空乏層の厚みは、距離ｄ１と同じ２μｍになる。 The impurity concentration of the first P-type region is 10 20 cm −3 , its depth d4 is 5 μm, the impurity concentration of the second P-type region is 10 20 cm −3 , and its depth d3 is 10 μm. At this time, in the region between the first P-type region 3 and the second P-type region 8 in the N-type semiconductor substrate 2, diffusion from the first P-type region 3 and the second P-type region 8 has occurred. Further, since the N-type impurity concentration is offset by the P-type impurity, the N-type impurity concentration is about 10 14 cm −3 . At this time, the thickness of the depletion layer is 2 μm, which is the same as the distance d1.

Ｎ型半導体基板２のうち第１のＰ型領域３と第２のＰ型領域８との間の領域におけるＮ型不純物濃度は、Ｎ型半導体基板２のＮ型不純物濃度と、第１のＰ型領域３と第２のＰ型領域８との間の距離と、第１のＰ型領域３と第２のＰ型領域８のＰ型不純物濃度とに依存する。言い換えれば、空乏層の幅Ｗは、Ｎ型半導体基板２そのもののＮ型不純物濃度と、第１のＰ型領域３と第２のＰ型領域８との間の距離と、第１のＰ型領域３および第２のＰ型領域８のＰ型不純物濃度とに依存する。   The N-type impurity concentration in the region between the first P-type region 3 and the second P-type region 8 in the N-type semiconductor substrate 2 is equal to the N-type impurity concentration of the N-type semiconductor substrate 2 and the first P-type region. It depends on the distance between the mold region 3 and the second P-type region 8 and the P-type impurity concentration of the first P-type region 3 and the second P-type region 8. In other words, the width W of the depletion layer depends on the N-type impurity concentration of the N-type semiconductor substrate 2 itself, the distance between the first P-type region 3 and the second P-type region 8, and the first P-type region. It depends on the P-type impurity concentration of the region 3 and the second P-type region 8.

距離ｄ１は、空乏層の幅Ｗ以下の幅であれば良いので、次式（２）を満たすように、各部を設計すればよい。

Figure 2006222213
Since the distance d1 may be a width equal to or smaller than the width W of the depletion layer, each part may be designed so as to satisfy the following expression (2).
Figure 2006222213

このような条件を満たすパラメータの一例を挙げると、Ｎ型半導体基板２のＮ型不純物濃度は１０18〜１０20ｃｍ-3、その厚みが１００〜４００μｍ、第１のＰ型領域３のＰ型不純物濃度が１０19〜１０21ｃｍ-3、その深さが１〜１０μｍ、第２のＰ型領域８のＰ型不純物濃度が１０19〜１０21ｃｍ-3、その深さｄ３が５〜２０μｍ、距離ｄ１が１〜５μｍである。 As an example of parameters satisfying such conditions, the N-type impurity concentration of the N-type semiconductor substrate 2 is 10 18 to 10 20 cm −3 , its thickness is 100 to 400 μm, and the P-type of the first P-type region 3 The impurity concentration is 10 19 to 10 21 cm −3 , the depth is 1 to 10 μm, the P-type impurity concentration of the second P-type region 8 is 10 19 to 10 21 cm −3 , and the depth d3 is 5 to 20 μm. The distance d1 is 1 to 5 μm.

このサージ保護用半導体素子１の使用態様の一例であるＬＥＤパッケージ１３およびその回路を、図５（ａ）および（ｂ）に示している。簡単に説明すると、サージ保護用半導体素子１は、正電圧の供給を受けるフレーム１１０ａ上に配置されて、ＬＥＤ１２０と共に透明樹脂部１１２で封止されている。第１の表面電極５は、ワイヤ１１１によってフレーム１１０ｂ（アース）に接続されている。ＬＥＤ１２０は、そのＰ側電極が第２の表面電極６に、また、Ｎ側電極が第１の表面電極５に接続されるよう配置される。   FIG. 5A and FIG. 5B show an LED package 13 and its circuit, which are examples of usage modes of the surge protection semiconductor element 1. In brief, the surge protection semiconductor element 1 is arranged on a frame 110 a that receives supply of a positive voltage, and is sealed together with the LED 120 by a transparent resin portion 112. The first surface electrode 5 is connected to the frame 110 b (earth) by a wire 111. The LED 120 is arranged such that its P-side electrode is connected to the second surface electrode 6 and its N-side electrode is connected to the first surface electrode 5.

ＬＥＤ１２０を発光させるための通常電圧が裏面電極７に印加されたときには、裏面電極７と第２の表面電極６とが導通して、ＬＥＤ１２０が発光する。Ｎ型半導体基板２と第１のＰ型領域３は、降伏電圧がこの通常電圧以上になるように設計されているので、通常電圧印加時には、裏面電極７と第１の表面電極５とは導通しない。   When a normal voltage for causing the LED 120 to emit light is applied to the back surface electrode 7, the back surface electrode 7 and the second front surface electrode 6 are brought into conduction, and the LED 120 emits light. Since the N-type semiconductor substrate 2 and the first P-type region 3 are designed so that the breakdown voltage is equal to or higher than the normal voltage, the back electrode 7 and the first front electrode 5 are electrically connected when the normal voltage is applied. do not do.

一方、裏面電極７にＥＳＤによる大電圧が印加された場合には、Ｎ型半導体基板２と第１のＰ型領域３の接合部Ｊ２３でツェナー降伏が発生して、第１の表面電極５からフレーム１０ｂにＥＳＤによる大電流（ＥＳＤ電流）を逃すことができる。   On the other hand, when a large voltage due to ESD is applied to the back electrode 7, Zener breakdown occurs at the junction J 23 between the N-type semiconductor substrate 2 and the first P-type region 3, and the first surface electrode 5 A large current (ESD current) due to ESD can be released to the frame 10b.

ここで、本実施形態に係るサージ保護用半導体素子１と、図４に示す従来のサージ保護用半導体素子１００とにおけるＥＳＤ電流の経路の違いを、図２（ａ）および（ｂ）を用いて説明する。図２（ａ）および（ｂ）において、太線矢印はＥＳＤ電流の流れを示している。   Here, the difference in the path of the ESD current between the surge protection semiconductor element 1 according to the present embodiment and the conventional surge protection semiconductor element 100 shown in FIG. 4 will be described with reference to FIGS. explain. In FIGS. 2 (a) and 2 (b), bold arrows indicate the flow of ESD current.

図２（ｂ）に示す従来のサージ保護用半導体素子１００では、Ｐ型領域１０３とＮ型半導体基板１０２との接合部Ｊ１２３のうち、表層部Ｓ１２３にもＥＳＤ電流が流れ入むことになっていた。これに対して図２（ａ）に示す本発明に係るサージ保護用半導体素子１では、第１のＰ型領域３の側面が空乏層ＤＬによって覆われているために、空乏層ＤＬが形成されていない領域からのみ第１のＰ型領域３にＥＳＤ電流が流れ込む。よって、表層部Ｓ２３にはＥＳＤ電流が流れ込むことがない。   In the conventional surge protection semiconductor element 100 shown in FIG. 2B, an ESD current flows into the surface layer portion S123 of the junction J123 between the P-type region 103 and the N-type semiconductor substrate 102. It was. On the other hand, in the surge protection semiconductor element 1 according to the present invention shown in FIG. 2A, since the side surface of the first P-type region 3 is covered with the depletion layer DL, the depletion layer DL is formed. The ESD current flows into the first P-type region 3 only from the region that is not. Therefore, the ESD current does not flow into the surface layer portion S23.

Ｎ型半導体基板２の表層部における融点は、表面欠陥の影響により、表面欠陥が存在していない領域の融点よりも低くなっている。そのため、表層部Ｓ２３のサージ耐量は、表層部Ｓ２３以外における接合部Ｊ２３のサージ耐量よりも低くなっている。本実施形態に係るサージ保護用半導体素子１は、サージ耐量が低い表層部Ｓ２３へのＥＳＤ電流の流入を防止することによって、サージ保護用半導体素子１全体のサージ耐量を向上させている。   The melting point of the surface layer portion of the N-type semiconductor substrate 2 is lower than the melting point of the region where no surface defects exist due to the influence of surface defects. Therefore, the surge resistance of the surface layer portion S23 is lower than the surge resistance of the joint J23 other than the surface layer portion S23. The surge protection semiconductor element 1 according to the present embodiment improves the surge tolerance of the entire surge protection semiconductor element 1 by preventing the ESD current from flowing into the surface layer portion S23 having a low surge tolerance.

次に、図３を用いて、サージ保護用半導体素子１の製造方法の一例を説明する。まず、Ｎ型半導体基板２の表面のうち、第２のＰ型領域８を形成する領域を露出するマスクを形成して、露出したＮ型半導体基板２表面からボロン等のＰ型不純物をドーピングおよび熱拡散させて、第２のＰ型領域８を形成する（図３（ａ））。また、第１のＰ型領域３を形成する領域を露出するマスクを形成して、露出したＮ型半導体基板２表面からボロン等のＰ型不純物をドーピングおよび熱拡散させて、第１のＰ型領域３を形成する（図３（ｂ））。なお、第２のＰ型領域８を第１のＰ型領域３よりも浅く形成する場合には、先に第１のＰ型領域３を形成すればよい。   Next, an example of a method for manufacturing the surge protection semiconductor element 1 will be described with reference to FIG. First, a mask that exposes a region for forming the second P-type region 8 in the surface of the N-type semiconductor substrate 2 is formed, and a P-type impurity such as boron is doped from the exposed N-type semiconductor substrate 2 surface. The second P-type region 8 is formed by thermal diffusion (FIG. 3A). Further, a mask that exposes a region where the first P-type region 3 is to be formed is formed, and P-type impurities such as boron are doped and thermally diffused from the exposed surface of the N-type semiconductor substrate 2 to form the first P-type. Region 3 is formed (FIG. 3B). Note that when the second P-type region 8 is formed shallower than the first P-type region 3, the first P-type region 3 may be formed first.

次に、１１００℃程度での熱酸化と化学気相成長法（ＣＶＤ:Chemical Vapor Deposition）を用いて、Ｎ型半導体基板２上に絶縁膜４を形成する。そして、フォトリソグラフィによって絶縁膜４を選択的にエッチングして、Ｎ型半導体基板２と第１のＰ型領域３との表面の一部を露出するコンタクト窓９を開口する（図３（ｃ））。なお、絶縁膜４は、図１に示すようにＮ型半導体基板２表面のうち周辺部を露出するように形成してもよいし、周辺部も覆うようにしておいてもよい。図３（ｃ）に示すように、絶縁膜４をＮ型半導体基板２の周辺部を除いて形成しておけば、ウエハからチップに切断する際に絶縁膜４に掛かるストレスを低減することができる。   Next, the insulating film 4 is formed on the N-type semiconductor substrate 2 using thermal oxidation at about 1100 ° C. and chemical vapor deposition (CVD). Then, the insulating film 4 is selectively etched by photolithography to open a contact window 9 exposing a part of the surfaces of the N-type semiconductor substrate 2 and the first P-type region 3 (FIG. 3C). ). The insulating film 4 may be formed so as to expose the peripheral portion of the surface of the N-type semiconductor substrate 2 as shown in FIG. 1 or may cover the peripheral portion. As shown in FIG. 3C, if the insulating film 4 is formed excluding the peripheral portion of the N-type semiconductor substrate 2, stress applied to the insulating film 4 when the wafer is cut into chips can be reduced. it can.

次に、コンタクト窓９をアルミニウムなどの金属材料で埋めることによって、Ｎ型半導体基板２および第１のＰ型領域３と接する第１の表面電極５および第２の表面電極６を形成する。最後に、チタン、金、銀、ニッケル、又はこれらを含む金属を蒸着して、多層または単層の裏面電極７を形成する。   Next, the first surface electrode 5 and the second surface electrode 6 that are in contact with the N-type semiconductor substrate 2 and the first P-type region 3 are formed by filling the contact window 9 with a metal material such as aluminum. Finally, titanium, gold, silver, nickel, or a metal containing these is vapor-deposited to form a multilayer or single-layer back electrode 7.

本発明に係るサージ保護用半導体素子１は、第１のＰ型領域３側面のうち、少なくとも表面欠陥による影響を被る部分（表層部Ｓ２３）が空乏層ＤＬによって覆われるように設計した、浮遊状態の第２のＰ型領域８を備えている。このような第２のＰ型領域８を備えているために、表層部Ｓ２３にはサージによる大電流が流れ込むことがない。よって、本発明に係るサージ保護用半導体素子１は、高ＥＳＤ耐量のフリップチップ型ツェナーダイオードとなる。よって、本発明に係るサージ保護用半導体素子１を用いれば、ＬＥＤ等保護すべき素子の保護効果を向上させることができる。   The semiconductor element 1 for surge protection according to the present invention is a floating state designed so that at least a portion (surface layer portion S23) affected by a surface defect is covered with a depletion layer DL among the side surfaces of the first P-type region 3 The second P-type region 8 is provided. Since such a second P-type region 8 is provided, a large current due to a surge does not flow into the surface layer portion S23. Therefore, the semiconductor element 1 for surge protection according to the present invention is a flip chip type Zener diode having a high ESD resistance. Therefore, if the semiconductor element 1 for surge protection according to the present invention is used, the protection effect of an element to be protected such as an LED can be improved.

なお、本発明に係るサージ保護用半導体素子１において、第１の表面電極５からサージが侵入した場合には、第１の表面電極５と裏面電極７との間で順方向に電流が流れ、裏面電極７から外部にサージを逃すことができる。本発明に係るサージ保護用半導体素子１では、空乏層ＤＬによって電流経路が制限されるために、第１の表面電極５と第２の表面電極６とを結ぶような電流経路はできにくい。よって、本発明に係るサージ保護用半導体素子１は、裏面電極７からサージが侵入する場合だけでなく、第１の表面電極５からサージが侵入する場合にも、第２の表面電極６上に接続した保護対象物を保護することができる。   In the surge protection semiconductor element 1 according to the present invention, when a surge enters from the first surface electrode 5, a current flows in the forward direction between the first surface electrode 5 and the back electrode 7, A surge can escape from the back electrode 7 to the outside. In the semiconductor element 1 for surge protection according to the present invention, since the current path is limited by the depletion layer DL, it is difficult to form a current path that connects the first surface electrode 5 and the second surface electrode 6. Therefore, the semiconductor element 1 for surge protection according to the present invention is not only on the second surface electrode 6 not only when the surge enters from the back electrode 7 but also when the surge enters the first surface electrode 5. The connected protection object can be protected.

なお、上記実施形態では、Ｎ型半導体基板２に、Ｐ型不純物領域（第１のＰ型領域３および第２のＰ型領域８）を設けた場合を説明したが、導電型を逆にした場合にも本発明は有効である。つまり、Ｎ型半導体基板２の代わりにＰ型半導体基板を用いて、第１のＰ型領域３および第２のＰ型領域８の代わりにＮ型領域を設けるようにしてもよい。   In the above embodiment, the case where the P-type impurity regions (the first P-type region 3 and the second P-type region 8) are provided in the N-type semiconductor substrate 2 has been described. However, the conductivity type is reversed. Even in this case, the present invention is effective. That is, a P-type semiconductor substrate may be used instead of the N-type semiconductor substrate 2, and an N-type region may be provided instead of the first P-type region 3 and the second P-type region 8.

本発明に係るサージ保護用半導体素子は、ＬＥＤ等を静電気等のサージから保護するサージ保護用半導体素子として有用である。   The semiconductor device for surge protection according to the present invention is useful as a semiconductor device for surge protection that protects LEDs and the like from surges such as static electricity.

（ａ）は、本発明の実施形態に係るサージ保護用半導体素子の断面図、（ｂ）は、Ｎ型半導体基板の平面図(A) is sectional drawing of the semiconductor element for surge protection which concerns on embodiment of this invention, (b) is a top view of an N-type semiconductor substrate サージ侵入時の電流経路の違いを説明する図Diagram explaining the difference in current path during surge intrusion 図１のサージ保護用半導体素子の製造方法を説明する図The figure explaining the manufacturing method of the semiconductor element for surge protection of FIG. 従来のサージ保護用半導体素子の断面図Sectional view of a conventional semiconductor device for surge protection （ａ）は、サージ保護用半導体素子を封入したＬＥＤパッケージの概略図、（ｂ）は（ａ）の回路図(A) is the schematic of the LED package which enclosed the semiconductor element for surge protection, (b) is the circuit diagram of (a).

符号の説明Explanation of symbols

１ サージ保護用半導体素子
２ Ｎ型半導体基板
３ 第１のＰ型領域
４ 絶縁膜
５ 第１の表面電極
６ 第２の表面電極
７ 裏面電極
８ 第２のＰ型領域
１００ サージ保護用半導体素子
１０２ Ｎ型半導体基板
１０３ Ｐ型領域
１０４ 絶縁膜
１０５ 第１の表面電極
１０６ 第２の表面電極
１０７ 裏面電極
１１０ａ、１１０ｂ フレーム
１１１ ワイヤ
１２０ ＬＥＤ DESCRIPTION OF SYMBOLS 1 Surge protection semiconductor element 2 N type semiconductor substrate 3 1st P type area | region 4 Insulating film 5 1st surface electrode 6 2nd surface electrode 7 Back surface electrode 8 2nd P type area | region 100 Surge protection semiconductor element 102 N-type semiconductor substrate 103 P-type region 104 Insulating film 105 First surface electrode 106 Second surface electrode 107 Back electrode 110a, 110b Frame 111 Wire 120 LED

Claims (4)

第１導電型の半導体基板と、
前記半導体基板の表面から内部に形成した第１の第２導電型領域と、
前記第１の第２導電型領域から所定の距離だけ離れた位置で当該第１の第２導電型領域を周回する第２の第２導電型領域と、
前記第１の第２導電型領域の表面と前記第２の第２導電型領域よりも外側の前記半導体基板表面の一部とを露出して、前記半導体基板表面を覆う絶縁膜と、
前記絶縁膜から露出した前記第１の第２導電型領域に設けた第１の表面電極と、
前記絶縁膜から露出した前記半導体基板表面に設けた第２の表面電極と、
前記半導体基板の裏面に設けた裏面電極とを備え、
前記第２の第２導電型領域と前記半導体基板との接合部で発生した空乏層が、前記第１の第２導電型領域と前記半導体基板との接合部のうち、少なくとも表面欠陥が存在する領域を覆うことを特徴とする、サージ保護用半導体素子。 A first conductivity type semiconductor substrate;
A first second conductivity type region formed inside from the surface of the semiconductor substrate;
A second second conductivity type region that circulates around the first second conductivity type region at a position away from the first second conductivity type region by a predetermined distance;
An insulating film that covers the surface of the semiconductor substrate by exposing a surface of the first second conductivity type region and a part of the surface of the semiconductor substrate outside the second second conductivity type region;
A first surface electrode provided in the first second conductivity type region exposed from the insulating film;
A second surface electrode provided on the surface of the semiconductor substrate exposed from the insulating film;
A back electrode provided on the back surface of the semiconductor substrate,
The depletion layer generated at the junction between the second second conductivity type region and the semiconductor substrate has at least surface defects in the junction between the first second conductivity type region and the semiconductor substrate. A semiconductor element for surge protection characterized by covering an area. 前記第１の第２導電型領域と前記第２の第２導電型領域との間の距離ｄ１は、前記半導体基板の誘電率をε、半導体基板と第２の第２導電型半導体領域との電位差をＶ、電子電荷量をｑ、前記第１の第２導電型領域と前記第２の第２導電型領域との間の領域における第１導電型不純物濃度をＮDとするときに、
Figure 2006222213
 を満たすことを特徴とする、請求項１に記載のサージ保護用半導体素子。 The distance d1 between the first second conductivity type region and the second second conductivity type region is expressed as follows. The dielectric constant of the semiconductor substrate is ε, and the distance between the semiconductor substrate and the second second conductivity type semiconductor region is When the potential difference is V, the electron charge amount is q, and the first conductivity type impurity concentration in the region between the first second conductivity type region and the second second conductivity type region is N D ,
Figure 2006222213
 The semiconductor element for surge protection according to claim 1, wherein: 前記第１の第２導電型領域の平面形状は円形状であり、
前記第２の第２導電型領域の平面形状は、前記第１の第２導電型領域と中心を同じにする環状であることを特徴とする、請求項１に記載のサージ保護用半導体素子。 The planar shape of the first second conductivity type region is circular,
2. The surge protection semiconductor device according to claim 1, wherein a planar shape of the second second conductivity type region is an annular shape having the same center as that of the first second conductivity type region. 第１導電型の半導体基板の表面から内部に、第１の第２導電型領域を形成する工程と、
前記第１の前記第２導電型領域から所定の距離だけ離れた位置で前記第１の第２導電型領域を周回する第２の第２導電型領域を形成する工程と、
前記第１の第２導電型領域の表面と前記第２の第２導電型領域よりも外側の前記半導体基板表面の一部とを露出して、前記半導体基板を覆う絶縁膜を形成する工程と、
前記絶縁膜から露出した前記第１の第２導電型領域と前記半導体基板表面とに、第１および第２の表面電極を形成する工程と、
前記半導体基板の裏面に裏面電極を形成する工程とを備え、
前記第２の第２導電型領域と前記半導体基板との接合部で発生した空乏層が、前記第１の第２導電型領域と前記半導体基板との接合部のうち、少なくとも表面欠陥が存在する領域を覆うように、前記第２の第２導電型領域を形成することを特徴とする、サージ保護用半導体素子の製造方法。 Forming a first second conductivity type region from the surface of the first conductivity type semiconductor substrate to the inside;
Forming a second second conductivity type region that goes around the first second conductivity type region at a position away from the first second conductivity type region by a predetermined distance;
Exposing the surface of the first second conductivity type region and a portion of the surface of the semiconductor substrate outside the second second conductivity type region to form an insulating film covering the semiconductor substrate; ,
Forming first and second surface electrodes on the first second conductivity type region exposed from the insulating film and the surface of the semiconductor substrate;
Forming a back electrode on the back surface of the semiconductor substrate,
The depletion layer generated at the junction between the second second conductivity type region and the semiconductor substrate has at least surface defects in the junction between the first second conductivity type region and the semiconductor substrate. A method for manufacturing a semiconductor device for surge protection, wherein the second second conductivity type region is formed so as to cover the region.
JP2005033103A 2005-02-09 2005-02-09 Surge protecting semiconductor device and its manufacturing method Pending JP2006222213A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527618A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Planar diode
JPS5780765A (en) * 1980-11-07 1982-05-20 Toshiba Corp Semiconductor device
JPS58114456A (en) * 1981-12-26 1983-07-07 Fuji Electric Co Ltd Transistor incorporating constant-voltage diode
JPS6136979A (en) * 1984-07-30 1986-02-21 Nec Corp Constant-voltage diode
JPH11251644A (en) * 1998-02-27 1999-09-17 Matsushita Electron Corp Semiconductor light emitting device
JP2000012913A (en) * 1998-06-19 2000-01-14 Matsushita Electron Corp Electrostatic protective diode used for semiconductor light-emitting device and manufacture thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527618A (en) * 1978-08-17 1980-02-27 Mitsubishi Electric Corp Planar diode
JPS5780765A (en) * 1980-11-07 1982-05-20 Toshiba Corp Semiconductor device
JPS58114456A (en) * 1981-12-26 1983-07-07 Fuji Electric Co Ltd Transistor incorporating constant-voltage diode
JPS6136979A (en) * 1984-07-30 1986-02-21 Nec Corp Constant-voltage diode
JPH11251644A (en) * 1998-02-27 1999-09-17 Matsushita Electron Corp Semiconductor light emitting device
JP2000012913A (en) * 1998-06-19 2000-01-14 Matsushita Electron Corp Electrostatic protective diode used for semiconductor light-emitting device and manufacture thereof

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