JP2006222102A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device having a high amplification factor, and to provide its manufacturing method. <P>SOLUTION: A bipolar transistor of polysilicon emitter structure has a polysilicon region 8 doped with impurities, and an emitter region 30 having a thin film layer 30 containing carbon at an interface with the polysilicon region 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor, and more particularly to a semiconductor device having a polycrystalline silicon emitter structure and a method for manufacturing the semiconductor device.

  A bipolar transistor, which is one of the components of a semiconductor device, can easily coexist with resistors, capacitors, and the like, and can form a large number of circuit elements on a semiconductor substrate to perform required circuit operations and functions. Widely used because of its properties.

  Bipolar transistors have various required electrical characteristics, and one of the important characteristics is the current amplification factor. When the emitter injection efficiency is improved, the characteristics of the current amplification factor can be improved. Therefore, various techniques have been proposed as techniques for obtaining a semiconductor device having a high emitter injection efficiency.

  Conventionally, as a principle for improving the current amplification factor of a bipolar transistor, a method of providing an energy gap at the junction between the emitter and the base and blocking the flow of minority carriers injected from the base to the emitter has been widely used.

  As a specific method, a bipolar transistor having a MIS (metal / insulating film / semiconductor) structure in which an insulating film is formed as a thin film through which a tunnel current can flow, for example, a thin film through which a tunnel current flows can be used. A hetero bipolar transistor using a microcrystal (μC), which is a high quality heteroemitter material, as an emitter is known.

  In the case of a bipolar transistor having a thin film through which a tunnel current flows as an emitter, holes from the base are blocked by the thin film due to the difference in tunneling probability between electrons and holes in the thin film, and the base current is reduced. In the case of a heterobipolar transistor using a microcrystal, majority carriers are injected into the base layer while suppressing the reverse injection of minority carriers from the base to the emitter due to the band gap difference between the emitter and the base. As a result, the base current is reduced.

  In general, for example, the following techniques are known as techniques for improving the reliability of a semiconductor device.

  Japanese Patent Application Laid-Open No. 2002-270819 discloses a semiconductor device including a heterojunction bipolar transistor having a high-frequency performance improved without separating a high-concentration region between an emitter and an external base at the shortest distance and increasing a leakage current between the emitter and the base. (Patent Document 1).

  In JP 2003-086598, the distance between the base electrode portion and the emitter electrode portion is increased, the area where the base electrode portion and the emitter electrode portion face each other is reduced, and the existing capacity between the base and the emitter is reduced. A bipolar transistor is disclosed (Patent Document 2).

  Japanese Patent Application Laid-Open No. 2003-243407 discloses a bipolar transistor in which the base lead layer of the base layer is thickly stacked, the resistance of the base lead portion is reduced, and the base resistance of the entire base is reduced (Patent Document 3).

Japanese Patent Application Laid-Open No. 2004-221195 discloses a bipolar transistor containing carbon that prevents diffusion of a dopant in an emitter layer and germanium that compensates for a change in lattice constant due to carbon doping and lattice-matches the emitter layer to a semiconductor substrate material. (Patent Document 4).
JP 2002-270819 A JP 2003-086598 A Japanese Patent Laid-Open No. 2003-243407 JP 2004-221195 A

  In the conventional MIS structure bipolar transistor, the recombination current in the oxide film becomes dominant, particularly in a minute current region, and the base current increases, so the current gain on the low current side decreases, and in extreme cases, The size is 1 or less. Further, in such a structure, the metal and the insulating film easily react and lack reliability. Furthermore, since the insulating film has a considerable thickness, the series resistance (emitter resistance) increases. In addition, since the tunneling probability of holes and electrons is determined by the thickness of the oxide film, the thickness of the oxide film is sensitively reflected in the current amplification factor, resulting in variations in the characteristics of individual bipolar transistors. Note that the series resistance also changes. It is difficult to produce all oxide films stably with a margin of error. Therefore, there is a demand for a reliable bipolar transistor that does not decrease the current amplification factor even under a low current and can be easily manufactured.

  On the other hand, in conventional heterobipolar transistors using microcrystals, the emitter-base junction, that is, the interface between the emitter and base using microcrystal silicon, is unstable and easily fluctuates with respect to heat treatment, and is stable. hard. This is based on the instability of the microcrystal itself and the instability at the interface with single crystal silicon. Moreover, since a normal microcrystal contains a large amount of hydrogen, it is caused by promoting crystal instability. Furthermore, those using microcrystals are liable to cause characteristic deterioration not only during the manufacturing process but also during operation. For this reason, a highly reliable bipolar transistor that does not cause characteristic deterioration is desired.

  [Means for Solving the Problems] will be described below using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added in parentheses in order to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  A semiconductor device (10) according to the present invention includes a base region (4, 5) formed on a collector region (3), an emitter region (6) formed on the base region (4, 5), and an emitter. A polycrystalline silicon region (8) formed on the region (6) and doped with impurities, and a carbon-containing thin film layer (30) at the interface between the polycrystalline silicon region (8) and the emitter region (6). Have

  On the semiconductor substrate (1), a first conductivity type buried layer (2), a first conductivity type epitaxial collector region (3), a second conductivity type intrinsic base region (4), and an emitter region ( 6) and the polycrystalline silicon region (8) are arranged in order. Further, it has an external base region (5) adjacent to the intrinsic base region (4) and a sub-collector region (7) adjacent to the epitaxial collector region (3), and the intrinsic base region (4) is an external base region. (5) is connected to the base electrode (201), and the epitaxial collector region (3) is connected to the collector electrode (202) via the subcollector region (7). The carbon-containing thin film layer (3) is thin to the extent that it does not have bulk properties, and the interface state is generated by the synergistic action of impurities introduced into the polycrystalline silicon region (8) and the carbon compound contained in the carbon-containing thin film layer (3) The base current is suppressed by using a potential barrier generated by ionizing segregated impurities and the current amplification factor is increased.

  The manufacturing method includes a step of forming a buried layer (2) on a substrate (1), a step of forming a collector region (3) by epitaxial growth on the buried layer (2), and a collector region by ion implantation. (3) a step of forming a subcollector region (7), a step of forming an insulating film (102) for element isolation on the collector region (3), and an active region of the collector region (3) Forming an outer base region (5) and an intrinsic base region (4); and forming an insulating film (101) on the intrinsic base region (4), the outer base region (5) and the subcollector region (7). Opening an emitter contact in the insulating film (101), forming a carbon-containing thin film layer (30) on the opening surface of the emitter contact; A step of depositing a polycrystalline silicon region (8) so as to cover a part of the edge film (101), ion implantation of impurities into the polycrystalline silicon region (8) on the emitter contact, and diffusion of the impurities by heat treatment The step of forming the emitter region (6) in the intrinsic base (4) around the opening surface of the emitter contact, the insulating film (103) for electrode separation is deposited, the insulating film is annealed, and then the base contact and emitter Forming contacts and collector contacts and forming electrodes.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the current amplification factor of the bipolar transistor can be easily increased.

  In addition, the reliability of the bipolar transistor is improved.

  Furthermore, the ease and stability of manufacturing the bipolar transistor are improved.

  A semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the accompanying drawings.

(Constitution)
FIG. 1 is a schematic cross-sectional view showing the structure of a bipolar transistor 10 according to a first embodiment of the present invention.

  Referring to FIG. 1, a buried layer 2 is provided on a silicon substrate 1, and a collector layer 3 is provided thereon. The collector layer 3 includes a subcollector region 7 that connects the collector electrode 202 and the buried layer 2. An intrinsic base region 4 and an external base region 5 are provided on the collector layer 3. Intrinsic base region 4 is connected to base electrode 201 through external base region 5. An emitter region 6 is provided on the intrinsic base layer 4. The emitter region 6 is connected to the emitter electrode 200 through the upper polycrystalline silicon region 8. The emitter region 6 includes a carbon-containing thin film layer 30 at the interface with the polycrystalline silicon region 8. The insulating film 101 is provided on the intrinsic base region 4, the external base region 5, and the emitter region 6, and separates the electrodes and the elements. The insulating film 102 is provided on the collector layer 3, the intrinsic base layer 4, and the external base layer 5, and separates the electrodes and the elements. The insulating film 103 is provided on the insulating films 101 and 102 and separates the electrodes.

The silicon substrate 1 is n-type doped with impurities such as phosphorus, arsenic, and antimony, or p-type doped with impurities such as boron, aluminum, and gallium. In this embodiment, a p-type silicon substrate is used as an example. The buried layer 2 is, for example, an n ⁺ region having an impurity concentration of 10 ¹⁶ to 10 ²⁰ [cm ⁻³ ]. The collector layer 3 has a function as a part of the collector region and is an n-type region having a low impurity concentration, for example, about 10 ¹³ to 10 ¹⁷ [cm ⁻³ ] formed by an epitaxial technique or the like. The intrinsic base region 4 has a function as a base region and is a p-type region, for example, a p-type region having an impurity concentration of 10 ¹⁵ to 10 ²⁰ [cm ⁻³ ]. The external base region 5 is a p ⁺ region having an impurity concentration of 10 ¹⁷ to 10 ²⁰ [cm ⁻³ ], for example, in order to lower the base resistance. The emitter region 6 has a function as an emitter, and is, for example, an n ⁺ type region having an impurity concentration of 10 ¹⁹ to 10 ²¹ [cm ⁻³ ]. The subcollector region 7 is an n ⁺ region, and the collector resistance is lowered by connecting the collector electrode 202 and the buried layer 2. The polycrystalline silicon region 8 is a polycrystalline layer doped with high-concentration impurities, which is a semiconductor material layer, and blocks minority carriers injected from the base. The carbon-containing thin film layer 30 is an extremely thin adsorption layer so that the bulk property of the carbon compound does not appear. Examples of carbon compounds include DEP (diethyl phthalate), DBP (dibutyl phthalate), DOP (dioctyl phthalate), BHT (2,6-di-tert-butyl-4-methylphenol), menthol, diphenyl, butyric acid, etc. A carbon compound having a relatively good adsorptivity and thermally strong is used. These carbon compounds can be used not only alone but also in a mixture or combination. The emitter electrode 200, the base electrode 201, and the collector electrode 202 are each formed of metal, silicide, or the like.

(Production method)
With reference to FIG. 2, a method of manufacturing a bipolar transistor according to the present invention will be described.

(1) A buried layer 2 having an impurity concentration of 10 ¹⁷ to 10 ¹⁹ [cm ⁻³ ] is formed on a substrate of a predetermined conductivity type (p-type or n-type) by ion implantation or impurity diffusion of As, Sb, P, or the like. Formed (see FIG. 2A).
(2) Next, the collector layer 3 having an impurity concentration of preferably 10 ¹⁴ to 10 ¹⁷ [cm ⁻³ ] is formed by epitaxial growth or the like. Thereafter, the subcollector region 7 having an impurity concentration of preferably 10 ¹⁷ to 10 ²⁰ [cm ⁻³ ] is formed by ion implantation or the like (see FIG. 2B).
(3) An insulating film 102 for element isolation is formed by a selective oxidation method, a CVD method, or the like (see FIG. 2C).
(4) The external base region 5 and the intrinsic base region 4 are formed in the active region of the collector layer 3 by ion implantation or impurity diffusion (see FIG. 2D).
(5) An insulating film 101 is formed on the intrinsic base region 4, the external base region, and the subcollector region 7, and an emitter contact is opened by photoetching. Next, the opening surface of the emitter contact is immersed in a solvent containing a diluted carbon compound, and the carbon-containing thin film layer 30 is adsorbed and formed on the opening surface. At this time, a material in which a carbon compound is soluble, such as pure water, ethanol, or ether, is used as the solvent. The carbon-containing thin film layer 30 may be formed by exposing the opening surface in an atmosphere containing a carbon compound. As the atmosphere, for example, clean air, nitrogen gas, carbon dioxide gas or the like is used. Examples of carbon compounds formed as the carbon-containing thin film layer 30 include DEP (diethyl phthalate), DBP (dibutyl phthalate), DOP (dioctyl phthalate), BHT (2,6-di-tert-butyl-4-methylphenol), A carbon compound such as menthol, diphenyl, butyric acid, etc., which has a relatively good adsorptivity to silicon and is thermally strong. These carbon compounds can be used alone or in combination or in combination (see FIG. 2E).
(6) A polycrystalline silicon region 8 is deposited by LPCVD. Next, n-type impurities such as As, Sb, and P are ion-implanted into the polycrystalline silicon region 8 on the emitter contact at a high concentration (5 × 10 ¹⁹ [cm ⁻³ ] or more). Furthermore, it is heat-treated at 900 to 950 ° C. to activate and diffuse impurities, thereby forming the emitter region 6. At this time, an n ⁺ diffusion layer having an impurity concentration of 10 ²⁰ to 10 ²¹ [cm ⁻³ ] is preferably formed in the emitter region 6. Thereafter, the polycrystalline silicon 8 is photoetched to leave an emitter electrode portion (see FIG. 2F).
(7) After the insulating film 103 is deposited and annealed, the base contact, the emitter contact, and the collector contact are opened by photoetching (see FIG. 2G).
(8) Al—Si serving as an electrode is sputtered on the surface, and an emitter electrode 200, a base electrode 201, and a contact electrode 202 are formed by metal etching (see FIG. 2H). Next, each electrode is alloyed to form a passivation film (not shown).
As described above, a bipolar transistor according to the present invention is produced.

(Operation and operation principle)
The operation and operation principle of the bipolar transistor according to the present invention will be described with reference to FIGS.

The polycrystalline silicon region 8, the carbon-containing thin film layer 30, and the emitter region 6 will be described with reference to FIG.
Generally, high density lattice defects such as dangling bonds exist near the polycrystalline silicon / silicon interface. Lattice defects existing at this interface serve as trapping centers for free carriers as deep acceptor or donor levels. Referring to FIG. 3, an approximate band diagram near the vicinity of the polycrystalline silicon / silicon interface is shown. At this interface, the interface state is terminated by majority carriers and has a high density of trapped negative charges. For this reason, referring to FIG. 2A, a depletion layer region is generated in the vicinity of the polycrystalline silicon / silicon interface, and the potential changes to generate a potential barrier ΦS serving as a barrier against carriers.

  In addition to dangling bonds, many segregation sites of impurities exist at the interface of the polycrystalline silicon / silicon. Referring to FIG. 3B, when a polycrystalline silicon region is doped with a low concentration n-type impurity (for example, arsenic), the trapping site of the dangling bond reduces the potential barrier height Φs due to segregation of the impurity. To do. Referring to FIG. 3C, the polycrystalline silicon region 8 according to the present invention is further doped with impurities. For this reason, most of the arsenic in the polycrystalline silicon region 8 is affected by the carbon-containing thin film layer 30 at the interface, and segregates at dangling bonds and other segregation sites at the polycrystalline silicon / silicon interface. The levels existing at the polycrystalline silicon / silicon interface are terminated, and a part of arsenic is easily ionized at the segregation site to generate the potential barrier height Φs ′. Therefore, impurities begin to segregate at other segregation sites present at the interface, and positive charges are generated at the interface.

  In the potential state shown in the band diagram of FIG. 3C, the height Φs ′ of the potential barrier acts as a barrier for minority carriers (holes) injected from the base region into the emitter region, thereby reducing the base current. Let As a result, the current amplification factor is improved.

The models that explain the phenomenon in which h _FE increases due to a decrease in base current can be broadly divided into (1) an oxide film tunneling model, (2) a low mobility model, and (3) a thermal electron emission model from a segregation potential barrier. is there. Pingxi Ma et al. Have proposed an analytical model that considers these three carrier transport mechanisms with respect to the carrier transport phenomenon of a transistor having an n-type polycrystalline silicon emitter structure.

According to this analytical model, when the native oxide film formed at the n-type polycrystalline silicon / silicon interface is extremely thin (5 mm or less), the current amplification factor h _FE is the height of the potential barrier accompanying segregation of arsenic and the like. It is known that the change greatly depends on Φs and the interface state density Nt, and it has been found that the bipolar transistor according to the present invention also changes depending on the height Φs of the potential barrier and the interface state density Nt.

Referring to FIG. 4, the band structure in the AA 'line of the bipolar transistor according to the present invention shown in FIG. 1 is shown. Between A and B, a polycrystalline silicon region 8, B is an n-type polycrystalline silicon / silicon interface (near the carbon-containing thin film layer 30), and C is an emitter / base interface. The height Φs ′ of the potential barrier at the N-type polycrystalline silicon / silicon interface is 0.18V, which is considerably larger than the barrier Φs of 0.15V due to the band gap reduction effect. Accordingly, the current amplification factor h _FE of the bipolar transistor according to the present invention varies greatly due to the influence of the potential barrier height Φs.

Next, in the comparison between the levels regarding the presence or absence of the carbon-containing thin film layer 30 at the n-type polycrystalline silicon / silicon interface, the potential barrier height Φs of the bipolar transistor formed with the carbon-containing thin film layer 30 according to the present invention is the same manufacturing. It is 10 mV higher than the bipolar transistor that does not form the carbon-containing thin film layer 30 formed in the process (except for the process of creating the carbon-containing thin film layer 30), and according to the analysis result of the model, the interface state density Nt is It has decreased to 1/500. Referring to FIG. 5, a Gummel plot showing current-voltage characteristics is shown. The carbon compound addition concentration to the carbon-containing thin film layer according to the present invention is 250 ppb. In addition, this carbon compound concentration shows the concentration in pure water, and is a value of TOC (Total organic carbon: total organic carbon) for convenience. The base current IB and the collector current IC according to the present invention are indicated by solid lines, and the base current IB and the collector current IC of the bipolar transistor without the carbon-containing thin film layer 30 are indicated by broken lines. Further, the current / current amplification factor hFE according to the present invention is indicated by a one-dot chain line, and the current amplification factor hFE of a bipolar transistor without the carbon-containing thin film layer 30 is indicated by a solid line. Referring to FIG. 5, the collector current IC in the range of 1 × 10 ⁻¹³ to 1 × 10 ⁻¹ (A) shows exactly the same characteristics, but only a difference is observed in the base current. The current amplification factor hFE is increased by about 1.4 times compared to the case where the carbon-containing thin film layer 30 is not provided. Therefore, the fact that the carbon-containing thin film layer 30 formed at the n-type polycrystalline silicon / silicon interface does not affect the collector current means that there is no barrier action for transport of electrons whose interface is majority carriers. This indicates that there is no potential barrier in the conduction band. This indicates that a barrier action is brought about with respect to transport of holes which are minority carriers from the base region to the emitter region, that is, a potential barrier is formed in the valence band.

  As described above, in the bipolar transistor having the carbon-containing thin film layer 30 according to the present invention, arsenic segregated at the n-type polycrystalline silicon / silicon interface and the carbon compound constituting the carbon-containing thin film layer 30 are formed of silicon dangling bonds. This is considered to be caused by the fact that the interface state in the forbidden band is remarkably lowered due to bonding, and at the same time, the ionization of impurities forms a bend in the energy band of the valence band of the interface, generating a potential barrier.

Referring to FIG. 6, the relationship between the current amplification factor h _FE of the concentration and the bipolar transistor of the carbon compound for forming the carbon-containing thin film layer 30 to the n-type polycrystalline silicon / silicon interface is shown. The carbon compound concentration shown in FIG. 6 indicates the concentration in pure water, and is a TOC value for convenience. Here, the TOC concentration range is 30 to 280 ppb. The immersion time in the pure water containing a carbon compound is 10 minutes at room temperature. As shown in FIG. 6, the current amplification factor h _FE has a positive correlation with the TOC concentration and shows a linear change with little variation. This indicates that the current gain _hFE is excellent in controllability, and the carbon-containing thin film layer 30 can be easily formed without using any special equipment, so that mass productivity is very high.

  In a bipolar transistor having a MIS (metal / insulating film / semiconductor) structure in which an insulating film as a thin film capable of passing a tunnel current is formed, when the polycrystalline layer 8 is deposited on the oxide film and heat-treated, the oxide film is partially To be locally grown epitaxially. This is because thermal distortion occurs at the interface due to the difference in crystallinity between the polycrystalline layer and the insulating film, and oxygen as an impurity exists in a metastable state to alleviate this. This is because crystal grains in the crystal layer grow, oxygen state changes, and Si—O bond recombination occurs. In a remarkable case, the oxide film has a ball shape, and as a result, the polycrystalline layer is solid-phase epitaxially grown at the contact surface between the polycrystalline layer and the single crystal of the substrate. In the case of such a structure, the interface between the single crystal and the polycrystal is not flat, and the base current value related to the characteristics of the bipolar transistor is not constant, which causes variations in product characteristics. In the present invention, since a carbon-containing thin film layer 30 made of a carbon compound adsorption layer is formed on the single crystal emitter region 6 and the polycrystalline silicon region 8 is formed on the thin film, such an interface is flat. This eliminates the problem that the base current value becomes unstable.

Further, since no barrier against electrons is formed, generation of series resistance (emitter resistance) due to the insulating film can be prevented. Furthermore, since the current amplification factor _hFE can be arbitrarily changed with good controllability by changing the concentration of the carbon compound, the present invention requires an advanced insulating film forming technique that requires high precision of the unit. In addition, since the polycrystalline silicon region 8 can be deposited by a generally used low-pressure CVD apparatus, extremely high mass productivity can be obtained.

  On the other hand, since the polycrystalline silicon region 8 is deposited at about 550 to 650 ° C. and hardly contains hydrogen, it is like a heterobipolar transistor using a microcrystal (μC) deposited at about 100 to 300 ° C. as an emitter. In addition, the characteristics are not easily changed by heat treatment at 400 to 600 ° C. In the case of polycrystalline silicon used in the present invention, it can withstand up to about 950 ° C., and an extremely stable bipolar transistor can be obtained.

  As described above, the bipolar transistor according to the present invention forms the base region by forming the carbon-containing thin film layer 30 between the emitter region 6 and the polycrystalline silicon region 8 and bending the potential barrier of the valence band at the interface. It acts as a barrier against holes injected from the base, can reduce the base current, and can easily increase the current amplification factor. In addition, the current amplification factor according to the present invention is directly proportional to the carbon compound concentration of the carbon-containing thin film layer 30 and is extremely excellent in mass productivity.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. .

FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a structure according to a method for manufacturing a semiconductor device in an embodiment of the present invention. FIG. 2B is a cross-sectional view showing the structure according to the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 2C is a cross-sectional view showing a structure according to the method for manufacturing a semiconductor device in the embodiment of the present invention. FIG. 2D is a cross-sectional view showing the structure relating to the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 2E is a cross-sectional view showing the structure according to the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 2F is a cross-sectional view showing the structure relating to the method for manufacturing the semiconductor device in the embodiment of the present invention. FIG. 2G is a cross-sectional view showing a structure according to the method for manufacturing a semiconductor device in the embodiment of the present invention. FIG. 2H is a cross-sectional view showing a structure according to the method for manufacturing a semiconductor device in the embodiment of the present invention. FIG. 3 is a conceptual diagram of energy levels of the semiconductor device according to the embodiment of the present invention. FIG. 4 is a conceptual diagram of energy levels of the semiconductor device according to the embodiment of the present invention. FIG. 5 is a comparison diagram of current-voltage characteristics according to the embodiment of the present invention and a conventional example. FIG. 6 shows the carbon compound concentration characteristics of the current amplification factor of the semiconductor device according to the embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 1 Substrate 2 Embedded layer 3 Collector layer 4 Intrinsic base region 5 External base region 6 Emitter region 7 Subcollector region 8 Polycrystalline silicon region 30 Carbon-containing thin film layers 101, 102, 103 Insulating film 200 Emitter electrode 201 Base Electrode 202 Collector electrode B Polycrystalline silicon / silicon interface C Emitter / base interface

Claims (8)

A base region formed on the collector region;
An emitter region formed on the base region;
A polycrystalline silicon region formed on the emitter region and doped with impurities;
A semiconductor device comprising a carbon-containing thin film layer at an interface between the polycrystalline silicon region and the emitter region. The semiconductor device according to claim 1,
On the semiconductor substrate,
A first conductivity type buried layer;
A first conductivity type epitaxial collector region;
An intrinsic base region of the second conductivity type;
The emitter region;
The polycrystalline silicon regions are arranged in order,
An external base region adjacent to the intrinsic base region and a sub-collector region adjacent to the epitaxial collector region;
The intrinsic base region is connected to a base electrode through the external base region,
The epitaxial collector region is connected to a collector electrode through the subcollector region. Forming a buried layer on the substrate;
Forming a collector region on the buried layer by epitaxial growth;
Forming a subcollector region in the collector region by ion implantation;
Forming an insulating film for element isolation on the collector region;
Forming an external base region and an intrinsic base region in the active region of the collector region;
Forming an insulating film on the intrinsic base region, the external base region, and the subcollector region; and
Opening an emitter contact in the insulating film, and forming a carbon-containing thin film layer on the opening surface of the emitter contact;
Depositing a polycrystalline silicon region to cover the emitter contact and part of the insulating film;
Implanting impurities into the polycrystalline silicon region on the emitter contact and diffusing the impurity by heat treatment to form an emitter region in the intrinsic base around the opening of the emitter contact;
Depositing an insulating film for electrode separation, annealing the insulating film, and then opening a base contact, an emitter contact, and a collector contact, and forming an electrode. A semiconductor manufacturing method according to claim 3,
The step of forming the carbon-containing thin film layer includes
A semiconductor manufacturing method comprising the step of immersing the opening surface of the emitter contact in a solvent containing a diluted carbon compound. The semiconductor manufacturing method according to claim 4,
The said solvent is any one of the pure water, ethanol, ether, or its combination, and a carbon compound is a soluble solvent. The semiconductor manufacturing method. A semiconductor manufacturing method according to claim 3,
The step of forming the carbon-containing thin film layer includes
A method for manufacturing a semiconductor, comprising: exposing an opening surface of the emitter contact in an atmosphere containing a carbon compound. The semiconductor manufacturing method according to claim 6.
The step of exposing the opening surface is performed in an atmosphere of any one of clean air containing a carbon compound, nitrogen gas, and carbon dioxide gas. In the semiconductor manufacturing method of Claim 3 to 7,
The carbon compound is
Among diethyl phthalate, dibutyl phthalate, dioctyl phthalate, 2,6-di-tert-butyl-4-methylphenol, menthol, biphenyl, butyric acid, One of the methods is a semiconductor manufacturing method.

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