JP2006221752A - Reproducing signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a device at low costs by reducing the influence of intercode interferences even without using a waveform equalizer circuit using an analog circuit or a multivalue AD converter circuit when a reproducing signal from a recording medium is subjected to waveform equalization by a waveform equalizing means constituted of a digital circuit. <P>SOLUTION: A binarization circuit 2 binarizes a reproducing signal, occurrence time of changing points of a binary signal is sequentially stored in an edge generation time memory 6, a pattern length before second occurrence time is measured by a pattern length computing circuit 12 based on first and second occurrence times of three occurrence times continuous in storage order, a pattern length after the second occurrence time is measured by a pattern length computing circuit 13 based on the second and third occurrence times, correction time is calculated by an edge position correction circuit 14 according to the combination of the pattern lengths before and after the second occurrence time, correction time is calculated from the correction hour, and an equalizing signal is outputted at each correction time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reproduction signal processing apparatus for processing a reproduction signal from a recording medium including a CD, a DVD, and an MO.

When information is recorded at a high density on a recording medium such as an optical disk or a magnetic disk, the reproduced signal is distorted by the influence of so-called intersymbol interference.
For example, when reproducing information recorded with a mark length on an optical disc, the edge position of each mark length is shifted from the original position due to the influence of intersymbol interference, resulting in an information reading error.
In order to correct the influence of such intersymbol interference, a reproduction signal processing apparatus from a conventional recording medium uses a waveform equalizer.
The waveform equalizer generally performs filter processing that emphasizes the high frequency band to reduce the influence of intersymbol interference of the reproduced signal.

In recent years, the integration of circuits has progressed, and the reproduction signal processing apparatus has been integrated into one integrated circuit.
Conventionally, as shown in FIG. 15, the reproduction signal of the optical disk from the head 100 is equivalently processed by an equalizer 101 (corresponding to a “waveform equivalent circuit”) 101 configured by an analog circuit, and binary through an AGC circuit 102. There is a reproduction signal circuit (see, for example, Patent Document 1) that outputs to the conversion circuit 103, binarizes by the binarization circuit 103, is converted into a digital signal, and is decoded by the decoding circuit 104.
Also, as shown in FIG. 16, an optical disk reproduction signal is input from the head 110, passed through the VGA circuit 111 and the LPF 112, and then converted into multilevel digital data by the AD conversion circuit 113. The digital data is equivalently processed by a PR equalizer (corresponding to a “waveform equivalent circuit”) 114 and a COS equalizer 115 (corresponding to a “waveform equivalent circuit”) configured by a digital circuit, and the output signal is used to perform Viterbi. There is a reproduction signal circuit (for example, see Patent Document 2) in which the decoding circuit 116 performs a decoding process.
Japanese Patent Laid-Open No. 06-005013 JP 09-007301 A

However, in the conventional reproduction signal processing apparatus having the configuration shown in FIG. 15, the equalizer 101 is configured by an analog circuit, and when it is intended to be mounted on the same integrated circuit as the decoding circuit 104 configured by a subsequent digital circuit, There is a problem that the circuit area of the analog circuit portion is increased, and it is difficult to reduce the size and cost of the circuit.
Further, in the conventional reproduction signal processing apparatus having the configuration shown in FIG. 16, the PR equalizer 114 and the COS equalizer 115 are constituted by digital circuits, and the same integrated circuit as the Viterbi decoding circuit 116 constituted by the subsequent digital circuit is provided. Although it is easy to integrate, an AD conversion circuit 113 that converts a reproduction signal into multi-level digital data is necessary. By mounting the AD conversion circuit 113, the circuit area is increased, and the circuit is reduced in size and cost. There was a problem that was difficult.

  The present invention has been made in view of the above points, and in performing waveform equalization with a waveform equivalent means constituted by a digital circuit, a reproduction signal from a recording medium is equivalent to a waveform equivalent circuit using an analog circuit or a multi-value. It is an object of the present invention to reduce the influence of intersymbol interference without using an AD conversion circuit and to reduce the size of the apparatus at low cost.

In order to achieve the above object, the present invention provides the following reproduction signal processing apparatus.
(1) Binarization means for binarizing a reproduction signal reproduced from a recording medium, and change for sequentially storing the occurrence time when the change point of the binarized signal binarized by the binarization means occurs Based on the first occurrence time and the second occurrence time of the three occurrence times in which the storage order stored in the point occurrence time storage means and the change point occurrence time storage means continues, the previous occurrence point for the occurrence point of the second occurrence time A pattern length measuring unit that measures a pattern length and measures a subsequent pattern length with respect to an occurrence point of the second occurrence time based on the second and third occurrence times, and a pattern length measurement unit before the pattern length measurement unit Correction time calculation means for calculating a correction time corresponding to the combination of the pattern length and the subsequent pattern length, and each occurrence time stored in the change point occurrence time storage means with the correction time calculated by the correction time calculation means A correction time calculation means for calculating a correction time by adding each correction time reproduction signal processing apparatus including an equalized signal output means for outputting an equalized signal to the correction time calculated by the calculation means.

(2) In the reproduction signal processing apparatus of (1), the pattern length measuring means is stored in advance when the third occurrence time cannot be obtained from the change point occurrence time storage means within a predetermined time. A reproduction signal processing apparatus having a predetermined value as the rear pattern length.
(3) In the reproduction signal processing apparatus of (1), the recording medium is an optical recording medium, and the correction time is a negative value when the preceding pattern length is larger than the following pattern length. A reproduction signal processing device that is a positive value when the preceding pattern length is smaller than the following pattern length.
(4) In the reproduction signal processing apparatus according to (1), the recording medium is a magnetic recording medium, and the correction time is a positive value when the preceding pattern length is larger than the following pattern length. A reproduction signal processing device that has a negative value when the preceding pattern length is smaller than the following pattern length.

(5) Binarization means for binarizing the reproduction signal reproduced from the recording medium, and change for sequentially storing the time of occurrence when the change point of the binarized signal binarized by the binarization means occurs A pattern in which the pattern length is measured based on two generation times of which the storage order is adjacent to each other for a plurality of generation times in which the storage order stored in the point generation time storage means and the change point generation time storage means is continuous A length measuring means, a correction time calculating means for calculating a correction time according to a combination of a plurality of pattern lengths measured by the pattern length measuring means, and the correction time calculated by the correction time calculating means for generating the change point. Correction time calculation means for calculating a correction time added to each occurrence time stored in the time storage means, an equalization signal is output at each correction time calculated by the correction time calculation means, etc. Reproduction signal processing apparatus including a signal output unit.

  The reproduction signal processing apparatus according to the present invention does not use a waveform equivalent circuit using an analog circuit or a multi-level AD conversion circuit when equalizing the waveform of a reproduction signal from a recording medium by a waveform equivalent means constituted by a digital circuit. However, the influence of intersymbol interference can be reduced, and the apparatus can be downsized at low cost.

Hereinafter, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
[Example 1]
FIG. 1 is a block diagram showing the configuration of a reproduction signal processing circuit according to Embodiment 1 of the present invention.
FIG. 2 is an operation waveform diagram of the reproduction signal processing circuit shown in FIG.
As shown in FIG. 1, in this reproduction signal processing circuit, a head 1 reproduces a signal from a recording medium such as an optical disk or a magnetic disk. The reproduced signal is binarized by the binarizing circuit 2 and converted into a digital signal.
The PLL circuit 3 generates a reproduction clock synchronized with the edge of the binarized signal. The PLL circuit 3 generates an N-phase multiphase clock having a predetermined phase shift at the same frequency as the reproduction clock.

FIG. 3 is a block diagram showing an example of the internal configuration of the PLL circuit 3 shown in FIG.
As shown in FIG. 3, differential buffers 33-1 to 33-N (N is a positive integer) connected to N stages are multiphase clock sources.
Each differential buffer 33-1 to 33-N is fed back to the first-stage differential buffer 33-1 so that the output of the last-stage differential buffer 33-N is inverted, and constitutes a so-called ring oscillator. is doing.
The outputs of the differential buffers 33-1 to 33-N are output as N-phase output clocks Clk1, Clk2, Clk3,..., ClkN via the output buffers 34-1 to 34-N.

The N-phase output clocks Clk1, Clk2, Clk3,..., ClkN all have the same frequency and have a predetermined phase difference from each other.
FIG. 4 is a waveform diagram showing the relationship between the N-phase output clocks Clk1, Clk2, Clk3,..., ClkN.
The operating current of each differential buffer 33-1 to 33-N can be changed by a common control terminal, and the oscillation frequency of the multiphase clock source can be changed by changing the voltage of the control terminal. Can do.
The phase difference between the input signal (binarized signal) of the PLL circuit 3 and ClkN, which is one of the output clocks, is compared by the phase comparison unit 30, and the voltage according to the phase difference is obtained by the charge pump 31 and the filter 32. It is given to the control terminal.

As a result, a phase locked loop is formed, and the output clock ClkN is a clock signal synchronized with the binarized signal.
The bit number counter 5 is incremented for each cycle of the output clock ClkN and outputs the current bit number Tb.
In FIG. 2, the range of Tb = 0, 1,.
The edge position detection circuit 4 outputs an edge position signal Te having a value corresponding to the phase of the binarized signal from the phase relationship between the multiphase clock and the binarized signal.
FIG. 5 is a block diagram showing an example of the internal configuration of the edge position detection circuit 4 shown in FIG.
FIG. 6 is an operation waveform diagram of the edge position detection circuit shown in FIG.

The edge position detection circuit 4 has N (N is a positive integer) DFFs 40-1 to 40 each having a binary signal as a D input and N-phase clocks Clk1, Clk2, Clk3,. -N and the pattern determination circuit 41.
The combination pattern of the outputs of the N DFFs 40-1 to 40-N varies depending on the phase relationship between the N-phase clocks Clk1, Clk2, Clk3,.
The pattern determination circuit 41 detects the edge position of the binarized signal from the combination pattern output from the N DFFs 40-1 to 40-N, and outputs the edge position signal Te.
FIG. 6 is an operation waveform diagram when N = 8.

One cycle of the clock ClkN is divided into 8 and numbers 1 to 8 are assigned in order from the front. In the first cycle of the clock ClkN, the binarized signal has a changing edge at the position of “3” of the 8 division number. In this case, the edge position detection circuit 4 sets Te to “3” during one cycle of the next clock Clk1.
Similarly, in the second and third cycles of the clock ClkN, the change edge position of the binarized signal is the position of “5” and “7” of the 8-division number, respectively. Becomes “5” and “7”, respectively.
When there is no change edge of the binarized signal, Te is “0”.

FIG. 2 shows an example in which the edge of the binarized signal is generated at the positions of Tb = “0”, “2”, “6”, and “8”, and Te is delayed by one clock of the clock ClkN. = "7""4""7""2" are output.
For other Tb, Te = “0”, but the illustration is omitted.
The decoding circuit 7 sets the load signal Ld to “1” when Te is not “0”, that is, when there is a change edge of the binarized signal.
FIG. 2 shows a case where Ld = “1” at the positions of Tb = “1”, “3”, “7”, and “9”.
The edge generation time memory 6 fetches and stores the current bit number Tb and the edge position signal Te every time the load signal Ld becomes “1”.

That is, every time a change edge of the binarized signal occurs, the edge generation time memory 6 generates a change edge of the binarized signal by combining the bit number Tb and the edge position signal Te at the time when the change edge occurs. Time is memorized sequentially.
The bit number Tb and the edge position signal Te are processed, for example, by adding Tb as the upper bits of Te and combining them as one data corresponding to Tb * N + Te. That is, the combined time data is a value obtained by counting one cycle of the clock ClkN in units of N division.
In FIG. 2, the combined data is shown as (Tb, Te).
FIG. 7 is a block diagram showing an example of the internal configuration of the edge generation time memory 6 shown in FIG.

The edge occurrence time memory 6 includes M (M is a positive integer) stage registers (REG) 60-1 to 60-M. The edge position occurrence time (Tb, Te) is stored in the first-stage register 60-1 every time the load signal Ld becomes “1”, and the values already stored in the respective registers are Shifted to the stage register.
Three multiplexers (MUX) 61 to 63 select and output one of the outputs of the M-stage registers 60-1 to 60-M, respectively.
In FIG. 7, the center multiplexer 62 is a register for selecting an edge occurrence time (Tb0, Te0) to be corrected for the edge position, and the register number is designated by the selection signal A0.

In FIG. 7, the upper multiplexer 61 and the lower multiplexer 63 select the previous and subsequent edge generation times (Tb−, Te−) and (Tb +, Te +) of the edge whose edge position is to be corrected, respectively. The register numbers are designated by the selection signals A− and A +, respectively.
FIG. 2 shows an example in which Tb = “1” and Ld = “1”.
Therefore, a combination of Tb and Te values “1” and “7” at the time of Tb = “1” is stored in REG1.
The values “−1” and “4” of Tb and Te already stored in REG1 (register 60-1) shown in (h) of FIG. 2 are the values of REG2 (register 60-2) shown in (i) of FIG. Shifted to.

Next, Tb = “3” and Ld = “1”.
Therefore, the combination of Tb and Te values “3” and “4” at the time of Tb = “3” is stored in REG1 (register 60-1) shown in FIG.
The values “1” and “7” of Tb and Te already stored in REG1 (register 60-1) are shifted to REG2 (register 60-2) shown in (i) of FIG. The values “−1” and “4” of Tb and Te already stored in 2) are shifted to REG3 (register 60-3) shown in FIG.
The delay circuit 8 delays the load signal Ld and outputs a delay signal DLd.
Here, the predetermined delay amount Dly1 is, for example, an amount slightly longer than the maximum inversion length of the binarized signal.

FIG. 2 shows an example in which the predetermined delay amount Dly1 is five clocks of the clock ClkN, and DLd = “1” at the positions of Tb = “6” “8” “12” “14”. Yes.
An up / down counter (referred to as “U / D counter” in the figure) 9 counts up with a load signal Ld and counts down with a delay signal DLd.
The count value of the U / D counter 9 is the selection signal A0 and indicates the register number in which the edge generation time that is the correction target of the edge position is stored.
By generating the selection signal A0 in this way, the edge generation time (Tb0, Te0) to be selected as the edge position correction target becomes the edge position generation time (Tb, Te) input to the edge generation time memory 6. Is delayed by the delay amount of the delay circuit 8 + 1 (Dly1 + 1).

In the example shown in FIG. 2, A0 = "1" when Tb = "0""1".
The register selected here is REG1 (register 60-1) shown in (h) of FIG. 2, and Tb, Te = “− 1” and “4” are read out.
In addition, when Tb = “2” “3”, A0 = “2”.
The register selected here is REG2 (register 60-2) shown in (i) of FIG. 2, but the read values are the same as Tb, Te = “− 1” and “4”.
Further, when Tb = “4”, “5”, “6”, A0 = “3”.
The register selected here is REG3 (register 60-3) shown in (j) of FIG. 2, but the read values are Tb, Te = “− 1” and “4”, which are also the same.

Further, Tb = “7” and A0 = “2”.
The register selected here is REG2 (register 60-2) shown in FIG. 2 (i). At this time, the read value changes to Tb, Te = “1” and “7”.
Although the following description is omitted, the edge generation time (Tb0, Te0) selected from A0 and read from the edge generation time memory 6 is the edge position generation time (Tb, Te) input to the edge generation time memory 6. ) Is delayed by 6 clocks of the clock ClkN.
The increment circuit 10 adds 1 to the selection signal A0 and outputs a selection signal A− indicating the register number in which the edge generation time (Tb−, Te−) before the edge position correction target edge is stored.

The decrement circuit 11 subtracts 1 from the selection signal A0 and outputs a selection signal A + indicating a register number in which the edge generation time (Tb +, Te +) after the edge position correction target edge is stored.
In this way, the edge generation time memory 6 outputs the edge generation time (Tb0, Te0) for edge position correction, and the edge generation times (Tb−, Te−) and (Tb +, Te +) before and after the edge generation time. Is done.
The pattern length calculation circuit 12 calculates the difference L− between the edge generation time (Tb0, Te0) subject to edge position correction and the previous edge generation time (Tb−, Te−). The calculated value is the pattern length before the edge position correction target edge.

The pattern length calculation circuit 13 calculates a difference L + between the edge generation time (Tb0, Te0) subject to edge position correction and the subsequent edge generation time (Tb +, Te +). The calculated value is the pattern length behind the edge position correction target edge.
In FIG. 2, the edge generation time (Tb0, Te0) of the edge position correction target at the position of Tb = “7” is “1” “7”, and the previous edge generation time (Tb−, Te−) is “−1” and “4”.
As a result, as the pattern length L− before the edge position correction target edge, (Tb0− (Tb −)) * 8+ (Te0− (Te −)) = (1 − (− 1)) * 8+ (7−4) ) = 19 is calculated.

This pattern length is a value counted on the basis of a time obtained by dividing one cycle of the clock ClkN into N (here, 8).
Similarly, the edge generation time (Tb +, Te +) after the edge position correction target edge at the position of Tb = “7” is “3” “4”.
As a result, ((Tb +) − Tb0) * 8 + ((Te +) − Te0) = (3-1) * 8 + (4-7) = 13 is calculated as the pattern length L + behind the edge position correction target edge. The
The edge position correction circuit 14 outputs an edge position correction amount dTe according to the combination of the pattern lengths (L−, L +) before and after the edge position correction target edge.

It has already been stated that when information recorded with a mark length on an optical disk is reproduced, the edge position of each mark is shifted from the original position due to the effect of intersymbol interference, resulting in information reading errors. However, intersymbol interference in mark length recording occurs when the edge position of each mark changes depending on the pattern length before and after.
Therefore, it is possible to reduce the influence of intersymbol interference by correcting the edge position of each mark according to the combination of the pattern lengths (L−, L +) before and after the mark.
Here, to simplify the description, the edge position correction amount dTe is “−1” if L−> L +, and “+1” if L− <L +.
FIG. 2 shows an example in which the edge position correction amount dTe = “− 1” because L−> L + at the position of Tb = “7”.

Further, since L− <L + at the position of Tb = “9”, the edge position correction amount dTe = “+ 1”.
The adding circuit 15 adds the edge position correction amount dTe and a predetermined delay amount Dly2 to the edge generation time (Tb0, Te0) to be edge position corrected, and the edge generation time (Tb0Eq, Te0Eq) after the edge position correction is added. Output. Here, the delay amount Dly2 is larger than the delay amount Dly1.
In FIG. 2, at the position of Tb = “7”, the edge generation time (Tb0, Te0) = “1” “7” and the edge position correction amount dTe = “− 1”. Here, the delay amount Dly2 is assumed to be eight clocks of the clock ClkN.

Therefore, the edge generation time (Tb0Eq, Te0Eq) after edge position correction = “Tb0 + Dly2”, “Te0 + dTe” = “9”, “6”.
At the position of Tb = “9”, the edge generation time (Tb0, Te0) = “3” “4” and the edge position correction amount dTe = “+ 1”, so that the edge generation time after the edge position correction (Tb0Eq, Te0Eq) = "11""5".
The timing circuit 19 receives the delay signal DLd, and alternately stores the edge generation time (Tb0Eq, Te0Eq) after edge position correction in the two registers (REGa) 16 and (REGb) 17 at the next clock timing. To go.
One of the stored values is selected and output by a multiplexer (MUX) 18.

The quotient calculation circuit 20 and the remainder calculation circuit 21 calculate the quotient (integer value) and the remainder when the input data is divided by N, respectively.
Since the edge generation time (Tb0Eq, Te0Eq) after edge position correction is a value obtained by counting one cycle of the clock ClkN in units of N, the quotient is the bit number of the edge generation time after edge position correction, and the remainder Indicates the edge position in the corresponding bit number.
In FIG. 2, after Tb = “8”, the register (REGa) 16 holds the edge generation time (Tb0Eq, Te0Eq) = “9”, “6” after edge position correction. As described above, the data is actually combined and processed as one piece of data, and held as a value of Tb0Eq * N + Te0Eq = “78”.

The quotient calculation circuit 20 and the remainder calculation circuit 21 respectively separate the edge generation times Tb0Eq and Te0Eq after edge position correction from the one data. When Tb = “8”, the edge generation time Tb0Eq after edge position correction is obtained. “9” and Te0Eq = “6” are output.
The comparator 22 compares the bit number Tb0Eq of the edge generation time after edge position correction with the output value Tb of the bit number counter, and if it matches, the output of the gate circuit 23 is enabled, and the corrected edge is output from the gate circuit 23. A position signal TeEq is output.
FIG. 2 shows edge generation times Tb0Eq “9” and Te0Eq = “6” after edge position correction after Tb = “8”.
Therefore, when Tb = “9”, the comparator 22 enables the output of the gate circuit 23, and the corrected edge position signal TeEq = “6” is output.

Similarly, when Tb = “11”, TeEq = “5” is output, and when Tb = “15”, TeEq = “6” is output. For other Tb, TeEq = “0”, but not shown.
The corrected edge position signal TeEq output in this way is obtained by delaying the edge position signal Te detected by the edge position detection circuit 4 by a predetermined amount, as shown by the one-dot chain line arrow in FIG. The edge position is corrected.
The corrected edge position signal TeEq is input to the decoding circuit 24, and the signal read from the recording medium is decoded into the original digital data.

As described above, in the reproduction signal processing circuit from the recording medium of Example 1 shown in FIG. 1, the influence of intersymbol interference is obtained by correcting the edge position of each mark according to the combination of the pattern lengths before and after the mark. Can be reduced.
In addition, since the reproduced signal processing circuit is composed of a digital circuit without using a waveform equalizer or multi-level AD converter using an analog circuit, the circuit can be reduced in size and cost.

[Example 2]
Next, a reproduction signal processing circuit according to Embodiment 2 of the present invention will be described.
FIG. 8 is a block diagram showing the configuration of the reproduction signal processing circuit according to the second embodiment of the present invention. The same reference numerals are given to the portions common to FIG. 1, and the description thereof is omitted.
FIG. 9 is an operation waveform diagram of the reproduction signal processing circuit shown in FIG.
The decode circuit 25 receives the selection signal A0 that is output from the U / D counter 9 and selects the edge generation time (Tb0, Te0) for which the edge position is to be corrected, and underflows when the value is “1”. The (UF) signal is output.
The state of UF signal = “1” indicates the state of selection signal A0 = “1”. In this case, the selection signal A + output from the decrement circuit 11 is “0”.

However, there is no register in the edge generation time memory 6 selected when these selection signals are “0”.
That is, in the state where the UF signal = “1”, the edge generation time (Tb0, Te0) to be subjected to edge position correction is read from the edge generation time memory 6 with a predetermined delay amount Dly1 for pattern length measurement. However, at that time, the next edge generation time (Tb +, Te +) has not yet occurred, indicating that reading is impossible.
When the UF signal = “0” (selection signal A0 ≠ “0”), the pattern length calculation circuit 13 ′ shown in FIG. 8 sets the pattern length L + behind the edge position correction target edge in the same manner as that in FIG. When the UF signal = "1" (selection signal A0 = "0"), a predetermined amount of value is output as the pattern length L + behind the edge position correction target edge.

The predetermined amount is appropriately set to a value slightly larger than the delay time Dly1.
In FIG. 9, the operation waveform before Tb = “6” is the same as FIG.
In the operation waveform example shown in FIG. 9, after Tb = “3” and the edge of the binarized signal is detected, the next edge is not detected until Tb = “10”.
Therefore, when Tb = “9”, “10”, “11”, the state of the selection signal A0 = “0” occurs, and the underflow signal (UF) is “1”.
The edge generation time (Tb0, Te0 = “3” “4”) to be edge position corrected is read from the edge generation time memory 6 with the predetermined delay amount Dly1 at the timing of Tb = “9”. The next edge generation time (Tb +, Te +) has not yet occurred, and Tb +, Te + are indefinite (indicated by “X” in the figure).

Since the UF signal = “1” (A0 = “0”), the pattern length calculation circuit 13 ′ outputs a predetermined amount of value as the pattern length L + behind the edge position correction target edge.
In this example, the pattern length L + = “48”.
This is a value obtained by counting the delay amount corresponding to 6 clocks of Dly1 + 1 based on the time obtained by dividing one period of the clock ClkN into N (here, 8) (6 * 8 = 48).
In general, the intersymbol interference amount has a tendency that the amount of change in the waveform interference amount due to the change in the pattern length becomes smaller when one of the front and rear pattern lengths exceeds a certain value.
This is because, for example, when the recording medium is an optical disc, if the pattern length is larger than that of the light spot system, the amount of reflected light is not changed even if the pattern length is further increased.

Therefore, at a certain pattern length or longer, as shown in the present embodiment, even if the pattern length is changed to a predetermined value, sufficiently accurate intersymbol interference can be corrected.
In the example of FIG. 1, it is necessary to increase the delay amount Dly1 according to the pattern length to be handled and increase the storage capacity of the edge generation time memory 6 according to the number of edges that can be generated within that time. .
In the reproduction signal processing circuit shown in FIG. 8, the pattern length to be handled is set at a predetermined amount, so that the storage capacity of the edge generation time memory 6 can be reduced, and the circuit can be further reduced in size and cost. Become.

Example 3
Next, a reproduced signal processing circuit according to Embodiment 3 of the present invention will be described.
The configuration of this reproduction signal processing circuit is the same as that of the reproduction signal processing circuit shown in FIG. 1 or FIG.
FIG. 10 is a waveform diagram showing the relationship between the combination of the input pattern lengths (L−, L +) and the edge position correction amount dTe in the edge position correction circuit 14 of the reproduction signal processing circuit according to the third embodiment of the present invention.
FIG. 11 is a waveform diagram for explaining the state of intersymbol interference in an optical recording medium such as an optical disk.

FIG. 11 shows the case of mark length recording. The solid line in FIG. 6A shows the waveforms of the original recording data and the reproduction signal when the relationship between the pattern lengths L− and L + before and after a certain edge is in the relationship of L− <L +. Also, the dotted line in (b) of the figure shows the original recording data and the reproduction signal waveform when the relationship between the pattern lengths (L−, L +) before and after a certain edge is L− = L +. .
In the optical recording medium, as shown in FIG. 11, the intersymbol interference causes the signal level at the original edge position to shift in the direction of the signal level of the longer pattern length before and after the edge, resulting in reproduction. The zero cross point position of the signal is generated so as to shift to the shorter pattern length before and after the edge.

Although not shown, the direction of intersymbol interference is the same in the case of mark position recording.
Therefore, when the optical recording medium is used, in the case of L− <L + in FIG. 11A, the position of the binarized signal is shifted backward, that is, the edge position correction amount dTe is set in the positive direction. The correction is suitable as a correction direction of intersymbol interference.
Although not shown, in the case of L-> L +, correction with the edge position correction amount dTe in the negative direction is appropriate.
As shown in FIG. 10, the input / output characteristics of the edge position correction circuit 14 are shown in a three-dimensional graph. The characteristics of the edge position correcting circuit 14 are exactly the characteristics suitable for the optical recording medium described above.
In this manner, this reproduction signal processing circuit can correct intersymbol interference suitable for a case where the recording medium is an optical recording medium such as an optical disk.

Example 4
Next, a reproduced signal processing circuit according to Embodiment 4 of the present invention will be described.
The configuration of this reproduction signal processing circuit is the same as that of the reproduction signal processing circuit shown in FIG. 1 or FIG.
FIG. 12 is a waveform diagram showing the relationship between the combination of the input pattern lengths (L−, L +) and the edge position correction amount dTe in the edge position correction circuit 14 of the reproduction signal processing circuit according to the fourth embodiment of the present invention.
FIG. 13 is a waveform diagram for explaining the state of intersymbol interference in a magnetic recording medium such as a magnetic disk.
In magnetic recording, the peak position of a reproduction signal is detected as equivalent to detection of a reproduction signal zero cross point in mark length recording of an optical disk.

The solid line in FIG. 13A shows the waveforms of the original recording data and the reproduction signal when the relationship between the pattern lengths (L−, L +) before and after a certain edge is L− <L +. Yes.
Also, the dotted line in (b) of the figure shows the original recording data and the reproduction signal waveform when the relationship between the pattern lengths (L−, L +) before and after a certain edge is L− = L +. .
In the magnetic recording medium, as shown in FIG. 13, the intersymbol interference occurs such that the peak position of the reproduction signal is shifted to the longer pattern length before and after the edge.
Therefore, when using a magnetic recording medium, the position of the binarized signal is shifted forward in the case of L− <L + in FIG. That is, the correction in which the edge position correction amount dTe is in the negative direction is suitable as the correction direction of the intersymbol interference.

Although not shown, in the case of L-> L +, correction with the edge position correction amount dTe as the positive direction is appropriate.
As shown in FIG. 12, the input / output characteristics of the edge position correction circuit 14 are shown in a three-dimensional graph. The characteristics of the edge position correction circuit 14 are exactly the characteristics suitable for the magnetic recording medium described above.
In this way, this reproduction signal processing circuit can correct intersymbol interference suitable for the case where the recording medium is a magnetic recording medium such as a magnetic disk.

Example 5
Next, a reproduction signal processing circuit according to Embodiment 5 of the present invention will be described.
FIG. 14 is a block diagram showing the configuration of the reproduction signal processing circuit according to the fifth embodiment of the present invention. The same reference numerals are given to the portions common to FIG. 1, and the description thereof is omitted.
The edge generation time memory 6 ′ includes edge generation times (Tb0, Te0) (Tb−, Te−) (Tb +, Te +), which are outputs of the edge generation time memory 6 shown in FIG. The edge generation time (Tb--, Te--) (Tb ++, Te ++) two times before and two times after is output. The output registers are designated by selection signals A-- and A ++, respectively.

The increment circuit 26 adds 2 to the selection signal A0, and outputs a selection signal A-- indicating the register number in which the edge generation time (Tb--, Te--) immediately before the edge position correction target edge is stored. To do.
The decrement circuit 27 subtracts 2 from the selection signal A0, and outputs a selection signal A ++ indicating a register number in which the edge generation time (Tb ++, Te ++) two edges after the edge position correction target edge is stored.
In the pattern length calculation circuit 28, a difference L−− between the edge generation time (Tb−, Te−) before the edge position correction target edge and the previous edge generation time (Tb−−, Te−−) is obtained. Calculated.

The pattern length calculation circuit 29 calculates the difference L ++ between the edge generation time (Tb +, Te +) after the edge position correction target edge and the subsequent edge generation time (Tb ++, Te ++).
The edge position correction circuit 14 'outputs an edge position correction amount dTe according to a combination of four pattern lengths (L--, L-, L +, L ++) before and after the edge position correction target edge.

As described above, in this reproduction signal processing circuit, the edge position of each mark is corrected in accordance with the combination of four or more pattern lengths before and after the mark, and therefore, compared with the reproduction signal processing circuit of the first embodiment. It is possible to accurately reduce the influence of intersymbol interference.
Similarly to the reproduction signal processing circuit of the first embodiment, the reproduction signal processing circuit of the fifth embodiment is configured by a digital circuit without using a waveform equalizer or multi-level AD converter using an analog circuit. Therefore, the circuit can be reduced in size and cost.

  The reproduction signal processing apparatus according to the present invention can be applied to all apparatuses for reproducing a recording medium.

1 is a block diagram showing a configuration of a reproduction signal processing circuit according to Embodiment 1 of the present invention. FIG. FIG. 2 is an operation waveform diagram of the reproduction signal processing circuit shown in FIG. 1. FIG. 2 is a block diagram illustrating an example of an internal configuration of a PLL circuit 3 illustrated in FIG. 1. FIG. 6 is a waveform diagram showing the relationship between N-phase output clocks Clk1, Clk2, Clk3,..., ClkN.

FIG. 2 is a block diagram illustrating an example of an internal configuration of an edge position detection circuit 4 illustrated in FIG. 1. FIG. 6 is an operation waveform diagram of the edge position detection circuit shown in FIG. 5. It is a block diagram which shows an example of an internal structure of the edge generation time memory 6 shown in FIG. It is a block diagram which shows the structure of the reproduction | regeneration signal processing circuit of Example 2 of this invention. FIG. 9 is an operation waveform diagram of the reproduction signal processing circuit shown in FIG. 8.

It is a wave form diagram which shows the relationship between the combination of input pattern length (L-, L +) in the edge position correction circuit 14 of the reproduction signal processing circuit of Example 3 of this invention, and edge position correction amount dTe. It is a wave form diagram with which it uses for description of the mode of intersymbol interference in optical recording media, such as an optical disk. It is a wave form diagram which shows the relationship between the combination of input pattern length (L-, L +) in the edge position correction circuit 14 of the reproduction signal processing circuit of Example 4 of this invention, and edge position correction amount dTe. It is a wave form diagram with which it uses for description of the mode of intersymbol interference in magnetic recording media, such as a magnetic disc.

It is a block diagram which shows the structure of the reproduction | regeneration signal processing circuit of Example 5 of this invention, and attaches | subjects the same code | symbol to the part which is common in FIG. 1, and abbreviate | omits the description. It is a block diagram which shows the structure of the conventional reproduction | regeneration signal processing apparatus. It is a block diagram which similarly shows the other structural example of the conventional reproduction | regeneration signal processing apparatus.

Explanation of symbols

1, 100, 110: Head 2, 103: Binary circuit 3: PLL circuit 4: Edge position detection circuit 5: Bit number counter 6, 6 ': Edge generation time memory 7: Decoding circuit 8: Delay circuit 9: U / D counter 10, 26: Increment circuit 11, 27: Decrement circuit 12, 13, 28, 29: Pattern length calculation circuit 14, 14 ': Edge position correction circuit 15: Addition circuit 16, 17: Register 18, 61-63 : Multiplexer 19: timing circuit 20: quotient operation circuit 21: remainder operation circuit 22: comparator 23: gate circuit 24, 104: decoding circuit 25: decoding circuit 30: phase comparison unit 31: charge pump 32: filters 33-1 to 33 -N: differential buffer 34 1 to 34-N: output buffer 40-1 to 40-N: DFF 41: pattern determination circuit 60-1 to 60-M: register 101: equalizer 102: AGC circuit 111: VGA circuit 112: LPF 113: AD conversion circuit 114: PR equalizer 115: COS equalizer 116: Viterbi decoding circuit

Claims (5)

  Binarization means for binarizing the reproduction signal reproduced from the recording medium, and change point occurrence time for sequentially storing the occurrence time when the change point of the binarized signal binarized by the binarization means occurs Based on the first generation time and the second generation time of the three generation times in which the storage order stored in the storage unit and the change point generation time storage unit is continuous, the previous pattern length for the generation point of the second generation time is obtained. A pattern length measuring means for measuring and measuring a pattern length after the second occurrence time based on the second and third occurrence times, and a previous pattern length measured by the pattern length measuring means; Correction time calculating means for calculating a correction time according to the combination of the subsequent pattern lengths, and adding the correction time calculated by the correction time calculating means to each occurrence time stored in the change point occurrence time storage means A correction time calculation means for calculating a correction time, the correction time calculation means that an equalized signal output means for outputting an equalized signal to the correction time calculated by wherein the reproduction signal processing apparatus.   2. The reproduction signal processing apparatus according to claim 1, wherein the pattern length measurement means sets a predetermined value stored in advance when the third generation time cannot be obtained from the change point generation time storage means within a predetermined time. A reproduction signal processing apparatus having the pattern length after the rear.   The reproduction signal processing device according to claim 1, wherein the recording medium is an optical recording medium, and the correction time is a negative value when the previous pattern length is larger than the subsequent pattern length, The reproduction signal processing device according to claim 1, wherein when the preceding pattern length is smaller than the following pattern length, the reproducing signal processing device is a positive value.   The reproduction signal processing apparatus according to claim 1, wherein the recording medium is a magnetic recording medium, and the correction time is a positive value when the previous pattern length is larger than the subsequent pattern length. The reproduction signal processing apparatus according to claim 1, wherein when the preceding pattern length is smaller than the following pattern length, the reproducing signal processing apparatus has a negative value.   Binarization means for binarizing the reproduction signal reproduced from the recording medium, and change point occurrence time for sequentially storing the occurrence time when the change point of the binarized signal binarized by the binarization means occurs Pattern length measuring means for measuring a pattern length based on two occurrence times whose storage orders are adjacent to each other for a plurality of occurrence times in which the storage order stored in the storage means and the change point occurrence time storage means is continuous Correction time calculation means for calculating a correction time according to a combination of a plurality of pattern lengths measured by the pattern length measurement means, and the correction time calculated by the correction time calculation means as the change point occurrence time storage means Correction time calculation means for calculating a correction time added to each occurrence time stored in the correction time, and an equalization signal output means for outputting an equalization signal at each correction time calculated by the correction time calculation means; Reproduction signal processing apparatus having a characterized by comprising.

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