JP2006216616A - Semiconductor device and manufacturing method thereof, and solid-state image pickup element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device containing a solid-state image pickup element for forming a mask on a region exceeding the limit of mask fining, reducing the number of processes, and improving reliability, and also to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device has an element separation region 23 by an impurity region, and a mask 29 for obstructing ion implantation remains on the element separation region 23. A mask 29 for obstructing ion implantation is formed with the component of a semiconductor element, for example with the same configuration as a gate control section 25 in a MOS transistor. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a semiconductor region is formed by ion implantation and a manufacturing method thereof, and a solid-state imaging device in which a source / drain region of a MOS transistor of a pixel is formed by ion implantation and a manufacturing method thereof.

  In a semiconductor device such as a semiconductor integrated circuit, when the semiconductor region is formed by ion implantation, a resist mask is usually used as a mask for ion implantation. The resist mask is formed by coating and forming a photoresist film on a semiconductor substrate, exposing the photoresist film to a pattern to be a mask, and developing it. This resist mask pattern has a fine pattern limit depending on the light source used for exposure. If the fine pattern exceeds this limit, a sufficient function as a mask cannot be obtained, and a highly accurate semiconductor device cannot be manufactured.

  In particular, in a CMOS solid-state imaging device, the layout of the MOS transistor that constitutes the pixel together with the photoelectric conversion unit takes a layout that does not exist in a normal MOS integrated circuit. Therefore, this resist mask serving as an ion implantation mask is a factor of design rule restriction. It is one of.

  Patent Document 1 proposes a technique in which in the CMOS solid-state imaging device, the element isolation portion is formed in an insulating film formed on the semiconductor substrate so as not to erode the semiconductor substrate as the element isolation portion.

JP 2002-270808 A

  FIGS. 11A and 11B show an example of a semiconductor integrated circuit having a MOS transistor in which an element isolation region is formed by an impurity region by ion implantation. In the semiconductor integrated circuit 1, an element isolation region 3 is formed by a p-type impurity region on the surface side of a first conductivity type, for example, a p-type semiconductor substrate 2, and the two regions surrounded by the element isolation region 3 are formed. MOS transistors Tr1 and Tr2 each having an n-type source / drain region 4 and a gate control unit 5 comprising a gate insulating film 6, a gate electrode 7 and a sidewall 8 are formed.

  When forming the source / drain region 4 of such a semiconductor integrated circuit 1, after forming the element isolation region 3 and the gate controller 5, a resist mask 9 indicated by a chain line on the substrate corresponding to the element isolation region 3. The n-type source / drain regions 4 are formed in a self-aligned manner by ion-implanting n-type impurities using the resist mask 9 and the gate controller 5 as a mask.

  By the way, in the semiconductor integrated circuit having the element isolation region by the impurity region as described above, with the miniaturization and high integration, when ion implantation is performed outside the element isolation region, such as formation of the source / drain region 4, Due to the miniaturization of resist mask 9 serving as an ion implantation mask shown in FIG. 11 and the limit of accuracy, ions are implanted into element isolation region 4, causing the element isolation region to collapse or the function of the element isolation region to deteriorate, resulting in a decrease in yield. It becomes a factor to lower. For example, in FIG. 11, if the distance d1 between the adjacent MOS transistors Tr1 and Tr2 becomes narrower, the resolution limit of the exposure and development of the photoresist film is exceeded, so that high-precision patterning cannot be performed and a high-precision resist mask is obtained. Cannot be formed. That is, there is a limit to the miniaturization and accuracy of the mask depending on the light source used for exposure. For this reason, the mask displacement of the resist mask or the mask itself may not be formed at the time of ion implantation of the source / drain region, and some impurities enter the element isolation region 4 to cause the element isolation collapse and the function deterioration. There is a risk of causing it.

  On the other hand, in a CMOS solid-state imaging device, with the miniaturization and high integration of pixels, when forming MOS transistors in the pixels, miniaturization and mask accuracy of the ion implantation blocking mask as described with reference to FIGS. From this limit, the element isolation region collapses and the function decreases, resulting in a decrease in yield.

  In view of the above-described points, the present invention makes it possible to form a mask on a region exceeding the limit of mask miniaturization, reduce the number of processes, and improve the reliability of the semiconductor device, its manufacturing method, and A solid-state imaging device and a manufacturing method thereof are provided.

  A semiconductor device according to the present invention has an element isolation region by an impurity region, and an ion implantation blocking mask remains on the element isolation region.

  The ion implantation blocking mask is preferably formed in the same configuration as the components of the semiconductor element formed in the other part.

The ion implantation blocking mask is preferably formed in the same configuration as the gate control unit of the MOS transistor formed in the other part.
When the ion implantation blocking mask is formed separately from the gate control portion of the MOS transistor formed in the other part, the ion implantation blocking mask has a required potential for enhancing the isolation capability of the element isolation region. It is preferable to apply.

  The ion implantation blocking mask can be formed of an insulating film having a thickness sufficient to block ion implantation.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation region by an impurity region in a semiconductor substrate, and an ion having the same configuration as a component of a semiconductor element formed in another part of the semiconductor substrate on the element isolation region. The method includes a step of forming an implantation blocking mask and a step of forming a semiconductor region of a required conductivity type by ion implantation in a required region of the semiconductor substrate using the ion implantation blocking mask.

It is preferable to simultaneously form the ion implantation blocking mask on the element isolation region and the component of the semiconductor element in the same process.
The ion implantation blocking mask on the element isolation region is preferably formed with the same configuration as the gate control unit of the MOS transistor formed on the other part of the semiconductor substrate.

  A method of manufacturing a semiconductor device according to the present invention includes: a step of forming an element isolation region by an impurity region on a semiconductor substrate; and an ion implantation preventive layer with an insulating film having a thickness sufficient to prevent ion implantation on the element isolation region. The method includes a step of forming a mask and a step of forming a semiconductor region of a required conductivity type by ion implantation in a required region of the semiconductor substrate using an ion implantation blocking mask.

  In the solid-state imaging device according to the present invention, a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged, the pixels are separated from each other by an element isolation region by an impurity region, and the same as the gate control unit of the MOS transistor on the element isolation region A mask for preventing ion implantation according to the structure remains.

As the ion implantation blocking mask, when formed separately from the gate controller of the MOS transistor, it is preferable to apply a required potential for enhancing the element isolation capability of the element isolation region to the ion implantation blocking mask. .
As an ion implantation blocking mask, it is preferable to apply a required potential for enhancing blooming resistance.

  In the solid-state imaging device according to the present invention, a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged, and the pixels are separated from each other by an element isolation region by an impurity region, which is sufficient to prevent ion implantation on the element isolation region. A mask for preventing ion implantation by an insulating film having a film thickness remains.

  A method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device in which a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged, and an element isolation region is formed by an impurity region on a semiconductor substrate. A step of forming a gate control unit and an ion implantation blocking mask having the same configuration as the gate control unit on the MOS transistor forming region and the element isolation region of the semiconductor substrate, and the gate control unit and the ion implantation blocking step, respectively. And a step of forming source / drain regions of the MOS transistor by ion implantation using the mask as a mask.

  It is preferable that the ion implantation blocking mask on the element isolation region and the gate control part of the MOS transistor are simultaneously formed in the same process.

  A method for manufacturing a solid-state imaging device according to the present invention is a method for manufacturing a solid-state imaging device in which a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged, and an element isolation region is formed by an impurity region on a semiconductor substrate. A step of forming an ion implantation blocking mask with an insulating film having a thickness sufficient to prevent ion implantation on the element isolation region of the semiconductor substrate; a gate control unit of the MOS transistor and an ion implantation blocking mask; And a step of forming source / drain regions of the MOS transistor by ion implantation using as a mask.

  According to the semiconductor device of the present invention, since the element isolation region is formed by the impurity region, the element isolation region can be miniaturized. By adopting a configuration in which the ion implantation blocking mask remains on the element isolation region, a process for removing the ion implantation blocking mask is omitted, and a semiconductor device capable of reducing the number of manufacturing steps can be provided.

  By forming the ion implantation blocking mask with the same configuration as the components of the semiconductor elements formed in other parts, the ion implantation blocking is further refined beyond the limit of miniaturization as in conventional resist masks. The mask can be formed.

By forming the ion implantation blocking mask with the same configuration as that of the gate control part of the MOS transistor formed in the other part, the mask can be further refined and sufficiently exceeded the limit of miniaturization as in the conventional resist mask. An ion implantation blocking mask having ion implantation blocking capability can be formed. When this ion implantation blocking mask is formed separately from the gate control part of the MOS transistor formed in the other part, the required potential is applied to the ion implantation blocking mask, so that the impurity in the element isolation region immediately below is applied. However, it is possible to enhance the element isolation capability.
When forming a mask for ion implantation prevention by extending the gate control part of the MOS transistor over the element isolation region, the fine element isolation region adjacent to the gate control part is surely covered with the mask for ion implantation prevention. Can do.

  As described above, by providing the ion implantation blocking mask according to the present invention, it is possible to provide a highly reliable semiconductor device without causing destruction of the element isolation region or deterioration of the function.

  By forming the ion implantation blocking mask with an insulating film having a thickness sufficient to prevent ion implantation, the ion implantation blocking mask is further miniaturized beyond the limit of miniaturization as in conventional resist masks. Can be formed.

  According to the method for manufacturing a semiconductor device according to the present invention, a miniaturized element isolation region can be formed by forming an element isolation region from an impurity region. By forming an ion implantation blocking mask with the same configuration as the components of the semiconductor element formed in the other part on this element isolation region, it is further miniaturized beyond the limit of miniaturization as in the conventional resist mask. An ion implantation blocking mask can be formed. In addition, since the ion implantation blocking mask is formed with the same configuration as the constituent elements of the semiconductor element, the process can be simplified.

By forming the mask for ion implantation prevention with the same structure as the gate control part of the MOS transistor which is formed on the other part of the semiconductor substrate, the ion mask is further miniaturized beyond the limit of miniaturization by resist mask and sufficient ion implantation prevention An ion implantation blocking mask having the capability can be formed. Further, the positional deviation of the ion implantation blocking mask hardly occurs, so that it is possible to avoid a reduction in the isolation capability of the element isolation region caused by the mask deviation. Simplification of the process can be achieved.
When forming an ion implantation blocking mask at the extension of the gate control section of the MOS transistor formed on the other part of the semiconductor substrate, the ion implantation blocking mask is easily formed on a fine element isolation region adjacent to the gate control. can do.

  Although the ion implantation blocking mask of the present invention and a conventional resist mask can be used in combination, the resist mask is not necessary depending on the layout, and the process can be reduced.

  According to the method of manufacturing a semiconductor device according to the present invention, since the step of forming an ion implantation blocking mask with an insulating film having a thickness sufficient to block ion implantation in the element isolation region is provided, the resist mask can be miniaturized. It is possible to form a fine ion implantation blocking mask exceeding the limit of the above. In addition, the process can be simplified.

  In the method of manufacturing a semiconductor device according to the present invention, by providing the above-described ion implantation blocking mask, a highly reliable semiconductor device can be manufactured without causing destruction of the element isolation region and a decrease in function.

  According to the solid-state imaging device according to the present invention, since the element isolation region is formed of the normal region, the element isolation region can be miniaturized, and the pixel is isolated by the element isolation region by the impurity region. Therefore, high integration of pixels can be achieved. Since the ion implantation blocking mask having the same configuration as that of the gate control unit of the pixel MOS transistor is formed on the element isolation region, a fine ion implantation blocking mask exceeding the limit of the resist mask can be realized. Moreover, impurity ion implantation does not penetrate into the element isolation region during ion implantation of the source / drain regions, and the isolation capability of the element isolation region can be maintained. Since the ion implantation blocking mask is finally left, the step of removing the ion implantation blocking mask is omitted, and a CMOS solid-state imaging device capable of reducing the manufacturing process can be provided.

  Thus, by having the ion implantation blocking mask according to the present invention, it is possible to provide a highly reliable solid-state imaging device without causing destruction of the device isolation region or deterioration of the function.

When this ion implantation blocking mask is formed separately from the gate controller in the pixel MOS transistor, the impurity in the element isolation region immediately below is made higher in concentration by applying the required potential to the ion implantation blocking mask. Thus, the element isolation capability can be enhanced. Along with this, it is possible to reinforce the suppression of dark current by recombining charges boiling from the interface of the element isolation region due to the impurity region.
When forming a mask for ion implantation prevention by extending the gate control part of the MOS transistor over the element isolation region, the fine element isolation region adjacent to the gate control part is surely covered with the mask for ion implantation prevention. Can do.

  By applying a required potential to the ion implantation blocking mask, the potential immediately below the ion implantation blocking mask can be controlled, and blooming resistance can be enhanced.

  By forming the ion implantation blocking mask with an insulating film having a thickness sufficient to prevent ion implantation, the ion implantation blocking mask is further miniaturized beyond the limit of miniaturization as in conventional resist masks. Can be formed.

  According to the method for manufacturing a CMOS solid-state imaging device according to the present invention, it is possible to form a miniaturized device isolation region by forming the device isolation region between pixels as an impurity region. By forming an ion implantation blocking mask having the same configuration as that of the gate control unit of the pixel MOS transistor on the element isolation region, the ions can be further miniaturized beyond the limit of miniaturization as in a conventional resist mask. An implantation blocking mask can be formed. Further, since the ion implantation blocking mask is formed with the same configuration as that of the gate controller, the process can be simplified.

  In the method for manufacturing a solid-state imaging device according to the present invention, by having the above-described ion implantation blocking mask, it is possible to manufacture a highly reliable solid-state imaging device without causing destruction of the element isolation region or deterioration of function. it can.

By simultaneously forming the ion implantation blocking mask on the element isolation region and the gate control portion of the pixel MOS transistor in the same process, the process can be simplified.
By forming the ion implantation blocking mask separately from the gate controller, a required potential can be applied to the ion implantation blocking mask after completion, and the isolation capability of the element isolation region can be further improved. .
By forming the ion implantation blocking mask by the extension of the gate control unit, the ion implantation blocking mask can be reliably covered on the miniaturized element isolation region adjacent to the gate control unit.

  As an ion implantation blocking mask, the ion implantation blocking mask according to the present invention and a conventional resist mask can be used in combination. However, depending on the layout, the resist mask becomes unnecessary, and the process can be reduced accordingly. it can.

  By providing an ion implantation prevention mask with an insulating film having a sufficient thickness to prevent ion implantation on the element isolation region, the limit of miniaturization as in the case of conventional resist masks can be achieved, similar to the configuration of the gate control unit. It is possible to form an ion implantation blocking mask that is more minute than that, and to reduce the number of processes and provide a highly reliable solid-state imaging device.

  According to the method for manufacturing a CMO solid-state imaging device according to the present invention, since the process for forming an ion implantation blocking mask with an insulating film having a film thickness sufficient to block ion implantation is formed in the element isolation region, Therefore, it is possible to form a fine ion implantation blocking mask that exceeds the limit of fabrication. In addition, the process can be simplified.

  Embodiments of the present invention will be described below with reference to the drawings.

1A to 1C show an embodiment of a semiconductor device according to the present invention. This embodiment is an example applied to a semiconductor integrated circuit having a MOS transistor.
In the semiconductor device 21 according to the present embodiment, an element isolation region 23 is formed by a p-type impurity region having the same conductivity type and higher concentration than the substrate concentration on one main surface of the first conductivity type and p-type semiconductor substrate 22. Each of the two regions surrounded by the element isolation region 23 includes an n-type source / drain region 24, a gate insulating film 26, for example, a gate electrode 27 made of polysilicon, and an insulating film formed on the side wall of the gate electrode 27. N-channel type MOS transistors Tr1 and Tr2 having a gate control unit 25 including a sidewall 28 are formed, and an ion implantation blocking mask 29 is left on the substrate corresponding to the element isolation region 23. .

  The ion implantation blocking mask 29 is formed with the same configuration as the components of the semiconductor element formed on the substrate 22. In other words, in the present embodiment, the ion implantation blocking mask 29 is formed by the configuration including the gate insulating film 26, the gate electrode 27, and the sidewalls 28 having the same configuration as the gate control unit 25 of the MOS transistors Tr1 and Tr2.

  The ion implantation blocking mask 29 is formed separately from the gate control section 25 of the MOS transistors Tr1 and Tr2. Further, as shown in FIG. 1C, in part of the element isolation region 23, that is, in a narrow region 31 (see FIG. 1A) between the ion implantation blocking mask 29 and the gate control unit 25, ion implantation blocking is performed. The side wall 26 on the mask 29 side and the side wall 26 on the gate control unit 25 side are embedded so as to protrude from both sides and are in close contact with each other, and the ion implantation blocking mask 29 is configured only by the side wall 26. By burying only the sidewalls 26, the penetration of impurity ions during ion implantation does not occur.

  The ion implantation blocking mask 29 can be formed simultaneously in the same process as the gate control unit 25 of the MOS transistors Tr1 and Tr2. In addition, although each gate control part 25 and the mask 29 for ion implantation prevention can also be formed in a different process, simultaneous formation is preferable from the simplification of a process. The source / drain regions 24 of the MOS transistors Tr1, Tr2 are formed by ion-implanting n-type impurities using the gate controller 25 and the ion implantation blocking mask 29 as a mask. In this ion implantation, an ion implantation blocking mask 29 having the same configuration as that of the gate controller 25 is formed on the element isolation region 23, so that impurities cannot penetrate the ion implantation blocking mask 29 and enter the element isolation region 23. Absent.

In FIG. 1, the gate lengths of the MOS transistors Tr1 and Tr2 and the gate length of the element isolation region 23 are the same. However, depending on the generation, for example, when further miniaturization is performed, the gate length of the element isolation region 23 having the gate length of the MOS transistors Tr1 and Tr2 may be shortened.
In addition to the above example, for example, a silicon oxide film or a silicon nitride film formed in a separate process can be applied as the same configuration as the constituent elements of the semiconductor element that becomes the ion implantation blocking mask 29.

  According to the semiconductor device 21 of the present embodiment, the ion implantation blocking mask 29 having the same configuration as that of the gate controller 25 is formed on the element isolation region 23, whereby the source / drain regions 24 of the MOS transistors Tr1 and Tr2 are formed. Is formed by ion implantation, the impurity is not implanted into the element isolation region 23. For this reason, the isolation capability of the element isolation region 23 can be maintained. As a result, the element isolation region 23 is not destroyed or reduced in function.

  In particular, when the width of the element isolation region 23 between adjacent MOS transistors Tr1 and Tr2 in FIG. Can be formed. Since the ion implantation blocking mask 29 has the same configuration as that of the gate control unit, the mask 29 can have sufficient capability to block ion implantation, and mask displacement does not occur. Accordingly, it is possible to prevent a decrease in element isolation capability caused by mask displacement as in the case of a conventional resist mask.

  In addition, since the ion implantation blocking mask 29 is finally left in the semiconductor device, the process of removing the ion implantation blocking mask 29 is omitted, and the manufacturing process can be simplified. As an ion implantation blocking mask in manufacturing a semiconductor device, an ion implantation blocking mask 29 having the same configuration as that of the gate control unit of the present embodiment and an ion implantation blocking mask using a conventional resist mask can be used in combination. . However, depending on the layout, an ion implantation blocking mask using a resist mask can be dispensed with, and the number of processes can be reduced accordingly.

  In the present embodiment, the gate electrode 27 constituting the ion implantation blocking mask 29 has a required potential for enhancing the element isolation capability of the element isolation region 23. In this example, the element isolation region 23 is a p-type impurity region. Since it is formed, a negative voltage can be applied. By applying a negative voltage, the surface side of the p-type impurity region of the element isolation region 29 is made p-type and highly concentrated, and the element isolation capability is enhanced.

  2A and 2B show another embodiment of the semiconductor device according to the present invention. The semiconductor device 33 according to the present embodiment is configured by extending the gate control section 25 of the MOS transistor Tr1 to the element isolation region 23, and forming an ion implantation blocking mask 29 with the extended section. The parts corresponding to those in FIG.

  Also in the semiconductor device 33 according to the present embodiment, the ion implantation blocking mask 29 having the same configuration as that of the gate control unit 25 of the MOS transistor Tr1 is formed on the region corresponding to the element isolation region 33, and therefore has been described with reference to FIG. Similarly to the above, it is possible to form an ion implantation blocking mask on a fine region, and to prevent a decrease in element isolation capability caused by mask displacement. In addition, the process can be reduced.

  Here, when the MOS transistor Tr1 is turned on, a positive voltage is applied to the gate electrode 27 in this example. At this time, a positive voltage is also applied to the gate electrode 27 on the ion implantation blocking mask 29 side, and the p-type element isolation region 23 immediately below the ion implantation blocking mask 29 becomes n-type. If the p-type impurity concentration of 23 is sufficiently high, the element isolation capability can be maintained.

  Furthermore, as another embodiment, as shown in FIG. 3, the gate electrode 27 is extended so as to extend over a part of the element isolation region 23, and the side wall 28 is formed in the remaining part to form ions. It is also possible to form an implantation prevention mask 29.

FIG. 4 shows still another embodiment of the semiconductor device according to the present invention.
In the semiconductor device 36 according to the present embodiment, an insulating film, for example, an oxide film formed in the step of forming the element isolation region 23 is formed with a film thickness sufficient to prevent ion implantation, and this insulating film is used as an ion implantation blocking mask. 39, and is configured so that the ion implantation blocking mask 39 finally remains. For example, when the element isolation region is formed of an impurity diffusion region and a silicon oxide film thereon, this silicon oxide film is formed sufficiently thick to prevent ion implantation, and this silicon oxide film is formed into an ion implantation blocking mask 39. Can be used as Since other configurations are the same as those in FIG. 1, the same reference numerals are given to corresponding portions, and redundant description is omitted.

  According to the semiconductor device 39 of the present embodiment, since an insulating film having a film thickness sufficient to block ion implantation is used as the ion implantation blocking mask 39, the MOS transistors Tr1, Tr2 are the same as described with reference to FIG. When the source / drain regions 24 are formed by ion implantation, no impurity ions are implanted into the element isolation region 23. For this reason, the isolation capability of the element isolation region 23 can be maintained.

  Even when the width of the element isolation region 23 between the adjacent MOS transistors Tr1 and Tr2 is narrow enough to exceed the limit of miniaturization of the resist mask, the ion implantation blocking mask can be formed. Since the ion implantation blocking mask 39 is configured using an insulating film formed in the process of forming the element isolation region 23, mask displacement does not occur. Accordingly, it is possible to prevent a decrease in element isolation capability caused by mask displacement as in the case of a conventional resist mask.

  In addition, since the ion implantation blocking mask 39 is finally left in the semiconductor device, the step of removing the ion implantation blocking mask 39 is omitted, and the manufacturing process can be simplified. As the ion implantation blocking mask, the ion implantation blocking mask 39 of the present embodiment can be used in combination with a conventional ion implantation blocking mask using a resist mask.

  In the embodiment of FIG. 1 described above, the ion implantation blocking mask 29 is formed in the same configuration as the gate control unit 25 of the MOS transistors Tr1 and Tr2, but the other components of the semiconductor element formed on the semiconductor substrate 22 It can also be formed with the same structure. In this case, in order to reduce the number of processes, it is desirable to simultaneously form an ion implantation blocking mask in the same process as the formation of the components of the semiconductor element.

  In the above example, the case where the source / drain regions are formed by ion implantation through the ion implantation blocking mask has been described. However, the present invention provides other semiconductor regions by ion implantation through the ion implantation blocking mask. The present invention can also be applied when formed and configured.

  Next, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. The present embodiment is a manufacturing method applied to the manufacturing of the semiconductor device shown in FIG.

  First, as shown in FIG. 5A, a first conductivity type, for example, p-type silicon semiconductor substrate 22 is provided, and a p-type impurity 42, for example, boron (B) is formed on one main surface of the semiconductor substrate 22 through a resist mask 41. ) Is implanted to form an element isolation region 23 by p-type impurities.

  Next, as shown in FIG. 5B, a gate insulating film 26 and, for example, a polysilicon film 43 to be a gate electrode are formed on the entire main surface of the semiconductor substrate 22.

  Next, as shown in FIG. 5C, the gate insulating film 26 and the polysilicon film 43 are patterned through a resist mask (not shown), and the gate insulating films are respectively formed on the two regions surrounded by the element isolation regions 23. 26 and a gate electrode 27 thereon, and a gate insulating film 26 and a gate electrode 27 are formed in a region corresponding to the element isolation region 23 where an ion implantation blocking mask is to be formed.

  Next, as shown in FIG. 6D, an insulating film 44 such as a silicon oxide film is formed on the entire surface of the substrate so as to cover the gate electrode 27 by, for example, a CVD (chemical vapor deposition) method.

  Next, the insulating film 44 is etched back to form sidewalls 28 made of the insulating film 44 on the side surfaces of the gate electrode 27 as shown in FIG. 6E. That is, in the element isolation region 23, the gate control unit 25 is formed by the gate insulating film 26, the gate electrode 27, and the sidewall 28. On the element isolation region 23, a gate insulating film 26 having the same configuration as the gate control unit 25, a gate electrode 27, and an ion implantation blocking mask 29 by a sidewall 28 are formed.

  Next, as shown in FIG. 6F, n-type source / drain regions 24 are formed by implanting n-type impurities 45, for example, phosphorus (P) ions, using the gate controller 25 and the ion implantation blocking mask 29 as a mask. . Thus, the semiconductor device 21 having the target MOS transistors Tr1 and Tr2 is obtained.

  In the manufacturing method described above, the gate control unit 25 and the ion implantation blocking mask 29 can be patterned in the patterning step shown in FIG. 6E. Further, the gate control unit 25 and the ion implantation blocking mask 29 can be patterned so as to be continuous integrally.

  According to the manufacturing method of the semiconductor device according to the present embodiment, the ion implantation blocking mask 29 on the element isolation region 23 has the same configuration as the gate controller 25 of the MOS transistor, that is, the gate insulating film 26, the gate electrode 27, and the side. By forming the wall 28, a highly reliable ion implantation blocking mask can be formed. Further, the ion implantation blocking mask 29 can be formed in a region exceeding the limit of miniaturization of the conventional resist mask. That is, even when the element isolation region 23 is miniaturized and the ion implantation blocking mask 29 is also miniaturized, a sufficiently reliable ion implantation blocking mask can be formed. Since the gate controller 25 is formed at the same time as the gate controller 25, the position of the ion implantation blocking mask 29 is not displaced. Therefore, in the ion implantation process of the source / drain region of FIG. 6F, n-type impurities do not penetrate into the p-type element isolation region 23, and the element isolation capability of the element isolation region 23 does not deteriorate. A highly reliable semiconductor device in which the element isolation region 23 is not broken and its function is not degraded can be manufactured.

  Ultimately, the ion implantation blocking mask 29 is left without being removed, so that the ion implantation blocking mask removal step is omitted, and the number of steps can be reduced accordingly. Although not shown, the ion implantation blocking mask 29 of the present embodiment can be used in combination with the resist mask in other parts as an ion implantation blocking mask, but depending on the layout of the ion implantation blocking mask. In the case where a resist mask is unnecessary, the number of processes can be further reduced.

As another embodiment of the method for manufacturing a semiconductor device of the present invention, an ion implantation blocking mask can be formed of the insulating film 39 shown in FIG. The insulating film 39 is formed by thickly forming an insulating film, for example, a silicon oxide film, formed in the step of forming the element isolation region 23. The steps after the formation of the ion implantation blocking mask 39 are the same as described above.
Also in the manufacturing method of the semiconductor device of the present embodiment, it is possible to form an ion implantation blocking mask in a region beyond the limit of resist miniaturization. Further, it is possible to prevent a reduction in the isolation capability of the element isolation region 23 caused by mask displacement. Furthermore, the process can be reduced.

The ion implantation blocking mask according to the present embodiment described above can be applied to a CMOS solid-state imaging device. FIG. 7 shows an embodiment of the layout of the pixel region in the CMOS solid-state imaging device according to the present invention.
In the CMOS solid-state imaging device 51 of the present embodiment, a unit pixel 52 [52A, 52B, 52C, 52D] is formed by a photoresist PD serving as a photoelectric conversion unit and a plurality of MOS transistors. Arranged regularly, for example, arranged in a matrix. The unit pixel 52 includes, for example, one photodiode PD and three MOS transistors, that is, a transfer transistor, a reset transistor, and an amplification transistor. The transfer transistor Tr4 is formed of a charge storage region of the photodiode PD, a source / drain region 54 to be a floating diffusion (FD), and a transfer gate electrode 55 formed through a gate insulating film. The reset transistor Tr5 is formed of a pair of source / drain regions 54 and 56 and a reset gate electrode 57 formed through a gate insulating film. The amplifying transistor Tr6 is formed of source / drain regions 56 and 58 and a gate electrode 59 formed through a gate insulating film. A vertical signal line 60 is connected to one source / drain region 58 of the amplifying transistor Tr6 of each pixel arranged in the vertical direction, and a power source for supplying a power supply voltage Vdd to one source / drain region 56 of the reset transistor Tr5. Line 61 is connected. Each pixel 52 [52A, 52B. 52C, 52D] are separated from each other by an element isolation region 63 indicated by hatching.

  In the CMOS solid-state imaging device 51 according to the present embodiment, the element isolation region 63 is formed of a required conductivity type, for example, a p-type impurity region, and the MOS transistor Tr4 is formed on the entire region of the element isolation region 63 or on the required region. An ion implantation blocking mask having the same structure as that of the gate control section (consisting of a gate insulating film, a gate electrode, a sidewall, etc.) in .about.Tr6 is formed. In this case, the ion implantation blocking mask may be formed separately from the gate control portions of the MOS transistors Tr4 to Tr6. Alternatively, an ion implantation blocking mask may be formed integrally and continuously with a required MOS transistor gate controller.

In this example, as shown in FIG. 7, the gate controller (only the gate electrode 59 is shown) of the amplification transistor Tr6 is connected to the source / drain region 58 of the amplification transistor Tr6 of the adjacent pixel and the source / drain region of the transfer transistor Tr4. A U-shape including the gate control portion is extended on the element isolation region 63 so as to be positioned between the drain regions 54 (fd), and this extension portion is configured as an ion implantation blocking mask 64. In this case, an ion implantation blocking mask such as an insulating film such as a silicon oxide film or a silicon nitride film or a conventional resist mask can be formed on the other element isolation region 63. Using this ion implantation blocking mask, the gate controller of the MOS transistor, and the resist mask covering the photodiode PD as a mask, the second conductivity type, for example, n-type source / drain regions 54, 57, 58 of each MOS transistor are ionized. Form by injection. Further, a semiconductor region of a required conductivity type constituting the photodiode PD is formed by ion implantation using the ion implantation blocking mask, a resist mask covering the MOS transistor, and the gate control portion of the transfer transistor Tr6 as a mask.

  According to the CMOS solid-state imaging device 51 according to the present embodiment, the gate control unit of the amplification transistor Tr6 and the gate control unit of the amplification transistor Tr6 are formed in a U shape as viewed from above on the element isolation region 63 adjacent to the source / drain region 58 of the amplification transistor Tr6. By forming the ion implantation blocking mask 64 having the same configuration, when the source / drain region 58 is formed by ion implantation, impurities are not ion-implanted in the element isolation region 63. For this reason, the isolation capability of the element isolation region 63 can be maintained.

  By using this technique, element isolation can be formed while ensuring an ion implantation margin in the source / drain regions. This effect is not limited to the configuration in which the gate control unit of the amplification transistor is extended, and the same effect can be obtained in the ion implantation blocking masks of the embodiments shown in FIGS.

  In particular, when the width of the element isolation region 63 between the pixels is narrowed with the miniaturization and high integration of the pixels, that is, when the width of the resist isolation mask exceeds the limit of the miniaturization of the resist mask, Can be formed. Since the ion implantation blocking mask has the same configuration as that of the gate control unit, the mask can be given sufficient ability to block ion implantation, and mask displacement does not occur. Accordingly, it is possible to prevent a decrease in element isolation capability caused by mask displacement as in the case of a conventional resist mask.

  In addition, since the ion implantation blocking mask is finally left in the CMOS solid-state imaging device, the step of removing the ion implantation blocking mask is omitted, and the manufacturing process can be simplified. As an ion implantation blocking mask for manufacturing a CMOS solid-state imaging device, an ion implantation blocking mask having the same configuration as that of the gate control unit of the present embodiment and an ion implantation blocking mask using a conventional resist mask may be used in combination. it can. However, depending on the layout, an ion implantation blocking mask using a resist mask can be eliminated, and the number of processes can be reduced accordingly.

  When the ion implantation blocking mask 64 is formed separately from the gate control portions of the MOS transistors Tr4 to Tr6, the gate electrode of the ion implantation blocking mask 64 is required to enhance the isolation capability of the element isolation region 63. Since the element isolation region 63 is formed of a p-type impurity region in this example, a negative voltage can be applied. When a negative voltage is applied to the gate electrode of the ion implantation blocking mask 64, element isolation as described above can be enhanced, and the p-type impurity concentration at the interface of the element isolation region 63 is increased. , Dark current suppression can be enhanced.

FIG. 8 shows another embodiment of the layout of the pixel region in the CMOS solid-state imaging device according to the present invention. In the CMOS solid-state imaging device 65 of the present embodiment, the element isolation region 63 is formed of a required conductivity type, for example, a p-type impurity region, and other MOSs except for the reset transistor Tr5 are formed on the entire region of the element isolation region 63. An ion implantation blocking mask 64 having the same configuration as that of the gate controller in the transistors Tr4 and Tr6 is formed. In this case, the ion implantation blocking mask 64 is divided and formed so as to extend from the gate control portions (only the gate electrodes 55, 57, 59 are shown in the figure) of the corresponding MOS transistors Tr4, Tr6.
Since the other configuration is the same as that of FIG. 7 described above, the same reference numeral is given to the corresponding portion, and the duplicate description is omitted.

According to the CMOS solid-state imaging device 65 of the present embodiment, the ion implantation blocking mask 64 having the same configuration as the gate control unit of the MOS transistors Tr4 and tr6 is formed on the entire region of the element isolation region 63. When the drain region 58 is formed by ion implantation, or when the semiconductor region of the required conductivity type of the photodiode PD is formed, no impurity is ion-implanted into the element isolation region 63. For this reason, the isolation capability of the element isolation region 63 can be maintained.
By extending the gate control unit on almost all the element isolation regions 63 around the pixel, the reliability of element isolation can be improved. Here, the reason why the gate control unit of the reset transistor Tr5 is not extended on the element isolation region is that when the gate control unit of the reset transistor Tr5 is extended on the element isolation region, element isolation is guaranteed, but the power supply voltage is applied to the gate. Is applied, so that the isolation capability of the surface of the p + element isolation region immediately below is weakened. On the other hand, the voltage applied to the gate of the amplification transistor Tr6 is weaker than that of other transistors. In addition, when a voltage is applied to the transfer transistor Tr4, there is a way for electrons to escape to the floating diffusion region FD, so that the influence on other pixels is small.
In addition, the same effects as described in the CMOS solid-state image sensor of FIG.

FIG. 9 shows still another embodiment of the layout of the pixel region in the CMOS solid-state imaging device according to the present invention. In the CMOS solid-state imaging device 67 of the present embodiment, the element isolation region 63 is formed of a required conductivity type, for example, a p-type impurity region, and gate control is performed on the MOS transistors Tr4 to Tr6 over the entire region of the element isolation region 63. An ion implantation blocking mask 64 having the same configuration as that of the portion is formed. In this case, the ion implantation blocking mask 64 is formed so as to extend from the gate control portion (only the gate electrode 55 is shown in the figure) of the transfer transistor Tr4, and is divided for each pixel.
Since the other configuration is the same as that of FIG.

According to the CMOS solid-state imaging device 67 of the present embodiment, the source / drain region is formed by forming the ion implantation blocking mask 64 having the same configuration as the gate control unit of the transfer transistor Tr4 over the entire element isolation region 63. When forming 58 by ion implantation or when forming a semiconductor region of the required conductivity type of the photodiode PD, no impurity is ion-implanted into the element isolation region 63. For this reason, the isolation capability of the element isolation region 63 can be maintained.
By using the sul ion implantation blocking mask 64 disposed on the element isolation region 63 in common with the gate control unit of the transfer transistor Tr4, when a signal is accumulated in the floating diffusion region FD, a negative voltage is applied to the gate, Blooming resistance is enhanced.
In addition, the same effects as described in the CMOS solid-state image sensor of FIG.

FIG. 10 shows still another embodiment of the layout of the pixel region in the CMOS solid-state imaging device according to the present invention. In the CMOS solid-state imaging device 68 of the present embodiment, the element isolation region 63 is formed of a required conductivity type, for example, a p-type impurity region, and gate control is performed on the MOS transistors Tr4 to Tr6 over the entire region of the element isolation region 63. An ion implantation blocking mask 64 having the same configuration as that of the portion is formed. In this case, the ion implantation blocking mask 64 is formed separately from the gate controller of each of the MOS transistors Tr4 to Tr6.
Since other configurations are the same as those in FIG. 7 described above, the corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

According to the CMOS solid-state imaging device 68 of the present embodiment, the ion implantation blocking mask 64 having the same configuration as that of the gate control is provided on the entire region of the element isolation region 63 so as to be separated from the gate control units of the transistors Tr4 to Tr6. As a result, when the source / drain region 58 is formed by ion implantation, or when a semiconductor region of the required conductivity type of the photodiode PD is formed, impurities may be ion-implanted into the element isolation region 63. Absent. For this reason, the isolation capability of the element isolation region 63 can be maintained.
In FIG. 10, an ion implantation blocking mask 64 that does not belong to any gate control unit and has the same configuration as that of the gate control unit is disposed on the element isolation region 63, so that the ion implantation is always blocked regardless of the operation of the pixel. Since a voltage can be applied to the mask 64, blooming resistance can be further enhanced.
In addition, the same effects as described in the CMOS solid-state image sensor of FIG.

  The ion implantation blocking mask 64 in the CMOS solid-state imaging device according to the present invention is formed of an insulating film, a part of the element isolation region 63 is formed of only a sidewall, or the above-described semiconductor other than the gate control unit. The same configuration as described in the apparatus can be adopted.

In addition, the embodiment of the method for manufacturing a CMOS solid-state imaging device according to the present invention is performed with the same steps as the method for manufacturing a semiconductor device described above.
Also in the manufacturing method of the CMOS solid-state imaging device of the present embodiment, it is possible to form a miniaturized ion implantation blocking mask that accompanies miniaturization of the device isolation region, and in the ion implantation process of the source / drain region. The same effects as those of the semiconductor device manufacturing method described above can be achieved, such as a reduction in the isolation capability of the element isolation region and the reduction of the process.

A, B and C are a plan view showing an embodiment of a semiconductor device according to the present invention, a cross-sectional view taken along the line AA, and a cross-sectional view taken along the line BB. FIGS. 4A and 4B are a plan view of a main part showing another embodiment of an ion implantation blocking mask according to the present invention and a cross-sectional view thereof taken along the line CC. FIGS. It is sectional drawing which shows other embodiment of the mask for ion implantation prevention which concerns on this invention. A, B, and C are a plan view showing another embodiment of a semiconductor device according to the present invention, a sectional view taken along the line AA, and a sectional view taken along the line BB. 1A to 1C are manufacturing process diagrams (part 1) illustrating an embodiment of a method of manufacturing a semiconductor device according to the present invention. DF is a manufacturing process diagram (part 2) illustrating an embodiment of a method of manufacturing a semiconductor device according to the invention; It is a top view of the principal part which shows one Embodiment in the layout of the pixel area | region of the CMOS solid-state image sensor which concerns on this invention. It is a top view of the principal part which shows other embodiment in the layout of the pixel area | region of the CMOS solid-state image sensor which concerns on this invention. It is a top view of the principal part which shows other embodiment in the layout of the pixel area | region of the CMOS solid-state image sensor which concerns on this invention. It is a top view of the principal part which shows other embodiment in the layout of the pixel area | region of the CMOS solid-state image sensor which concerns on this invention. A and B are a plan view showing an example of a conventional semiconductor device and a cross-sectional view taken along the line AA.

Explanation of symbols

21..Semiconductor device, 22..Semiconductor substrate, 23..Element isolation region by impurity region, 24..Source / drain region, 25..Gate control unit, 26..Gate insulating film, 27..Gate electrode, 28..Sidewall, 29, 39 .. Mask for blocking ion implantation, Tr1, Tr2 ..MOS transistor, 51, 65, 67 ..CMOS solid-state imaging device, PD..Photodiode, Tr4 to Tr6 ..MOS transistor 52 [52A to 52D]... Pixel, 54... Source and drain regions (FD), 56, 58... Source and drain regions, 55, 57, 59. ..Power lines, 63 .. Element isolation regions, 64 .. Ion implantation blocking masks

Claims (30)

Having an element isolation region by an impurity region;
A semiconductor device, characterized in that an ion implantation blocking mask remains on the element isolation region. The semiconductor device according to claim 1, wherein the ion implantation blocking mask is formed with the same configuration as a component of a semiconductor element formed in another part. 2. The semiconductor according to claim 1, wherein the ion implantation blocking mask is formed separately from a gate control unit of a MOS transistor formed in another part and has the same configuration as the gate control unit. apparatus. The semiconductor device according to claim 1, wherein the ion implantation blocking mask is formed by an extension of a gate control unit of a MOS transistor formed in another part. 5. The semiconductor device according to claim 3, wherein a constituent member of the ion implantation blocking mask is formed of a gate insulating film, a gate electrode, and a sidewall. The semiconductor device according to claim 5, wherein at least a part of the element isolation region is formed by only the sidewall. The semiconductor device according to claim 3, wherein a necessary potential for enhancing the isolation capability of the element isolation region is applied to the ion implantation blocking mask. The semiconductor device according to claim 1, wherein the ion implantation blocking mask is formed of an insulating film having a thickness sufficient to block ion implantation. Forming an element isolation region by an impurity region in a semiconductor substrate;
Forming an ion implantation blocking mask having the same configuration as the component of the semiconductor element formed on the other part of the semiconductor substrate on the element isolation region;
And a step of forming a semiconductor region of a required conductivity type by ion implantation in the required region of the semiconductor substrate using the ion implantation blocking mask. The method for manufacturing a semiconductor device according to claim 9, wherein the ion implantation blocking mask on the element isolation region and the constituent elements of the semiconductor element are simultaneously formed in the same step. 10. The ion implantation blocking mask on the element isolation region is formed in the same configuration as the gate control unit by separating from a gate control unit of a MOS transistor formed on the other part of the semiconductor substrate. The manufacturing method of the semiconductor device of description. The method for manufacturing a semiconductor device according to claim 9, wherein the ion implantation blocking mask on the element isolation region is formed by an extension of a gate control unit of a MOS transistor formed on the other part of the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 11, wherein the gate control unit is formed of a gate insulating film, a gate electrode, and a sidewall. The method for manufacturing a semiconductor device according to claim 13, wherein at least a part of the element isolation region is covered only with the sidewall. Forming an element isolation region by an impurity region in a semiconductor substrate;
Forming an ion implantation blocking mask with an insulating film having a thickness sufficient to block ion implantation on the element isolation region;
And a step of forming a semiconductor region of a required conductivity type by ion implantation in the required region of the semiconductor substrate using the ion implantation blocking mask. A plurality of unit pixels composed of photoelectric conversion units and MOS transistors are arranged,
The pixels are separated from each other by an element isolation region by an impurity region;
A solid-state imaging device, wherein an ion implantation blocking mask having the same configuration as that of the gate controller of the MOS transistor remains on the device isolation region. The solid-state imaging device according to claim 16, wherein the ion implantation blocking mask is formed separately from a gate control unit of the MOS transistor. The solid-state imaging device according to claim 16, wherein the ion implantation blocking mask is formed by an extension of a gate control unit of the MOS transistor. The solid-state imaging device according to claim 17, wherein the ion implantation blocking mask is applied with a required potential for enhancing the isolation capability of the element isolation region. The solid-state imaging device according to claim 17, wherein a necessary potential for enhancing blooming resistance is applied to the ion implantation blocking mask. The solid-state imaging device according to claim 17 or 18, wherein the ion implantation blocking mask is formed of a gate insulating film, a gate electrode, and a sidewall. The solid-state imaging device according to claim 21, wherein only the sidewalls constituting the ion implantation blocking mask are formed on at least a part of the device isolation region. A plurality of unit pixels composed of photoelectric conversion units and MOS transistors are arranged,
The pixels are separated from each other by an element isolation region by an impurity region;
A solid-state imaging device, wherein an ion implantation blocking mask made of an insulating film having a film thickness sufficient to block ion implantation remains on the device isolation region. A method for manufacturing a solid-state imaging device in which a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged,
Forming an element isolation region by an impurity region in a semiconductor substrate;
Forming a gate control unit and an ion implantation blocking mask having the same configuration as the gate control unit on the MOS transistor formation region and the element isolation region of the semiconductor substrate, respectively.
Forming a source / drain region of the MOS transistor by ion implantation using the gate controller and the ion implantation blocking mask as a mask. The method for manufacturing a solid-state imaging device according to claim 24, wherein the ion implantation blocking mask on the device isolation region and the gate control unit of the MOS transistor are formed simultaneously in the same step. The method for manufacturing a solid-state imaging device according to claim 24, wherein the ion implantation blocking mask is formed separately from the gate control unit. The method of manufacturing a solid-state imaging device according to claim 24, wherein the ion implantation blocking mask is formed by an extension of the gate control unit. 28. The method of manufacturing a solid-state imaging device according to claim 26, wherein the gate control unit is formed of a gate insulating film, a gate electrode, and a sidewall. The method for manufacturing a solid-state imaging element according to claim 28, wherein at least a part of the element isolation region is covered only with the sidewall. A method for manufacturing a solid-state imaging device in which a plurality of unit pixels each including a photoelectric conversion unit and a MOS transistor are arranged,
Forming an element isolation region by an impurity region in a semiconductor substrate;
Forming an ion implantation blocking mask with an insulating film having a film thickness sufficient to block ion implantation on the element isolation region of the semiconductor substrate;
And a step of forming a source / drain region of the MOS transistor by ion implantation using the gate controller of the MOS transistor and the mask for blocking ion implantation as a mask.

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