JP2006211510A - Demodulation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse data demodulation device capable of judging pulse data following the change of pulse width characteristics due to the change of the characteristics of a communication module and a communication environment. <P>SOLUTION: The demodulation device comprises a counting circuit (3) for counting the pulse width of the pulse data; an arithmetic circuit (4) for analyzing the maximum value of the pulse width of a single pulse data stipulated by the packet format of the pulse data, and the minimum value of the pulse width of a double pulse data stipulated by the packet format respectively by a packet unit by using a counted value by the counting circuit, and for computing a judgement threshold for discriminating a single pulse and a double pulse on the basis of both analyzed results; and an adjustment circuit (5) for adjusting the pulse width of the pulse data following the double pulse data part and the single pulse data part to the width based on a prescribed standard, on the basis of the size relation of the counted value counted in the counting circuit and the judgement threshold computed in the arithmetic circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a demodulator used for demodulating pulse data modulated by PPM (Pulse Position Modulation), and relates to, for example, a technique effective when applied to infrared communication according to IrDA (Infrared Data Association) _FIR (Fast Infrared) standards.

  PPM modulation includes, for example, 4PPM modulation that defines four types of pulse positions in 2-bit units of data, and 16PPM modulation that defines 16 types of pulse positions in 4-bit units of data. In this PPM modulation, a state called a double pulse in which modulated pulses are adjacent to each other and a single pulse that is not adjacent to each other can occur. In demodulating the modulated pulse data, for example, the pulse position is detected by high level detection of the sampled pulse. At this time, if the PPM modulated pulse data is distorted on the receiving side and the pulse width is greatly extended, there is a possibility that an error may occur in the determination of the pulse position. On the other hand, in Patent Document 1, in 4PPM modulation, the synchronization of symbol positions for every four pulse slots is obtained, and when a plurality of pulse slot positions within the same symbol detected thereby are detected, the first detection position , There is a pulse slot position. In Patent Document 2, a phase correction circuit that switches a receivable pulse width range of a reception signal when a reception data error is detected is employed.

Japanese Patent No. 3307527 JP 2003-198482 A

  The present inventor has examined an error in determining a pulse position for PPM-modulated pulse data. For example, in the IrDA_FIR standard, the width of a single pulse is defined as 125 nsec (± 10 nsec) and the double pulse width is 250 nsec (± 10 nsec) in 4PPM modulated pulse data. However, even IrDA_FIR compatible infrared modules often do not satisfy this standard value for received pulses. It has been found by the present inventors that there are various forms of deviation from the standard value. For example, there are cases where the standard value always deviates from both the case where the pulse width deviates to the wide side and the case where it deviates to the narrow side. In some cases, the standard value deviates from the initial stage of reception. For example, during the preamble reception in the packet format of the reception pulse, there are cases where the reception pulse is not output for the initial several times, or the pulse width becomes extremely narrow even if the reception pulse is output. After that, there are cases where the pulse stabilizes and the pulse is output according to the standard value. Depending on the characteristics of the infrared module product and the communication environment, the pulse width does not meet the standard value irregularly even during the period after the pulse width has stabilized. There is a case. In this way, different signal characteristics are shown for each infrared module, so if some measure is not used on the receiving circuit side that performs demodulation, a single pulse is mistakenly recognized as a double pulse when a nonstandard pulse is received from the infrared module. For example, it is impossible to perform accurate reception, resulting in a communication error. In addition, when the infrared module product connected to the receiver circuit is different, it shows different electrical characteristics, and the receiver circuit can set the single pulse and double pulse discrimination range corresponding to the individual electrical characteristics of the product. It becomes necessary. For example, according to the electrical characteristics of the infrared light receiving module to be used, an individual discrimination range is set in advance by a microprocessor or the like so that a single pulse and a double pulse can be discriminated. Even in such a case, if a pulse deviating from the assumed determination range is received, the determination of the pulse is mistaken and a reception error occurs. In the case where the pulse width is extremely narrow at the initial stage of reception (during the preamble period), there is a possibility that a reception error occurs at that stage. A device such as a portable device whose installation state is unstable cannot follow the change in the pulse width characteristic due to the influence of the receiving distance and the angle that change every moment, and a reception error occurs. In this way, the present inventor has found that it is necessary to be able to determine pulse data following changes in the characteristics of the communication module and the communication environment. For such a viewpoint, the above-mentioned patent document does not provide a specific means.

  An object of the present invention is to provide a demodulator capable of determining a received pulse following changes in characteristics of a communication module and a communication environment.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  One representative demodulating device of the present invention includes a measuring circuit (3) for measuring the pulse width of an input pulse (10), the maximum pulse width of a single pulse portion defined by the packet format of the input pulse, and a double pulse. A value corresponding to the minimum pulse width of the unit is generated for each packet using the measurement value by the measurement circuit, and a determination threshold value (13) for distinguishing between the single pulse and the double pulse is obtained based on the generation result A pulse width of the double pulse and the single pulse of the input pulse is predetermined based on a magnitude relationship between the arithmetic circuit (4) that performs the measurement and a determination threshold value acquired by the arithmetic circuit with respect to the input pulse. An adjustment circuit (5) for adjusting the width of the data, and a data processing unit (6) for acquiring data from the pulse width adjusted by the adjustment circuit and demodulating the data With the door. As described above, since the determination threshold value is updated in packet format units, it is possible to determine input pulse data by dynamically changing the single pulse / double pulse determination range for each packet reception operation. Therefore, input pulse data can be determined following changes in the characteristics of the communication module and the communication environment. Even when it is applied to a portable device whose installation state is unstable, normal data reception can always be performed because it follows the change of the pulse waveform due to the influence of the receiving distance and the angle that change every moment.

  As a typical embodiment of the present invention, the packet format corresponds to the IrDA_FIR standard, the single pulse part is a preamble (PA), and the double pulse part is a start flag (STA).

  As another specific embodiment of the present invention, the arithmetic circuit performs an operation of shifting a value in the same direction as a tendency of an error of a pulse width of an input pulse with respect to a standard single pulse. Get the decision threshold. For example, the arithmetic circuit acquires, as the determination threshold, a value corresponding to an average value of a value corresponding to the maximum pulse width of the single pulse portion and a value corresponding to the minimum pulse width of the double pulse data portion. As a more specific calculation method, for example, the calculation circuit calculates a value obtained by shifting the value corresponding to the maximum pulse width of the single pulse data portion by 1 bit to the right and the minimum pulse width of the double pulse data portion. The determination threshold is acquired by adding the value obtained by shifting the corresponding value to the right by 1 bit.

  Another representative demodulator of the present invention includes a first arithmetic circuit (3) for analyzing a pulse width of a pulse defined by the packet format of the received pulse (10), and a single unit defined by the packet format. A second calculation for analyzing the maximum value of the pulse width in the pulse part and the minimum value of the pulse width in the double pulse part for each packet, and calculating a determination threshold for distinguishing between the single pulse and the double pulse based on the analysis result A circuit (4) and a detection circuit (5, 6) for detecting data from the received pulse based on a magnitude relationship between an analysis result by the first arithmetic circuit and a determination threshold value by the second arithmetic circuit.

  Still another representative demodulating device of the present invention analyzes the pulse width of the preamble and start flag specified by the packet format in units of packets of the received pulse by the infrared module, and receives based on the analysis result. Acquire a judgment threshold value for distinguishing between the pulse width of a single pulse and a pulse width of a double pulse included in the pulse, and determine the pulse width of the single pulse and the double pulse in the received pulse based on the obtained judgment threshold value. Adjust to the width of.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the received pulse data can be determined following changes in the characteristics of the communication module and the communication environment.

  FIG. 1 illustrates a demodulator (DMDL) applied to infrared communication based on the IrDA_FIR standard. The infrared module 2 receives an infrared signal and outputs pulse data. The demodulator 1 receives the pulse data. The demodulator 1 includes a pulse width counter 3, an arithmetic circuit 4, a pulse width adjustment circuit 5, a data processing circuit 6, and a control circuit 7.

  First, the communication data format defined by the IrDA FIR and the characteristics of the infrared module will be described. A communication data format of 4PPM which is a modulation method of IrDA_FIR is shown in FIG. Data transmitted by serial communication using infrared is converted into four light emission pulse positions in units of 2 bits and transmitted / received. The actual serial communication is as shown in FIG. 3, and a state called a single pulse in which pulses modulated by 4PPM are not adjacent to each other and an adjacent double pulse may occur.

  In the IrDA_FIR standard, the width of a single pulse is defined as 125 nsec (± 10 nsec), and the width of a double pulse is defined as 250 nsec (± 10 nsec). This is the standard value. In IrDA_FIR compatible infrared modules, there are many cases where the standard value is not satisfied due to the communication environment and electrical characteristics as described above. For example, as illustrated in FIG. 4, the pulse width deviates to the wide side and the narrow side to the narrow side. There can be both cases of deviating. In addition, during reception of the communication data format preamble (described later) in the initial stage of reception, there are cases where the reception pulse is not output for the initial several times, or even if the reception pulse is output, the pulse is stable. Even after a pulse according to the standard value is output, the pulse width may not satisfy the standard value due to changes in the communication environment.

  The packet format specified by IrDA_FIR is shown in FIG. In the transmission operation, after sending 16 preambles (PA) and 1 start flag (STA), data (DATA) and CRC (Cyclic Redundancy Check code) for the data are modulated by 4PPM and sent, and a stop flag is sent One packet is transmitted until (STO) is transmitted.

  The demodulator 1 starts data reception by receiving at least the last several times and one start flag (STA) among the 16 preambles (PA) during reception. When a stop flag (STO) is detected during data reception, the data reception is terminated, and the received data and CRC are inspected to determine whether the reception is normal. If normal, the received data (DATA) is demodulated, and if necessary, the subsequent packet is received. If there is an abnormality in the CRC check, retransmission of the packet is instructed.

  The symbol format of the preamble (PA) is shown in FIG. 6, and the symbol format of the start flag (STA) is shown in FIG. These symbol formats are not subject to 4PPM modulation and have the following characteristics. That is, the preamble (PA) is composed of a single pulse. All the start flags (STA) are composed of double pulses.

  The infrared module 2 receives an infrared signal and outputs a reception pulse (input pulse) 10. The pulse width counter 3 samples the signal pulse 10 and counts the pulse width. For example, the sampling pulse 11 is 48 MHz. As exemplified in FIG. 8, the pulse width counter 3 starts counting the sampling pulse 11 from the initial value in synchronization with the rising edge of the received pulse 10, for example, and stops the counting operation at the falling edge of the signal pulse 10. The width update trigger signal 12 is enabled.

  The arithmetic circuit 4 takes in the count value of the pulse width counter 3 and analyzes the pulse width every time the pulse width update trigger signal 12 is enabled. The pulse width of a single pulse can be analyzed during reception of the preamble (PA), and the pulse width of a double pulse can be analyzed during reception of the start flag (STA). For the analyzed pulse width of the single pulse, the count value of the maximum pulse width is stored in the storage circuit 16, and for the analyzed pulse width of the double pulse, the count value of the minimum pulse width is stored. The circuit 17 is stored. When reception of the start flag (STA) is completed, a determination threshold 13 which is a boundary condition for determining a single pulse and a double pulse from the count value corresponding to the stored maximum pulse width of the single pulse and the count value corresponding to the minimum pulse width of the double pulse. Is calculated. The determination threshold 13 is, for example, “single pulse maximum pulse width + double pulse minimum pulse width) / 2”. This is one idea for shifting the determination threshold in the same direction as the error tendency with respect to the pulse width because the error of the pulse width in the pulse signal is twice that of the single pulse with respect to the double pulse. . A square average or the like can be used instead of the simple average. In the circuit of FIG. 1, when storing the count value of the maximum pulse width and the minimum pulse width in consideration of the occurrence of a pulse sampling error when analyzing the pulse width, the process of truncating the lower 1 bit as an error, That is, 1-bit right shift processing is performed by the shift circuits 14 and 15. Since the 1-bit right shift processing is equivalent to dividing by 2, the count value corresponding to the maximum pulse width stored in the storage circuit 16 and the count value corresponding to the minimum pulse width of the double pulse stored in the storage circuit 17 are calculated. Addition is performed by the adder circuit 18 to obtain the determination threshold value 13.

  The comparison circuit 19 compares the count value output from the pulse width counter 3 with the determination threshold 13 and outputs an identification signal 20 indicating whether the pulse is a single pulse or a double pulse. In response to the identification signal 20, the pulse width adjustment circuit 5 adjusts the pulse width of the signal pulse 10 to a pulse width of a 125 nsec single pulse or a 250 nsec double pulse based on the standard and outputs it.

  The data processing circuit 6 includes a 16-bit shift register 21 and a 4PPM decoder 22. The 16-bit shift register 21 serially inputs the pulse signal output from the pulse width adjustment circuit 5 at a period of 125 nsec, and outputs it in parallel in units of 16 bits. The 4PPM decoder demodulates 4PPM format modulation data into 8-bit data in units of 16 bits and outputs the result. The 8-bit data is subjected to required data processing by a circuit at a later stage (not shown).

  The control circuit 7 has a format detection circuit 23 and a state machine 24. The format detection circuit 23 detects whether the output data 25 of the 16-bit shift register 21 is a preamble (PA), a start flag (STA), or data (DATA), a preamble detection signal 26, a start flag A transition detection signal 27 and a data transition detection signal 28 are generated. Although not shown, the format detection circuit 23 also detects a stop flag (STO). FIG. 9 shows a specific example of the format detection circuit 23. As illustrated in the figure, the format detection circuit 23 includes bit patterns 30 to 32 and comparators 33 to 35 to be detected for each of the detection signals 26, 27, and 28. Although not specifically shown, the preamble detection signal 26 is negated when the transition detection signal 34 to the start flag is asserted, and the transition detection signal 34 to the start flag is negated when the transition detection signal 28 to data is asserted. When the stop flag (STO) is detected, the data transition detection signal 28 is negated. The state machine 24 controls the operation of the demodulation circuit according to a predetermined procedure based on the input of the signal pulse 10 and the detection result by the format detection circuit 23.

  The storage circuit 16 can input the output count value of the shift circuit 14 during the assert period of the preamble detection signal 26. For example, as illustrated in FIG. 10, the storage circuit 16 includes a latch circuit 41 and a comparator 40, and the comparator 40 updates the pulse when the output count value 42 of the shift circuit 14 is larger than the latch data of the latch circuit 41. In synchronization with the update timing by the trigger 12, the latch circuit 41 is instructed to latch the count value 42. The instruction of the latch operation is valid only while the preamble detection signal 26 is asserted. Thereby, the latch circuit 41 can hold the maximum count value corresponding to the maximum pulse width of the single pulse included in the preamble (PA). Since the latch circuit 41 latches 0 by being initialized, the pulse width of the first received single pulse becomes the maximum value, and thereafter the count value of the larger pulse width is maximized every time the pulse width is updated. It will be stored as a value. Initialization of the latch circuit 41 is performed in response to detection of a stop flag (STO) by the state machine 24.

  The memory circuit 17 can input the output count value of the shift circuit 15 during the period when the transition detection signal 27 to the start flag is asserted. For example, as illustrated in FIG. 11, the storage circuit 17 includes a latch circuit 51 and a comparator 50, and when the comparator 50 has latch data of the latch circuit 51 larger than the output count value 52 of the shift circuit 15, In synchronization with the update timing by the pulse update trigger 12, the latch circuit 51 is instructed to latch the count value 52. The instruction of the latch operation is valid only while the start flag transition detection signal 27 is asserted. Thereby, the latch circuit 51 can hold the minimum count value corresponding to the minimum pulse width of the double pulse included in the start flag (STA). The latch circuit 51 is initialized to obtain a pulse width count value when sampling a pulse width of 375 nsecc (1.5 times the standard value 250 nsec) (for example, 18/2 = 9 if the sampling clock 11 is 48 MHz). Hold. Therefore, if the pulse width of the first received double pulse is 375 nsec or less, the value of the pulse width becomes the minimum value, and thereafter, every time the pulse width is updated, a smaller pulse width count value is stored as the minimum value. become. Initialization of the latch circuit 51 is performed in response to detection of a stop flag (STO) by the state machine 24.

  FIG. 12 shows an example of the pulse width adjustment circuit 5. FIG. 13 shows a timing chart of the adjustment operation by the pulse width adjustment circuit 5. The flip-flops (FF) 61 and 62 are D-type flip-flops that latch the received signal pulse 10 in synchronization with a clock 67 such as 48 MHz. The rising of the reception pulse 10 is detected by the two-stage flip-flops 61 and 62, the inverter 60 and the AND gate 63. The counter 71 counts the clock 67 and generates pulses 68 at intervals of 125 nsec. The set clear register 64 is set to 1 when the detection signal 69 is set to a high level by detecting the rising edge of the signal pulse 10, and is cleared to 0 when the pulse 68 is generated at intervals of 125 nsec. The set clear controller 65 sets the set clear register 66 to 1 by generating a pulse 68 at an interval of 125 nsec in the set state of the set clear register 64 (t1, t3). Thereafter, when a pulse 68 having an interval of 125 nsec is generated in the clear state of the set clear register 64, the set clear controller 65 clears the set clear register 66 to 0 when the identification signal 20 means a single pulse, and the result As a result, a 125 nsec single pulse is formed as the width-adjusted pulse 70 (t2). On the other hand, after the set clear register 66 is set to 1, when the pulse 68 with an interval of 125 nsec is generated in the clear state of the set clear register 64, if the identification signal 20 means a double pulse, the set clear controller 65 Clears the set clear register 66 to 0 again at the timing when the pulse 68 at the interval of 125 nsec is generated, and as a result, a double pulse of 250 nsec is formed as the width-adjusted pulse 70 (t4).

  FIG. 14 shows a control procedure of an operation for obtaining the maximum count value of a single pulse and the minimum count value of a double pulse. The state machine 24 waits until there is a change in the received pulse 10, and proceeds to the next process when detecting the change (S1). In order to be able to receive a single pulse having a wide pulse width, the maximum count value of the pulse width of the single pulse is initially set to 0, for example (S2). Reception of the pulse signal 10 is started and the pulse width is counted (S3). Wait until the preamble (PA) is received, for example, three times (S4). This is to wait until the pulse width is stabilized in the initial stage of reception. When received three times, the count value of the received single pulse is compared with the count value of the single pulse received immediately before (initial value 0 when received for the first time) (S5), and if the received pulse is larger, the process proceeds to step S6. If the process is the same or smaller, the process proceeds to step S7. In step S6, the 1-bit right shift value of the count value corresponding to the pulse width of the single pulse at that time is stored as the maximum count value of the single pulse. In step S7, the detection circuit 23 detects the boundary between the preamble (PA) and the start flag (STA). If the boundary is detected, the process proceeds to the next process. If the preamble PA is still being received, the process proceeds to step S5. Return.

  For reception of the start flag (STA), the minimum count value of the pulse width of the double pulse is initialized to 9 corresponding to the pulse width of 375 nsec, for example (S8). The received double pulse and the count value of the double pulse received immediately before are compared (S9). If the received pulse is smaller, the process proceeds to step S10, and if it is equal, the process proceeds to step S11. In step S10, the 1-bit right shift value of the count value corresponding to the pulse width of the double pulse at that time is stored as the minimum count value of the double pulse. In step S11, a boundary between the start flag (STA) and data (DATA) is detected, and after the boundary with the data is detected, the process proceeds to step S12. If the start flag (STA) is being received, step S11 is performed. The process returns to S9. While data (DATA) is being received, the sum of the 1-bit right shift value of the maximum count value of the single pulse and the 1-bit right shift value of the minimum count value of the double pulse is used as a determination threshold value (S12). Data reception processing is started (S13). The data reception process is repeated until the stop flag (STO) is received. When the stop flag (STO) is received, the series of processes ends, and the process returns to step S1 in preparation for the next packet reception. Thereafter, the above process is repeated for each packet format.

  According to the demodulator 1 described above, since the determination threshold is updated in packet format units, it is possible to determine pulse data by dynamically changing the single pulse and double pulse discrimination range for each packet reception operation. Become. Therefore, pulse data can be determined following changes in the characteristics of the infrared module and the communication environment. Even when it is applied to a portable device whose installation state is unstable, normal data reception can always be performed because it follows the change of the pulse waveform due to the influence of the receiving distance and the angle that change every moment. Even if the connected infrared module has different electrical characteristics, it is not necessary to individually set a determination threshold value for single pulse and double pulse by a microprocessor or the like.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the present invention is not limited to 4PPM demodulation and can be applied to demodulation of 16PPM modulated signals. In addition, the storage circuit that stores the maximum count value and the minimum count value, the pulse width adjustment circuit, and the like are not limited to the above configuration, and can be changed to an appropriate logical configuration.

It is a block diagram which illustrates the demodulation apparatus applied to the infrared communication by IrDA_FIR standard. It is a format figure which shows the communication data format of 4PPM which is a modulation system of IrDA_FIR. It is a wave form diagram which illustrates the state called the single pulse and double pulse which generate | occur | produce in actual serial communication. It is a wave form diagram which illustrates both the case where the output pulse of the infrared module corresponding to IrDA_FIR deviates to the wide side and the case where it deviates to the narrow side. It is a format diagram which illustrates the packet format prescribed | regulated by IrDA_FIR. It is a format figure which illustrates the symbol format of a preamble. It is a format figure which illustrates the symbol format of a start flag. It is a timing chart of the pulse width detection operation by the pulse width counter. It is a block diagram which shows the specific example of a format detection circuit. It is a block diagram which shows an example of the memory | storage circuit which hold | maintains the maximum count value of a single pulse. It is a block diagram which shows an example of the memory | storage circuit which hold | maintains the minimum count value of a double pulse. It is a block diagram which shows an example of a pulse width adjustment circuit. It is a timing chart of the adjustment operation by the pulse width adjustment circuit. It is a flowchart which illustrates the control procedure of the operation | movement which acquires the maximum count value of a single pulse, and the minimum count value of a double pulse.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Demodulator 2 Infrared module 3 Pulse width counter 4 Arithmetic circuit 5 Pulse width adjustment circuit 6 Data processing circuit 7 Control circuit PA Preamble STA Start flag DATA Data STO Stop flag 13 Case threshold 14, 15 Shift circuit 16, 17 Storage circuit 18 Addition Circuit 19 Comparator 20 Single pass / double pulse identification signal 21 16 bit shift register 22 4PPM decoder 23 Format detection circuit 24 State machine 25 Output data 26 Preamble detection signal 27 Transition detection signal to start flag 28 Transition detection signal to data 40 Comparator 41 Latch Circuit 42 Output Count Value 43 Single Pulse Maximum Count Value 50 Comparator 51 Latch Circuit 52 Output Count Value 53 Double Pulse Minimum Count Value 70 Adjustment After pulse

Claims (7)

A measurement circuit that measures the pulse width of the input pulse;
A value corresponding to the maximum pulse width of the single pulse part and the minimum pulse width of the double pulse part defined by the packet format of the input pulse is generated for each packet unit using the measurement value by the measurement circuit, and the generation result An arithmetic circuit for obtaining a determination threshold for distinguishing between a single pulse and a double pulse based on
An adjustment circuit that adjusts the pulse widths of the double pulse and the single pulse of the input pulse to a predetermined width based on the magnitude relationship between the measurement value of the input pulse by the measurement circuit and the determination threshold acquired by the arithmetic circuit; ,
And a data processing unit that acquires data from the pulse width adjusted by the adjustment circuit and demodulates the data. The packet format corresponds to the IrDA_FIR standard,
The single pulse part is a preamble,
The demodulator according to claim 1, wherein the double pulse part is a start flag.   2. The demodulator according to claim 1, wherein the arithmetic circuit obtains the determination threshold by performing an operation of shifting a value in the same direction as a tendency of an error of a pulse width of an input pulse with respect to a standard single pulse.   The arithmetic circuit acquires, as the determination threshold value, a value corresponding to an average value of a value corresponding to the maximum pulse width of the single pulse portion and a value corresponding to the minimum pulse width of the double pulse data portion. The demodulator described.   The arithmetic circuit shifts the value corresponding to the maximum pulse width of the single pulse data portion by 1 bit to the right and the value corresponding to the minimum pulse width of the double pulse data portion to the right by 1 bit. The demodulation apparatus according to claim 4, wherein the determination threshold is acquired by adding the obtained value. A first arithmetic circuit that analyzes a pulse width of a pulse defined by a packet format of a received pulse;
For analyzing the maximum value of the pulse width in the single pulse part and the minimum value of the pulse width in the double pulse part specified in the packet format in units of packets, and for distinguishing between the single pulse and the double pulse based on the analysis result A second arithmetic circuit for calculating a determination threshold;
And a detection circuit configured to detect data from the received pulse based on a magnitude relationship between an analysis result by the first arithmetic circuit and a determination threshold value by the second arithmetic circuit.   Analyze the pulse width of the preamble and start flag specified by the packet format for each received pulse packet by the infrared module, and based on the analysis result, the single pulse width and double pulse width included in the received pulse And a demodulator that adjusts the pulse width of the single pulse and the pulse width of the double pulse to a predetermined width based on the acquired determination threshold.

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