JP2010133781A - Secondary surveillance radar - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a secondary surveillance radar which can utilize information included in a preamble. <P>SOLUTION: The secondary surveillance radar 1 receives a response R for mode S including a preamble PA having first to fourth pulses P1-P4. The secondary surveillance radar 1 is provided with a preamble pulse width counter processing section 34 including: a rising edge detection section 42 which detects the rising edges of the pulses P1-P4 of the preamble PA to output a rising edge detection signal Sr; a falling edge detection section 43 which detects the falling edges of the pulses P1-P4 of the preamble PA to output a falling edge detection signal Sd; and a counter 41 which counts a clock pulse CLK which is input at constant intervals between the rising edge detection signal Sr and the falling edge detection signal Sd to measure pulse widths WC1-WC4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a secondary monitoring radar that receives a response for mode S including a preamble.

  A secondary monitoring radar that acquires information related to monitoring for air traffic control by sending questions to transponders installed in aircraft and receiving various information in response to the questions as responses from the transponders. (SSR: Secondary Survey Radar) is known.

  The secondary monitoring radar transmits a question for mode A / C to the ATCRBS transponder used conventionally and a question for mode S to the mode S transponder developed in recent years. The secondary monitoring radar receives the mode A / C response to the mode A / C question and the mode S response to the mode S question.

  Here, the response for mode S includes a preamble and a data block. Furthermore, the preamble includes first to fourth pulses. These four pulses are transmitted at a predetermined pulse interval and a predetermined pulse width from a mode S transponder mounted on the aircraft (see Patent Document 1).

In the secondary monitoring radar, the response for the mode S is determined only when the four pulses of the preamble described above are detected at a predetermined pulse interval. Thereafter, the secondary monitoring radar processes and analyzes the information included in the data block transmitted after the preamble.
JP 2007-71623 A

  However, the secondary monitoring radar only measures the preamble pulse interval and detects whether or not it is a prescribed preamble. Therefore, there is a problem that other information held in the preamble cannot be obtained.

  The present invention has been developed to solve the above-described problems, and an object thereof is to provide a secondary monitoring radar that can use more information included in a preamble.

  A secondary monitoring radar according to the present invention, in a secondary monitoring radar that receives a response for mode S including a preamble having a first pulse to a fourth pulse, detects a rising edge of the preamble pulse and outputs a rising detection signal. The rising detection means for outputting, the falling detection means for detecting the falling edge of the preamble pulse and outputting the falling detection signal, and the rising detection signal and the falling detection signal are input at regular intervals. And a preamble pulse width counter processing means including a counter means for counting clock pulses and outputting the count value as a pulse width of the preamble pulse.

  According to the present invention, since the pulse width of the pulse included in the preamble can be obtained as information, the pulse width can be used as information.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram showing the relationship between the secondary monitoring radar and the aircraft according to the first embodiment. FIG. 2 is a block diagram showing an internal configuration of the secondary monitoring radar. FIG. 3 is a block diagram showing an internal configuration of the mode S response processor. FIG. 4 is a block diagram showing an internal configuration of the preamble pulse width count processing unit.

  As shown in FIG. 1, the secondary monitoring radar 1 according to the first embodiment transmits and receives a question Q and a response R to an aircraft 91 equipped with a mode S transponder 92, and obtains and monitors various information. It is.

  The secondary monitoring radar 1 is installed in the ground station 2. The secondary monitoring radar 1 includes an antenna 3, a transmission / reception unit 4, and a processing unit 5.

  As shown in FIG. 2, the transmission / reception unit 4 includes a mixer 11, a transmitter 12, and a receiver 13.

  The mixer 11 relays the antenna 3, the transmitter 12 and the receiver 13. The mixer 11 transmits the question Q sent from the transmitter 12 to the antenna 3. Further, the mixer 11 transmits the response R sent from the antenna 3 to the receiver 13.

  The transmitter 12 transmits the question Q input from the processing unit 5 to the aircraft 91 via the mixer 11 and the antenna 3. The transmitter 12 includes a main transmitter (not shown) that outputs INT pulses transmitted from the main beam, and a sub-transmitter (not illustrated) that outputs sidelobe suppression (SLS) pulses transmitted from the omni beam. Including.

  The receiver 13 receives the response R from the aircraft 91 to the question Q via the antenna 3 and the mixer 11. The receiver 13 digitizes the received response R by amplification detection and quantization, and then supplies the response R to an ATCRBS response processor 24 and a mode S response processor 23 described later.

  As shown in FIG. 2, the processing unit 5 includes a transmission controller 21, a channel manager 22, a mode S response processor 23, an ATCRBS response processor 24, a timing signal generator 25, and a monitoring processor 26. And.

  The transmission controller 21 is connected to the transmitter 12, the channel manager 22, the timing signal generator 25, and the monitoring processor 26.

  The transmission controller 21 generates an all-call question Q based on its own site ID (identification code) and PR value (response probability value) supplied from the monitoring processor 26 during the all-call period. Note that an all-call question dedicated to mode A / C is also generated during the all-call period. Further, the transmission controller 21 generates a roll call question Q based on aircraft information such as the mode S address, distance, and direction of the aircraft 91 supplied from the monitoring processor 26 during the roll call period.

  The transmission controller 21 transmits the generated questions Q from the antenna 3 via the transmitter 12 and the mixer 11.

  The channel manager 22 is connected to the transmission controller 21, the mode S response processor 23, the ATCRBS response processor 24, the timing signal generator 25, and the monitoring processor 26. The channel manager 22 sets the sweep time to the beam dwell time based on the signal from the timing signal generator 25. The channel manager 22 assigns an all call period and a roll call period to the sweep time. The channel manager 22 allocates a window period for receiving a response from the aircraft 91 to the all call period and the roll call period.

  The mode S response processor 23 is connected to the receiver 13, the channel manager 22, the timing signal generator 25, and the monitoring processor 26.

  The mode S response processor 23 detects the preamble PA included in the response R for mode S from the aircraft 91 equipped with the mode S transponder 92, and analyzes the information included in the data block of each response R. Note that data block analysis processing is performed by a known method, and is therefore omitted.

  As shown in FIG. 3, the mode S response processor 23 includes a binarization processing unit 31, a preamble correlation processing unit 32, a data decoder processing unit 33, and a preamble pulse width counter processing unit 34.

  The binarization processing unit 31 binarizes the input response R into “0” and “1”. The binarization processing unit 31 outputs the binarized response R to the preamble correlation processing unit 32, the data decoder processing unit 33, and the preamble pulse width counter processing unit 34.

  The preamble correlation processing unit 32 correlates the preamble PA including the binarized first pulse P1 to fourth pulse P4.

  The preamble correlation processing unit 32 measures the pulse interval of the first pulse P1 to the fourth pulse P4, and if it is a prescribed pulse interval, the data decoder processing unit 33, the preamble pulse width counter processing unit 34, and the subsequent stage. A preamble detection signal Sde is output. Here, the prescribed pulse interval between the first pulse P1 and the second pulse P2 is 1.0 μs. The pulse interval between the prescribed third pulse P3 and fourth pulse P4 is 1.0 μs. The pulse interval between the prescribed first pulse P1 and third pulse P3 is 3.5 μs.

  The data decoder processing unit 33 analyzes the data block DB included in the binarized response R. The data block DB is a Manchester code. The first data bit of the data block DB is at a position 8 μs after the rising edge of the first pulse P1 of the preamble PA.

  The preamble pulse width counter processing unit 34 counts and measures the first to fourth pulse widths WC1, WC2, WC3, and WC4 of the first to fourth pulses P1, P2, P3, and P4.

  As shown in FIG. 4, the preamble pulse width counter processing unit 34 includes a flip-flop circuit FF1, a counter unit 41, a rising detection unit 42, a falling detection unit 43, a counter latch circuit 44, and a flip-flop circuit FF2. And first to third shift registers SR1, SR2, SR3, a latch timing adjustment unit 45, and a pulse width latch circuit 46. The counter latch circuit 44 and the first to third shift registers SR1, SR2, SR3 correspond to the pulse width holding means described in the claims. The latch timing adjustment unit 45 corresponds to the timing adjustment means described in the claims. The pulse width latch circuit 46 corresponds to the pulse width output means described in the claims.

  The flip-flop circuit FF1 temporarily holds the response R including the preamble PA input after being binarized by the binarization processing unit 31, and then the counter unit 41, the rising detection unit 42, and the falling detection unit 43. To output.

  The counter unit 41 counts a 40 MHz clock pulse CLK input between the rising detection signal Sr and the falling detection signal Sd. The counter unit 41 outputs the count value to the counter latch circuit 44 as the pulse widths WC1 to WC4 of the first pulse P1 to the fourth pulse P4. Specifically, when the rising edge detection signal Sr is input from the rising edge detection section 42, the counter section 41 returns the count value to “0” and then restarts the counting of the clock pulse CLK. That is, the counter unit 41 counts and outputs the number of clock pulses CLK after the first pulse P1 to the fourth pulse P4 are input.

  The counter unit 41 needs to be configured to have a number of bits that can count the pulse widths WC1 to WC4. Here, considering that the cycle of the clock pulse CLK is 40 MHz and the specified pulse width is 500 ns, it is preferable that the counter unit 41 can count at least 25 or more. Therefore, the counter unit 41 is preferably 5 bits or more.

  The rising edge detection unit 42 detects rising edges of the first pulse P1 to the fourth pulse P4. When detecting the rising edge, the rising edge detection unit 42 outputs the rising edge detection signal Sr to the counter unit 41.

  The falling detection unit 43 detects the falling of the first pulse P1 to the fourth pulse P4. The falling detection unit 43 outputs a falling detection signal Sd to the counter latch circuit 44 via the flip-flop circuit FF2.

  The flip-flop circuit FF2 temporarily delays the falling detection signal Sd input from the falling detection signal Sd, and then outputs it to the counter latch circuit 44.

  The counter latch circuit 44 temporarily holds and outputs the pulse widths WC1 to WC4 counted by the counter unit 41. Specifically, pulse widths WC 1 to WC 4 corresponding to the first pulse P 1 to the fourth pulse P 4 are sequentially input from the counter unit 41 to the counter latch circuit 44. The counter latch circuit 44 holds the same pulse widths WC1 to WC4 until the falling detection signal Sd is input. The counter latch circuit 44 outputs the held pulse widths WC1 to WC4 to the shift register SR1 and the pulse width latch circuit 46. When the falling detection signal Sd is input, the counter latch circuit 44 newly uses the pulse widths WC1 to WC4 counted by the counter unit 41 at that time instead of the pulse widths WC1 to WC4 that are held. Hold and output.

  The first shift register SR1 delays the pulse widths WC1 to WC4 input from the counter latch circuit 44 by 1 μs. After the delay, the first shift register SR1 outputs the pulse widths WC1 to WC4 to the second shift register SR2 and the pulse width latch circuit 46.

  The second shift register SR2 delays the pulse widths WC1 to WC4 input from the first shift register SR2 by 2.5 μs. The second shift register SR2 outputs the pulse widths WC1 to WC4 to the third shift register SR3 and the pulse width latch circuit 46 after being delayed.

  The third shift register SR3 delays the pulse widths WC1 to WC4 input from the second shift register SR2 by 1.0 μs. The third shift register SR3 outputs the pulse widths WC1 to WC4 to the pulse width latch circuit 46 after being delayed.

  The counter latch circuit 44 and the shift registers SR1 to SR3 described above preferably have 5 bits or more, like the counter unit 41.

  The latch timing adjustment unit 45 includes a plurality of flip-flop circuits. When the preamble detection signal Sde is input from the preamble correlation processing unit 32, the latch timing adjustment unit 45 outputs a timing signal Stm for outputting the pulse widths WC1 to WC4 to the subsequent stage after a predetermined delay time. Output to 46.

  The pulse width latch circuit 46 holds the pulse widths WC1 to WC4 of the first pulse P1 to the fourth pulse P4 and outputs them to the subsequent stage. Further, when the timing signal Stm is input from the latch timing adjustment unit 45, the pulse width latch circuit 46 replaces the held pulse widths WC1 to WC4 with the counter latch circuit 44 and the shift registers SR1 to SR3 at that time. The input pulse widths WC1 to WC4 are held and output as new pulse widths WC1 to WC4.

  The ATCRBS response processor 24 is connected to the receiver 13, the channel manager 22, the timing signal generator 25, and the monitoring processor 26. The ATCRBS response processor 24 detects and processes a mode A / C dedicated all call question response from an aircraft (not shown) equipped with an ATCRBS transponder during the all call period.

  The timing signal generator 25 is connected to the transmission controller 21, the channel manager 22, the mode S response processor 23, the ATCRBS response processor 24, and the monitoring processor 26. The timing signal generator 25 forms and supplies the timing for system operation and question signal formation in the azimuth direction of the antenna 3 so as to control the entire system of the processing unit 5. The timing signal generator 25 inputs a 40 MHz (25 ns) clock pulse CLK to the mode S response processor 23.

  The monitoring processor 26 is connected to the transmission controller 21, the channel manager 22, the mode S response processor 23, the ATCRBS response processor 24, and the timing signal generator 25.

  In the monitoring processor 26, various aircraft information and the like are stored in the memory. The monitoring processor 26 receives the pulse widths WC1 to WC4 from the preamble pulse width counter processing unit 34. The monitoring processor 26 outputs a detection report including information relating the aircraft information supplied from the mode S response processor 23 and the pulse widths WC1 to WC4.

  Next, the aircraft 91 that transmits and receives with the secondary monitoring radar 1 described above will be briefly described.

  The aircraft 91 receives the mode S question Q transmitted from the antenna 3 of the secondary monitoring radar 1, and sends the mode S response R to the mode S question Q to the secondary monitoring radar 1 of the ground station 2. An antenna 93 and a mode S transponder 92 for transmitting the signal are mounted. The mode S transponder 92 includes a transmission / reception unit 94 and a signal processing unit 95 connected to the transmission / reception unit 94.

  Next, the transmission / reception operation between the secondary monitoring radar 1 and the aircraft 91 according to the first embodiment will be described with reference to the drawings.

  First, the transmission controller 21 generates a question Q based on information such as its own site ID and PR value from the monitoring processor 26 of the secondary monitoring radar 1. Here, the all-call question Q is generated during the all-call period set by the channel manager 22. On the other hand, during the roll call period set by the channel manager 22, a roll call question Q is generated.

  Next, the transmission controller 21 transmits the question Q via the transmitter 12 and the antenna 3.

  Next, when the aircraft 91 receives the question Q, the aircraft 91 transmits a response R including the preamble PA and the data block DB.

  When the secondary monitoring radar 1 receives the response R transmitted from the aircraft 91, the secondary monitoring radar 1 performs the following processing. Here, the pulse pattern of the data block DB is different between the response for all calls and the response for roll calls. However, the preamble PA is defined by the same pulse pattern regardless of the response for all calls and the response for roll calls. Therefore, the processing of the preamble PA, which is a feature of the present application, will be described together because the same processing is performed regardless of the response R for all calls and the response R for roll calls.

  First, when the response R is received by the antenna 3 of the secondary monitoring radar 1, the response R is output to the mode S response processor 23 via the mixer 11 and the receiver 13.

  Next, in the mode S response processor 23, the input response R is binarized by the binarization processing unit 31. Thereafter, the binarized response R is input to the preamble correlation processing unit 32. The preamble correlation processing unit 32 determines whether or not the pulse interval of the input preamble PA of the response R is a prescribed interval. When the preamble PA is detected, the preamble correlation processing unit 32 outputs the preamble detection signal Sde to the data decoder processing unit 33, the preamble pulse width counter processing unit 34, and the subsequent stage.

  When the preamble detection signal Sde is input, the data decoder processing unit 33 performs a decoding process on the data block DB input 8 μs after the first pulse P1 of the preamble PA. The data decoder processing unit 33 outputs a data bit and a reliability bit indicating the reliability of each data bit to the subsequent stage as a decoding result.

  On the other hand, the preamble pulse width counter processing unit 34 performs measurement processing of the pulse widths WC1 to WC4 of the first pulse P1 to the fourth pulse P4 included in the preamble PA.

  Hereinafter, measurement processing of the pulse widths WC1 to WC4, which is a feature of the present application, will be described with reference to the drawings. FIG. 5 is a timing chart for explaining the preamble pulse width measurement process. FIG. 6 is a timing chart for explaining the measurement processing of the pulse width of the first pulse. That is, FIG. 6 corresponds to a partially enlarged view of FIG.

  In FIG. 5 and FIG. 6, the numerical value shown in the “counter unit” is a value counted by the counter unit. In FIG. 5, the numerical values shown in the “counter latch circuit”, “shift registers SR1 to SR3”, and “pulse latch circuit” are the pulse widths held respectively. In FIG. 6, the numerical value shown in the “counter latch circuit” is the pulse width held in the counter latch circuit.

  In the following description, as shown in FIG. 5, the pulse widths WC1 to WC4 of the first pulse P1 to the fourth pulse P4 of the input preamble PA are not the prescribed 500 ns due to the malfunction of the transponder of the aircraft. These are described as being 500 ns, 475 ns, 525 ns, and 450 ns, respectively. In addition, it is assumed that a 40 MHz (25 ns period) clock pulse CLK is constantly input from the timing signal generator 25 to the preamble pulse width counter processing unit 34.

  First, as shown in FIG. 5, when the preamble PA is input to the preamble pulse width counter processing unit 34, the preamble PA is converted into the counter unit 41, the rising detection unit 42, and the falling detection unit 43 via the flip-flop circuit FF1. Is entered.

  Thereafter, the rising edge of the first pulse P1 is detected by the rising edge detector 42. When detecting the rising edge, the rising edge detection unit 42 outputs the rising edge detection signal Sr to the counter unit 41 as shown in FIG.

  When the rising edge detection signal Sr is input, the counter unit 41 returns the count value to “0” and enters the count state (enable state). Thereafter, the counter unit 41 counts the number of input clock pulses CLK again and outputs the count value to the counter latch circuit 44.

  Next, when the falling detection unit 43 detects the falling of the first pulse P1, the falling detection signal Sd is output to the counter latch circuit 44 via the flip-flop circuit FF2. When the falling detection signal Sd is input to the counter latch circuit 44, the count value (= 20) counted by the counter unit 41 at that time is replaced with a new pulse width instead of the previous pulse width held. Hold as WC1. The counter latch circuit 44 holds this pulse width WC1 until the next falling detection signal Sd is input, and outputs it to the first shift register SR1 and the pulse width latch circuit 46.

  The first shift register SR1 outputs the input pulse width WC1 to the second shift register SR2 and the pulse width latch circuit 46 1.0 μs after the pulse width WC1 is input.

  The second shift register SR2 outputs the input pulse width WC1 to the third shift register SR3 and the pulse width latch circuit 46 after 2.5 μs from the input of the pulse width WC1.

  The third shift register SR3 outputs the input pulse width WC1 to the pulse width latch circuit 46 1.0 μs after the pulse width WC1 is input.

  Next, when the second pulse P <b> 2 is input, the rise and fall are detected by the rise detection unit 42 and the fall detection unit 43. As a result, the pulse width WC2 of the second pulse P2 is counted in the same manner as the pulse width WC1 of the first pulse P1 described above, and the pulse width WC2 is held in the counter latch circuit 44. Here, since the pulse width WC2 of the second pulse P2 is 475 ns, which is shorter than the prescribed 500 ns, the count value is “19”.

  Next, the pulse width WC2 of the second pulse P2 is output from the counter latch circuit 44 to the first shift register SR1 and the pulse width latch circuit 46. After 1.0 μs, the pulse width WC2 of the second pulse P2 is output to the second shift register SR2 and the pulse width latch circuit 46, and further 2.5 μs later, the third shift register SR3 and the pulse width latch circuit 46, and 1.0 μs later, it is output to the pulse width latch circuit 46.

  Thereafter, when the third pulse P3 and the fourth pulse P4 are input, the respective pulse widths WC3 (= 21) and pulse widths WC4 (= 18) are counted by the same process as described above. Thereafter, the pulse width WC3 and the pulse width WC4 are output to the pulse width latch circuit 46 via the counter latch circuit 44 and the first to third shift registers SR1 to SR3.

  Next, when the preamble PA is detected by the preamble correlation processing unit 32, the preamble detection signal Sde is input from the preamble correlation processing unit 32 to the latch timing adjustment unit 45. Thereby, the latch timing adjusting unit 45 outputs the timing signal Stm to the pulse width latch circuit 46 after being delayed for a predetermined time.

  When the timing signal Stm is input to the pulse width latch circuit 46, the pulse width WC1 to WC4 input from the counter latch circuit 44 and the first to third shift registers SR1 to SR3 at that time are newly set. These are held as pulse widths WC1 to WC4.

  When the timing signal Stm is input, the pulse width WC4 is input from the counter latch circuit 44 to the pulse width latch circuit 46 and the pulse width WC3 is input from the first shift register SR1 due to the delay time described above. The pulse width WC2 is input from the second shift register SR2, and the pulse width WC1 is input from the third shift register SR3. Therefore, the pulse width latch circuit 46 outputs these four new pulse widths WC1 to WC4 to the monitoring processor 26 at the same time.

  Thereafter, the monitoring processor 26 outputs the pulse widths WC1 to WC4 in association with the aircraft information to an external processor (not shown). In the external processor, the pulse widths WC1 to WC4 are stored in association with the aircraft information and utilized. For example, an external processor is used for specifying an aircraft or analyzing a response state (gerbble or the like) by a difference in pulse widths WC1 to WC4 for each aircraft 91 (transponder 92), remotely or offline.

  As described above, in the secondary monitoring radar 1 according to the first embodiment, the preamble pulse width counter processing unit 34 measures the pulse widths WC1 to WC4 of the first pulse P1 to the fourth pulse P4 of the preamble PA as information. Can be output. As a result, the secondary monitoring radar 1 can use the pulse widths WC1 to WC4 that have not been used in the past for information or the like for identifying the aircraft 91.

  Further, the secondary monitoring radar 1 includes the counter latch circuit 44 that can hold the pulse widths WC1 to WC4 and the first to third shift registers SR1 to SR3, thereby providing four pulse widths WC1 to WC4. Can be output.

  Further, the secondary monitoring radar 1 includes first to third shift registers SR1 to SR3 that delay the outputs of the pulse widths WC1 to WC4 and a pulse width latch circuit 46 that can simultaneously hold the pulse widths WC1 to WC4. Thus, the pulse widths WC1 to WC4 can be output simultaneously.

  As mentioned above, although this invention was demonstrated in detail using embodiment, this invention is not limited to embodiment described in this specification. The scope of the present invention is determined by the description of the scope of claims and the scope equivalent to the description of the scope of claims. Hereinafter, modified embodiments in which the above-described embodiment is partially modified will be described.

  The configuration in the embodiment described above can be changed as appropriate. For example, it is conceivable to change the above-described numerical values and circuits.

  In the above-described embodiment, all the pulse widths of the first pulse to the fourth pulse included in the preamble are measured and output. However, only the pulse width of any one of the pulses may be measured and output. In this case, the first to third shift registers can be omitted as appropriate.

  In the above-described embodiment, the frequency of the clock pulse input to the counter unit is 40 MHz, but the frequency of the clock pulse can be changed as appropriate. The period (frequency) of the clock pulse may be smaller than the pulse width of the first pulse to the fourth pulse of the preamble.

It is the schematic which shows the relationship between the secondary monitoring radar and aircraft by 1st Embodiment. It is a block diagram which shows the internal structure of a secondary monitoring radar. It is a block diagram which shows the internal structure of a mode S response processor. It is a block diagram which shows the internal structure of a preamble pulse width count process part. It is a timing diagram explaining the measurement process of the pulse width of a preamble. It is a timing diagram explaining the measurement process of the pulse width of the first pulse.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Secondary monitoring radar 2 Ground station 3 Antenna 4 Transmission / reception part 5 Processing part 11 Mixer 12 Transmitter 13 Receiver 21 Transmission controller 22 Channel manager 23 Mode S response processor 24 ATCRBS response processor 25 Timing signal generator 26 Monitoring Processor 31 Binary processing unit 32 Preamble correlation processing unit 33 Data decoder processing unit 34 Preamble pulse width counter processing unit 41 Counter unit 42 Rising detection unit 43 Falling detection unit 44 Counter latch circuit 45 Latch timing adjustment unit 46 Pulse width latch Circuit 91 Aircraft 92 Transponder 93 Antenna 94 Transmitter / receiver 95 Signal processor FF1, FF2 Flip-flop circuits P1 to P4 First pulse to fourth pulse PA Preamble DB Data block CLK Clock pulse Q Question R Response Sr Rise detection signal Sd Falling detection signal Sde Preamble detection signals SR1 to SR3 Shift register Stm Timing signals WC1 to WC4 First to fourth pulse widths

Claims (7)

In the secondary monitoring radar receiving a response for mode S including a preamble having a first pulse to a fourth pulse,
Rising detection means for detecting a rising edge of the preamble pulse and outputting a rising detection signal, a falling detection means for detecting a falling edge of the preamble pulse and outputting a falling detection signal, and the rising detection signal; A preamble pulse width counter processing unit including a counter unit that counts clock pulses input at regular intervals between the falling detection signal and outputs the count value as the pulse width of the preamble pulse. Secondary surveillance radar characterized by that.   The secondary monitoring according to claim 1, wherein the preamble pulse width counter processing means includes pulse width holding means for receiving the pulse width measured by the counter means and holding the pulse width. Radar.   The secondary monitoring radar according to claim 2, wherein four pulse width holding means are provided.   4. The secondary monitoring radar according to claim 3, wherein the three pulse width holding means among the four pulse width holding means output the pulse widths after holding the pulse widths for different delay times. The preamble pulse width counter processing means includes:
The pulse width measured by the counter means is input, and the pulse width holding means for holding the pulse width;
5. The secondary according to claim 1, further comprising: a pulse width output unit configured to hold and output a plurality of pulse widths input from the pulse width holding unit. Surveillance radar. The preamble pulse width counter processing means includes timing adjustment means for inputting a timing signal to the pulse width output means,
6. The secondary monitoring radar according to claim 5, wherein when the timing signal is input, the pulse width output means holds a new pulse width instead of the held pulse width. A preamble detection unit that detects a preamble and outputs a preamble detection signal to the timing adjustment unit;
The secondary monitoring radar according to claim 6, wherein the timing adjustment unit outputs a timing signal when the preamble detection signal is input.