JP2006210697A - Strained silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a strained silicon wafer for further reducing through dislocation density in a strained silicon layer. <P>SOLUTION: The strained silicon wafer is in a structure, having an epitaxial layer with lattice mismatching and a strained Si layer 3 on a single-crystal silicon substrate 1, and uses an off-cut surface where the crystal surface of the silicon surface inclines by 0.2°-1° to the directions of crystal orientation <100> and <0-10> from a plane orientation of (100) plane. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a strained silicon wafer, and more particularly to a strained silicon wafer having a reduced threading dislocation density.

  In recent years, there has been an increasing demand for high-speed and low-power consumption semiconductor devices, but there is a limit to further device performance improvements due to significant scale reduction of devices, that is, significant reduction in device dimensions and miniaturization. I'm starting to see it.

  For this reason, a semiconductor substrate having a strained silicon layer has attracted attention as a substrate for forming a semiconductor device with high speed and low power consumption. In particular, a high-speed device using a strained silicon layer (hereinafter referred to as a strained Si layer) obtained by epitaxially growing silicon on a single crystal silicon substrate via a silicon-germanium layer (hereinafter referred to as a SiGe layer) in a channel region. Is attracting attention.

  In the strained Si layer, tensile strain is generated due to the SiGe layer having a larger lattice constant than silicon. This strain changes the Si band structure, degenerates and increases carrier mobility, and the use of a strained Si layer in the channel region makes it possible to increase the carrier speed by 1.5 times or more when using bulk silicon. It becomes.

  In order to obtain a high-quality strained Si layer, it is necessary to epitaxially grow a high-quality SiGe layer on a silicon substrate, that is, a SiGe layer having a low threading dislocation and defect density, relaxed strain, and a smooth surface.

  However, since there is a difference of about 4.2% in lattice constant between Si and Ge, when epitaxial growth is performed as it is in a normal state, the Si surface is oxidized before epitaxial growth, and even if high-temperature annealing is performed, epitaxial growth Threading dislocations and stacking faults frequently occur inside, and it is difficult to obtain a good epitaxial growth film.

  Attempts have also been made to remedy this problem. For example, it has been proposed that a SiGe layer is epitaxially grown with a gradient of Ge concentration in the thickness direction, and the magnitude of strain due to a difference in lattice constant is relaxed within an allowable limit of dislocation generation.

  Another proposal based on the same idea is to form SiGe layers in multiple layers and to change the Ge concentration of each step layer step by step to suppress the occurrence of dislocations due to lattice mismatch.

  In this way, in addition to using the SiGe layer as a composition gradient layer, a buffer layer such as a silicon nitride thin film is formed as an intermediate layer to suppress the propagation of dislocations, or epitaxial growth is performed using the off-cut surface of a single crystal silicon wafer as the ground A method has been proposed.

  In the latter technique using an off-cut wafer, when dislocations are developed in the growth process of the SiGe layer, the dislocations progress not in a straight line but in an inclined direction. As a result, dislocations penetrating to the outer surface of the SiGe layer are reduced, and the dislocation density of the strained Si layer is reduced (see, for example, Patent Document 1 and Patent Document 2).

  In Patent Document 1, in a method of epitaxially growing a SiGe layer on a silicon substrate, an off-cut surface in which the silicon substrate surface on which epitaxial growth starts is inclined from the (100) plane by 6 ° to 8 ° with respect to the <100> direction is used. ing.

According to Patent Document 2, when forming a SiGe epitaxial layer having a concentration gradient in which the Ge concentration is zero at the interface and enriches outward on the silicon substrate, the (100) plane of the single crystal silicon substrate is formed. By providing an off angle of 1 ° to 8 ° in the <110> direction, the threading dislocation density can be reduced to 3 × 10 ⁶ or lower, and the surface roughness Rms can be reduced to 20 nm or lower. .

However, these proposals are not sufficient for realizing the next-generation high-speed device, and it is necessary to further reduce the density of threading dislocations, and a solution is desired.
JP 2002-356399 A US Pat. No. 6,039,803

  As described above, in the conventional technique, even if the SiGe layer is inclined while increasing the Ge concentration on the surface of the silicon substrate and the SiGe layer is epitaxially grown, there is a misfit with the silicon substrate. Then, threading dislocations occur due to the misfit and reach the surface of the strained Si layer. The threading dislocation in the strained Si layer causes a junction leakage current when the device element is formed.

  Further, the threading dislocations and the residual strain energy cause the formation of cross-hatch pattern irregularities, resulting in a problem that the surface roughness Rms of the strained Si layer grown thereon increases.

  Therefore, an effective means for suppressing generation / propagation of threading dislocation density when epitaxially growing a composition gradient SiGe layer is required.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a strained silicon wafer having a low threading dislocation density.

  In order to achieve the above object, according to one embodiment of the present invention, the crystal surface is 0.2 ° to the crystal orientation <100> direction and <0-10> direction from the plane orientation (100) plane. There is provided a strained silicon wafer in which an epitaxial layer having a lattice mismatch and a strained Si layer are sequentially laminated on a single crystal silicon substrate having an off-cut surface inclined by 1 °.

Preferably, the epitaxial layer having a lattice mismatch has a composition gradient SiGe layer having a thickness of 0.1 to 3 μm (the Ge concentration ratio x of the Si _1-x Ge _x layer is x ≦ 0.5), and a thickness thereon. It is characterized by comprising a strain relaxation Si _1-x Ge _x layer having a constant Ge composition ratio of 0.1 to 1 μm.

  The strained Si layer is a strained Si layer having a thickness of 5 to 30 nm.

  ADVANTAGE OF THE INVENTION According to this invention, the distortion silicon wafer with few unevenness | corrugations on the surface by reducing threading dislocation density can be provided.

  The present inventors have repeatedly studied the preferred orientation of the underlying single crystal silicon substrate and the dislocation propagation direction in the SiGe layer, and reduced the threading dislocation density of the SiGe layer by using an optimum off-cut surface as the silicon wafer. This is what we can do.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view of a cross section of a strained silicon wafer according to an embodiment of the present invention.

In such a strained silicon wafer, a composition gradient is formed by epitaxially growing SiGe on a surface in which an off-angle is set with respect to the preferential plane orientation of a single crystal silicon substrate as a base. That is, the composition-graded SiGe with the Ge concentration gradually increased on the off-cut surface 1 inclined by 0.2 ° to 1 ° with respect to the crystal orientation <100> direction and <0-10> direction from the silicon substrate (100) surface. A layer 2 (Ge concentration ratio x of Si _1-x Ge _x layer x ≦ 0.5) 2 is formed. The composition-graded SiGe layer 2 is preferably, for example, one having a layer thickness of 0.1 to 3 μm and a Ge concentration of 25% / μm or less and increasing from 0% to 30%.

On the composition gradient SiGe layer 2, a strain relaxation SiGe layer 3 (Si _1-x Ge _x layer, 0.1 ≦ x ≦ 0.5) is epitaxially grown. The thickness of the strain relaxation SiGe layer 3 is preferably 0.1 to 1 μm. The composition gradient SiGe layer 2 and the strain relaxation SiGe layer 3 have lattice mismatch.

  Further, a strained Si layer 4 is formed on the strain relaxation SiGe layer 3. The strained Si layer 4 preferably has a thickness of 10 nm or less.

Thus, the threading dislocation density of the strained Si layer 4 can be reduced to 10 ³ / cm ² or less by forming a thin film having a three-layer structure on the single crystal silicon substrate 1 having the off-cut surface. It was.

  As described above, the off-angle of the single crystal silicon substrate 1 is desirably 0.2 ° or more. If it exceeds 0.2 °, an atomic step of a two atomic layer (0.34 nm) with a terrace length Lnm (L = 0.34 tanθ) is developed in the <110> direction according to the off-angle θ during the SiGe epitaxial growth process. At the same time, misfit dislocations are generated and extended from the interface. This misfit dislocation is on the smooth surface (111), and is an edge dislocation whose Burgers vector direction is <110>. As the epitaxial layer grows, misfit dislocations continue to move upward and extend in the <110> direction along the terrace, resulting in a reduction in dislocations that rise toward the surface as threading dislocations.

  Further, the reason why the upper limit of the off angle is set to 1 ° is that if it is more than this, the number of edge dislocations generated from the step increases and cancels out, and conversely, the effect of converging threading dislocations is lost.

  Desirable off-angles are as described above, particularly 0.5 ° ≦ X ≦ 1 ° with respect to the X direction (<100> direction) and 0.1 ° with respect to the Y direction (<0-10> direction). If ≦ Y ≦ 1 °, there is an effect of suppressing the threading dislocation density.

  Next, an outline of a method for producing the above-described strained silicon wafer will be described. First, in order to form an SiGe epitaxial layer on a mirror-polished surface with an off-angle set, for example, a CVD method by lamp heating, a vapor phase epitaxial growth method such as a CVD method in ultra high vacuum (UHV-CVD), It can be performed by a molecular beam epitaxial growth method (MBE) or the like.

  The formation conditions vary depending on the Si: Ge composition ratio and film thickness of the SiGe layer, the film formation method, the apparatus, etc., and are set appropriately. For example, taking the CVD method by lamp heating as an example, the composition is as follows when the composition is Ge = 0.3.

Carrier gas: H ₂ , source gas: SiH ₄ , GeH ₄ , chamber pressure: 10-100 Torr, temperature: 650-680 ° C., growth rate 10-50 nm / min.

  A strained Si layer is grown on the surface of the SiGe layer thus obtained by, for example, CVD. Since the formed strained Si layer has a lattice constant different from that of the underlying SiGe layer, the strained Si layer has elastic strain and can be degenerated, so that the movement of carriers is several times faster than the unstrained state. In order to use this strained Si layer as a device active region, it is preferably formed to a thickness of, for example, 5 to 30 nm.

  Furthermore, an example of the growth conditions of single crystal Si by CVD is as follows.

Carrier gas: H ₂ , source gas: SiH ₂ Cl ₂ or SiH ₄ , chamber pressure: 10 to 760 Torr, temperature: 650 to 1000 ° C.

The above-described epitaxial layer having a lattice mismatch has a composition of Si _1-x C _x (1>x> 0.1) or Si _1-x N _x (1> x ≧ 0.1). There is a similar effect.

Specifically, a hydrocarbon-based gas can be used as the C source gas, nitrogen or NH ₃ as the N source, and hydrogen as the carrier gas.

  Examples are described below, but the present invention is not limited to these examples.

As the silicon substrate, for example, a P-type substrate added with boron in which a single crystal ingot was prepared by the Czochralski method was used. The ingot was beveled, sliced into a plate, cut to a predetermined off angle, ground, and polished to a mirror finish. The resistivity is 0.1 to 1.0 Ω · cm, and the oxygen concentration is about 15 × 10 ¹⁷ / cm ³ . This wafer was SN-1 cleaned, immersed in a 5% aqueous hydrofluoric acid solution for several minutes and rinsed with pure water. Then, the thickness of the SiGe layer having a Ge composition gradient was set to 2 μm by the method described above, and the composition of the outer surface was changed. Si ₇₀ Ge ₃₀ was used. The strain-relaxed Si ₇₀ Ge ₃₀ layer having a constant Ge composition ratio was epitaxially grown at 900 ° C. on the composition gradient SiGe layer with a thickness of 1 μm. Further, a strained Si layer was epitaxially formed at 700 ° C. by 20 nm.

  In this example, the priority surface of the underlying silicon wafer is (100). When the off angle in the <100> direction (X direction) is X = 0.1 ° and the off angle in the <0-10> direction (Y direction) is changed in the range of Y = 0.1 ° to 10 ° The change in the dislocation density that appeared through the outermost surface through the Ge layer and the strained Si layer epitaxially grown on the off-angle surface was evaluated.

FIG. 2 shows the change in threading dislocation density with off-angle. When the off angle in the wafer <0-10> direction was 0.2 ° ≦ Y ≦ 1 °, the threading dislocation density was reduced to 10 ³ / cm ² .

According to the present embodiment, a strained silicon wafer capable of forming a high-quality strained Si layer in which the threading dislocation density is suppressed to 10 ³ / cm ² or less, and capable of realizing the performance of the next generation LSI, individual semiconductor element, etc. can get.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment.

1 is a schematic cross-sectional view of a strained silicon wafer according to an embodiment of the present invention. It is a diagram which shows the relationship between a Y direction off angle and a threading dislocation density.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon substrate, 2 ... Composition gradient SiGe layer, 3 ... Strain relaxation SiGe layer, 4 ... Strain Si layer.

Claims (3)

  On the single crystal silicon substrate, the crystal surface of which is an off-cut plane inclined by 0.2 ° to 1 ° with respect to the crystal orientation <100> direction and the <0-10> direction from the plane orientation (100) plane A strained silicon wafer in which a consistent epitaxial layer and a strained Si layer are sequentially laminated. The lattice mismatched epitaxial layer is formed on the composition gradient SiGe layer having a thickness of 0.1 to 3 μm (the Ge concentration ratio x of the Si _1-x Ge _x layer is x ≦ 0.5). The strained silicon wafer according to claim 1, wherein the strained silicon wafer is a strain-relaxed Si _1-x Ge _x layer having a constant Ge composition ratio of 0.1 to 1 μm. The epitaxial layer having lattice mismatching is Si _1-x C _x (1>x> 0.1) or Si _1-x N _x (1> x ≧ 0.1). Described strained silicon wafer.

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