JP2006173323A - Method of manufacturing strained silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a strained silicon wafer capable of further reducing feed through dislocation density in a strained Si layer formed on an SiGe layer in the strained silicon wafer including the SiGe layer. <P>SOLUTION: A composition gradient SiGe layer (Ge concentration ratio x of an Si<SB>1-x</SB>Ge<SB>x</SB>layer: 0<x≤0.5) is epitaxially grown into the thickness of 0.1 to 3 μm while raising Ge concentration on a single crystal silicon substrate, on which a strained relaxation Si<SB>1-x</SB>Ge<SB>x</SB>layer is formed where a Ge composition ratio with the thickness of 0.1 to 1 μm is constant, and further a 5 to 30 nm thick first strained Si layer is formed, on which a ≤10 nm thick strained Si layer is epitaxially grown at a lower temperature than the film formation temperature of the first strained Si layer as a second strained Si layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a strained silicon wafer in which a threading dislocation density of a strained Si layer is reduced in a method of epitaxially growing a SiGe layer and a strained Si layer on a single crystal silicon substrate.

  In recent years, a strained silicon wafer has been proposed in which a SiGe layer is epitaxially grown on a single crystal silicon substrate and a strained Si layer is epitaxially grown on the SiGe layer.

  In the strained Si layer, tensile strain is caused by the SiGe layer having a larger lattice constant than Si. This strain changes the band structure of Si, and the degeneration is solved and the carrier mobility is increased.

  Therefore, by using this strained Si layer as the channel region, the carrier movement speed can be increased by 1.5 times or more compared to the case of a semiconductor substrate using normal bulk silicon.

  For this reason, strained silicon wafers are attracting attention as suitable silicon wafers for high-speed MOSFETs, MODFETs, HEMTs, and the like.

  In order to obtain a high-quality strained Si layer in the strained silicon wafer as described above, a high-quality SiGe layer on the silicon substrate, that is, a threading dislocation density is low on the silicon substrate, a strain is reduced, and a smooth surface is formed. It is necessary to epitaxially grow the SiGe layer.

  However, due to the difference in lattice constant between Si and SiGe, misfit dislocations occur during the epitaxial growth of the SiGe layer on the silicon substrate. Further, threading dislocations due to misfit dislocations reach the surface at a high density, and the dislocations propagate to the strained Si layer formed on the SiGe layer with a high density.

  Dislocations in the strained Si layer cause the junction leakage current to increase in the device element formed there. Furthermore, there arises a problem that unevenness called a cross hatch pattern is generated on the surface of the strained Si layer due to threading dislocations and residual strain energy.

  Since dislocations and surface roughness induced in the strained Si layer as the active region of the device are directly related to the quality of the device, various proposals have been made to reduce the threading dislocation density. .

For example, a SiGe layered layer (composition gradient SiGe layer) with a Ge component increased at a concentration gradient of about 25% / μm or less is epitaxially grown on a single crystal silicon substrate, and strain relaxation with a constant Ge composition ratio is performed. A method of manufacturing a strained silicon wafer in which a strained Si layer is epitaxially grown on the strain-relaxed SiGe layer after epitaxially growing the SiGe layer is disclosed (for example, see Patent Document 1). However, even if the density of threading dislocations is improved by this method, it is at most 10 ⁵ / cm ² order, and the production yield in the device process is still a concern.

Further, a SiGe relaxation layer having a constant Ge composition ratio on a step composition gradient layer of a SiGe layer with a gradually increasing Ge composition ratio on a silicon substrate, and a strained silicon having a strained Si layer thereon. It has been proposed to reduce the threading dislocation density by increasing the number of steps in the wafer (see, for example, Patent Document 2). However, even in this method, it is difficult to reduce the threading dislocation density of the strained Si layer to less than 1 × 10 ⁵ / cm ² .
Japanese Patent No. 2792785 JP 2002-118254 A

  As described above, attempts have been made to reduce the threading dislocation density in strained silicon wafers by various methods.

  However, if the threading dislocation density is high as in the prior art, the yield in the device process is greatly affected.

  The present invention has been made to solve the above technical problem, and in a strained silicon wafer having a SiGe layer, the threading dislocation density in the strained Si layer formed on the SiGe layer is further reduced. It is an object of the present invention to provide a method for producing a strained silicon wafer.

In order to achieve the above object, a strained silicon wafer manufacturing method according to the present invention includes a compositionally-graded Si _1-x Ge _x layer (0 <x ≦ 0.5) on a single crystal silicon substrate with increasing Ge concentration. A step of epitaxially growing to a thickness of 0.1 to 3 μm, and a strain relaxation Si _1-x Ge _x layer (0.1 ≦ x ≦ 0.5) having a predetermined Ge concentration is formed on the composition-gradient Si _1-x Ge _x layer to a thickness of 0.1 to A step of epitaxially growing to 1 μm, a step of epitaxially growing a first strained Si layer on the strain-relaxed Si _1-x Ge _x layer to a thickness of 5 to 30 nm, and a second on the first strained Si layer. And a step of epitaxially growing the strained Si layer to a thickness of 10 nm or less at a temperature lower than the epitaxial growth temperature of the first strained Si layer.

  The growth temperature of the first strained Si layer is preferably 800 to 900 ° C., and the growth temperature of the second strained Si layer is preferably 600 to 750 ° C.

  As described above, according to the present invention, the threading dislocation density in the strained silicon wafer can be greatly reduced, and the defect density such as stacking faults can be further reduced as compared with the conventional case. Therefore, since the strained silicon wafer according to the present invention has the high-quality strained Si layer as described above, the degree of freedom in the device process is improved and the carrier mobility is increased, and the next generation is achieved. It can be suitably used for subsequent LSIs and individual semiconductor devices.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a strained silicon wafer produced by a strained silicon wafer manufacturing method according to an embodiment of the present invention. As the single crystal silicon substrate used in the manufacturing method according to the present invention, for example, a substrate obtained by doping a nitrogen and boron, cutting out a single crystal ingot pulled up by the Czochralski method (CZ method), and slicing it is preferably used. Of course, a substrate other than the CZ substrate, for example, an FZ substrate can also be used. The surface of this single crystal silicon substrate is preferably mirror-polished.

A Si _1-x Ge _x layer is formed on the single crystal silicon substrate. The Si _1-x Ge _x layer can be a constant composition layer with a Ge concentration of a predetermined value, but in order to further reduce the dislocation density, the Ge 1 layer is directed from the single crystal silicon substrate toward the outer layer. A composition gradient layer in which the concentration x gradually increases is preferable.

In addition, the Ge concentration x in the composition gradient Si _1-x Ge _x layer is preferably 0 <x ≦ 0.5, and the Ge concentration is preferably increased with a gradient of less than 20% / μm. This is because when the Ge concentration exceeds 20% / μm, the concentration gradient is too steep, so that dislocations and defects are likely to occur during epitaxial growth.

Further, when the thickness of the composition gradient SiGe layer is less than 0.1 μm, the strain becomes insufficient, while when the thickness exceeds 3 μm, the desired amount of strain does not change so much. It is preferable that it is 1-3 micrometers.

In the case where the Si _1-x Ge _x layer is a composition gradient layer, the uppermost layer with the highest Ge concentration is formed thick in order to alleviate the strain caused by the Si _1-x Ge _x layer. Is preferred.

That is, the strain relaxation layer, on the composition graded _{Si 1-x} Ge _x layer, the Ge composition ratio has the same Ge concentration as the Ge concentration reached in the top layer of the composition gradient layer is constant strain relaxation _{Si 1-x} Ge _{The x} layer is formed by epitaxial growth.

The strain relaxation Si _1-x Ge _x layer is preferably formed with a thickness of 0.1 to 1 μm from the viewpoint of sufficiently relaxing the strain generated from the composition gradient layer.

Next, a first strained Si layer having a thickness of 5 to 30 nm is formed by epitaxial growth on the strain relaxation Si _1-x Ge _x layer. In addition, as a growth temperature at this time, for example, a relatively high temperature of 800 to 900 ° C. is preferable.

Next, a second strained Si layer having a thickness of 10 nm or less is epitaxially grown on the first strained Si layer. The deposition temperature of the second strained Si layer is lower than the deposition temperature of the first strained Si layer, and preferably 600 to 750 ° C. As a result, pseudo-lattice growth is maintained in the second strained Si layer, and the threading dislocation density can be reduced to 1 × 10 ³ / cm ² or less.

As an epitaxial growth method of the Si _1-x Ge _x layer and the Si layer, for example, a vapor phase epitaxial growth method such as a CVD method by lamp heating, a CVD method in ultra high vacuum (UHV-CVD), or a molecular beam epitaxial growth method. (MBE) or the like.

The growth conditions vary depending on the composition ratio of Si and Ge of the SiGe layer to be grown, the film thickness, the growth method used, the apparatus, and the like, and are set as appropriate. For example, carrier gas: H ₂ , source gas: SiH ₄ , GeH _{4. The} chamber pressure is 1000 to 10000 Pa, and in the case of forming the Si _1-x Ge _x layer, the higher the growth temperature, the more effective the reduction of the dislocation density. 1100 ° C.

The surface of the SiGe layer is preferably smoothed by, for example, high-temperature hydrogen heat treatment at 850 to 1200 ° C. and a pressure of about 1000 to 100000 Pa in an H ₂ stream.

  Thereby, the surface of the strained Si layer formed thereon becomes smooth, and the occurrence of dislocations is also suppressed.

In addition, the strained Si layer is formed by epitaxially growing a single crystal Si layer by, for example, a CVD method on the Si _1-x Ge _x layer formed as described above.

The strained Si layer is formed by the CVD method under the conditions of, for example, carrier gas: H ₂ , source gas: SiH ₂ Cl ₂ or SiH ₄ , chamber pressure: 1000 to 100000 Pa, and temperature: 600 to 1000 ° C.

On the other hand, the composition of the composition gradient epitaxial layer and the strain relaxation epitaxial layer is Si _1-x C _x (1>x> 0.1) or Si _1-x N _x (1> x ≧ 0.1). There is a great effect.

Specifically, a hydrocarbon-based gas was used as the C source gas, nitrogen or NH ₃ was used as the N source, and hydrogen was used as the carrier gas.

  A strained silicon wafer on which a strained Si layer having a low threading dislocation density as described above is formed can be used as a suitable substrate for forming a high-speed device because the carrier movement is accelerated in the strained Si layer. it can.

  Examples of the present invention will be described below, but the present invention is not limited to the description of the examples.

(Examples and comparative examples)
When forming a strained silicon wafer, a P-type, resistivity 0.1-1.0 Ω / cm, plane-oriented (100) mirror-polished silicon wafer prepared by slicing a single crystal ingot pulled up by the Czochralski method Provided. The initial oxygen concentration of the wafer was 15 × 10 ¹⁷ atoms / cm ³ or less. First, a composition-graded SiGe layer having a composition on the outermost surface of Si ₇₀ Ge ₃₀ was epitaxially formed on the mirror surface of the wafer while increasing the Ge concentration toward the outer layer by the CVD method described above, and grown to a thickness of 2 μm. A strain-relaxed Si ₇₀ Ge ₃₀ layer having a constant Ge composition ratio with a thickness of 1 μm was epitaxially formed thereon at 900 ° C. On top of this, a first strained Si layer was epitaxially produced at 800 ° C. to form a layer having a thickness of 20 nm. Further, on this first strained Si layer, a second strained Si layer was formed to a thickness of 10 nm at various epitaxial growth temperatures.

FIG. 2 shows the relationship between the epitaxial film formation temperature and the threading dislocation density when the generation temperature of the second strained Si layer was changed from 500 to 900 ° C. As apparent from FIG. 2, the threading dislocation density was 10 ³ / cm ² or less by setting the epitaxial growth temperature of the second strained Si layer to 600 to 750 ° C. It has been found that threading dislocation density increases at a low epitaxial growth temperature of 550 ° C. or lower.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment.

It is a schematic sectional drawing of the distortion silicon wafer by the manufacturing method of the distortion silicon wafer which concerns on embodiment of this invention. It is a diagram which shows the relationship between a threading dislocation density and the epitaxial growth temperature of a 2nd strained Si layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon substrate, 2 ... Composition gradient SiGe layer, 3 ... Relaxation SiGe layer,
4 ... 1st strained Si layer, 5 ... 2nd strained Si layer.

Claims (3)

On a single crystal silicon substrate,
A step of epitaxially growing a composition-graded Si _1-x Ge _x layer (0 <x ≦ 0.5) with increasing Ge concentration to a thickness of 0.1 to 3 μm;
Epitaxially growing a strain relaxation Si _1-x Ge _x layer (0.1 ≦ x ≦ 0.5) having a predetermined Ge concentration on the composition-graded Si _1-x Ge _x layer to a thickness of 0.1 to 1 μm;
Epitaxially growing a first strained Si layer on the strain relaxed Si _1-x Ge _x layer to a thickness of 5 to 30 nm;
Epitaxially growing a second strained Si layer on the first strained Si layer to a thickness of 10 nm or less at a temperature lower than the epitaxial growth temperature of the first strained Si layer;
A method for producing a strained silicon wafer, comprising:   2. The strained silicon wafer according to claim 1, wherein a growth temperature of the first strained Si layer is 800 to 900 ° C., and a growth temperature of the second strained Si layer is 600 to 750 ° C. 3. Method. The composition of the composition gradient epitaxial layer and the strain relaxation epitaxial layer is Si _1-x C _x (1>x> 0.1) or Si _1-x N _x (1> x ≧ 0.1). A method for producing a strained silicon wafer according to claim 1.

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