JP2006210386A - Capacitor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the composition deviation of a capacitance insulating film by suppressing the thermal diffusion of a metal element for composing the capacity insulating film into a lower electrode, when film-forming the capacity insulating film made of a ferroelectric or a high dielectric by using a method where temperature in film formation in an MOCVD method, or the like becomes approximately 300°C or higher. <P>SOLUTION: In a capacitor, where the lower electrode 10, the capacity insulating film 11, and an upper electrode 12 are formed in this order along at least the sidewall section and bottom section of a hole 8 formed in a first interlayer insulating film 7, a sacrifice layer 9 containing at least one type of element in metal elements for composing the capacity insulating film 11 is formed between a part formed at the sidewall section of the hole 8 in the lower electrode 10 and the first interlayer insulating film 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a capacitive element having a concave three-dimensional structure provided with a capacitive insulating film made of a ferroelectric or a high dielectric, and a method for manufacturing the same.

  In recent years, research and development on ferroelectrics or high-dielectrics having spontaneous polarization characteristics has been actively conducted with the aim of putting RAMs that can perform writing and reading operations at a high speed at a low voltage that has not been conventionally possible. ing. In particular, in order to realize a megabit-class semiconductor memory device mounted on an LSI configured with a CMOS having a design rule of 0.18 μm or less, a three-dimensional structure capable of realizing a large capacity even in a small area. It is necessary to develop a capacitive element. Since the capacitive element having this three-dimensional structure mainly has a concave three-dimensional structure, the height of the capacitive element is much higher than the width of the capacitive element.

  Thus, in the case of a capacitive element having a three-dimensional structure, it is necessary to form a ferroelectric thin film or a high dielectric thin film in a portion where a concave portion or a convex portion is present. The MOCVD method (Metal Organic Chemical Vapor Deposition method) excellent in step coverage is mainly used, not the MOD method (Metal Organic Decomposition method) in which an organometallic solution used in a capacitive element having a structure is applied. A sputtering method or an ALD method (Atomic Layer Deposition method) may be used.

  The temperature at the time of forming a ferroelectric thin film or a high dielectric thin film by applying an organometallic solution containing a ferroelectric or high dielectric component using the MOD method is room temperature. On the other hand, the temperature when forming a ferroelectric thin film or a high dielectric thin film using the MOCVD method is about 300 ° C. or higher. Therefore, as one of the most important issues when forming a ferroelectric thin film or a high dielectric thin film, each metal constituting the ferroelectric thin film or the high dielectric thin film has a desired composition ratio immediately after the film formation. The point is whether or not.

  A conventional example will be described below with reference to the drawings.

First, a first conventional example will be described with reference to FIG. 8 (see, for example, Patent Document 1). FIG. 8 shows the structure of a capacitive element using a ferroelectric thin film made of a Pb (Zr _x Ti _1-x ) O ₃ (where 0 ≦ x ≦ 1) film formed by MOCVD as a capacitive insulating film. It is a principal part sectional view shown.

As shown in FIG. 8, a thermal oxide film 102 having a film thickness of 200 nm is formed on the silicon substrate 101, and a film thickness of 30 nm is formed on the thermal oxide film 102 in order from the lower layer. A lower electrode made of the Ti film 103 and the Pt film 104 having a thickness of 200 nm is formed. On the Pt film 104, a buffer layer 105 made of a TiO ₂ film or a PbTiO ₃ film and having a thickness of about 10 nm is formed. A ferroelectric thin film 106 made of a Pb (Zr _x Ti _1-x ) O ₃ (where 0 ≦ x ≦ 1) film having a thickness of 300 nm is formed on the buffer layer 105 by MOCVD. Is formed.

The buffer layer 105 in the first conventional example is a ferroelectric thin film 106 made of a Pb (Zr _x Ti _1-x ) O ₃ (where 0 ≦ x ≦ 1) film at about 600 ° C. by MOCVD. It has the role of preventing the reaction between Pb and Pt that occurs when the film is formed, and suppressing the characteristic deterioration caused by the alloy made of Pb and Pt.

Next, a second conventional example will be described with reference to FIG. 9 (see, for example, Patent Document 2). FIG. 9 is a cross-sectional view of the main part showing the structure of a capacitive element using a ferroelectric thin film made of a Bi ₄ Ti ₃ O ₁₂ film formed by MOCVD as a capacitive insulating film. In FIG. 9, the same reference numerals as those shown in FIG. 8 are given to the portions of the first conventional example that are common to FIG.

As shown in FIG. 9, a thermal oxide film 102 having a thickness of 200 nm is formed on a silicon substrate 101, and a film thickness of 20 nm is sequentially formed on the thermal oxide film 102 from the lower layer. An adhesive layer 107 made of a Ta film and a lower electrode made of a Pt film oriented in the (111) plane are formed. A buffer layer 109 made of a TiO ₂ film having a thickness of 20 nm is formed on the lower electrode 108. A ferroelectric thin film 110 made of a Bi ₄ Ti ₃ O ₁₂ film having a thickness of about 100 nm is formed on the buffer layer 109 by MOCVD. On the ferroelectric thin film 110, an upper electrode 111 made of a Pt film is formed.

The buffer layer 109 in the second conventional example promotes densification and surface smoothing of the ferroelectric thin film 110 formed on the buffer layer 109, and leak current due to pinholes or surface irregularities. It has a role to suppress the rise of
Japanese Patent Laid-Open No. 6-349324 (page 2-3 [0014] to [0025], FIG. 2, page 3-4 [0026] to [0030], and FIG. 3) JP-A-8-161933 (6th page [0043] to [0046] and FIG. 1)

  However, in the case of the first and second conventional examples described above, a capacitive element having a three-dimensional structure using a ferroelectric thin film or a high dielectric thin film formed by MOCVD as a capacitive insulating film is a capacitive element. We have found that there is a high probability that the desired characteristics will not be obtained. Hereinafter, this reason will be described in detail.

  First, in the case of forming a capacitive element having a planar structure, as described above, an organic metal solution is applied by using the MOD method to form a capacitive insulating film made of a ferroelectric thin film or a high dielectric thin film. In this MOD method, the temperature at which the organometallic solution containing the ferroelectric or high dielectric component is applied is room temperature. For this reason, the composition of the thin film after coating does not deviate from the desired composition, that is, the composition in the organometallic solution. Also, the RTA (Rapid Thermal Annealing) method using an infrared lamp is used for the heat treatment in an oxygen atmosphere of 650 ° C. to 800 ° C. necessary for crystallization of the coated thin film, so that it takes about 1 minute. During the heat treatment, the metal element constituting the capacitive insulating film is thermally diffused into the lower electrode, and the ferroelectric thin film or the high dielectric thin film hardly causes a composition shift.

  On the other hand, when a capacitive insulating film made of a ferroelectric thin film or a high dielectric thin film is formed by MOCVD, sputtering, or ALD, the temperature during film formation is about 300 ° C. or higher. Since the film speed is as low as about 1 nm / min to 20 nm / min, the metal element constituting the capacitive insulating film is thermally diffused into the lower electrode during the film formation, and the ferroelectric thin film or the high dielectric thin film causes a composition shift. End up.

  Incidentally, as a solution to the composition shift of the ferroelectric thin film or the high dielectric thin film, the first conventional example or the second conventional example has been proposed. As described above, the lower electrode and the capacitive insulating film In the structure in which the buffer layer is interposed therebetween, a new problem occurs. That is, since the buffer layer is not composed of a ferroelectric material or a high dielectric material, the capacitive element in which the buffer layer is interposed between the lower electrode and the capacitive insulating film is a ferroelectric material or a high dielectric material. Thus, a capacitor element made of a capacitor insulating film having a low dielectric constant is connected in series to the capacitor element formed. When a voltage is applied to the capacitor having such a structure, most of the voltage is applied to the capacitor insulating film having a low dielectric constant. As a result, a desired voltage is not applied to the capacitor insulating film made of a ferroelectric or a high dielectric, which originally has to be applied with a voltage and must contribute to the operation of the memory device, and is likely to malfunction.

  In particular, since the capacitive element having a three-dimensional structure is used for a megabit-class storage device mounted on an LSI composed of a CMOS of 0.18 μm or less, it is necessary to reduce the plane size, and the power supply voltage Is limited to 2V or less. Therefore, the thickness of the capacitive insulating film used for the capacitive element having a three-dimensional structure is desirably set to 100 nm or less, ideally in the range of 20 nm to 60 nm. In this case, when the buffer layers described in the first and second conventional examples are employed, as described above, the ferroelectric layer or the high dielectric material, which is originally applied with a voltage and has to contribute to the operation as a memory device, is used. A desired voltage is not applied to the capacitor insulating film, and the possibility of malfunctioning is very high.

  In other words, a capacitive element having a three-dimensional structure using a capacitive insulating film made of a ferroelectric or high dielectric formed at a high temperature of about 300 ° C. or higher by using the MOCVD method or the like is improved in performance and reliability. In the past, there was a problem that it could not be realized.

  In view of the above, an object of the present invention is to provide a capacitive element having a three-dimensional structure having excellent characteristics by a structure that can be easily realized.

  In order to achieve the above-mentioned purpose, as a result of intensive studies, we have made a capacitive insulation by providing a sacrificial layer containing a part of the metal element constituting the capacitive insulating film as a part of the base of the lower electrode. It has been found that the compositional deviation of the film can be prevented. That is, when a capacitive insulating film is formed on the lower electrode at about 300 ° C. or higher using the MOCVD method or the like, the thermal diffusion of the metal element from the sacrificial layer into the lower electrode occurs, and the capacitance contained in the lower electrode By increasing the concentration of the metal element constituting the insulating film, the amount of thermal diffusion of the metal element constituting the capacitive insulating film from the capacitive insulating film into the lower electrode is significantly reduced. Therefore, unlike the conventional example, a capacitive insulating film made of a ferroelectric or high dielectric having a desired composition can be realized without providing a capacitive film having a low dielectric constant such as a buffer layer.

  The present invention has been made in view of the above knowledge, and specifically, the capacitive element according to the present invention has a lower portion so as to extend along at least the side wall and bottom of the hole formed in the first interlayer insulating film. A capacitive element in which an electrode, a capacitive insulating film, and an upper electrode are formed in this order, and a capacitive insulating film is provided between a portion of the lower electrode formed on the sidewall of the hole and the first interlayer insulating film. A sacrificial layer containing at least one element among the metal elements constituting is formed.

  According to the capacitive element according to the present invention, since it has a configuration including a sacrificial layer containing at least one element of the metal elements constituting the capacitive insulating film, the capacitance is formed when the capacitive insulating film is formed. It is possible to prevent the elements constituting the insulating film from thermally diffusing to the lower electrode disposed on the side wall of the hole that occupies most of the area of the capacitor. Therefore, it is possible to realize a capacitive insulating film having a desired composition in which composition deviation is prevented. Therefore, a large-capacity capacitive element having high performance and high reliability can be realized in a small area.

In the capacitor element according to the present invention, the capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3, (Bi x La 1-x) 4 Ti 3 In the case of being made of any one material selected from the group consisting of O ₁₂ and (Ba _x Sr _1-x ) TiO ₃ (where 0 ≦ x ≦ 1), a strong composition having a desired composition is obtained. A capacitive insulating film made of a dielectric film or a high dielectric film can be realized.

  In the capacitive element according to the present invention, the sacrificial layer may be one kind of metal selected from the group consisting of Bi, Pb, Ta, Nb, Zr, Ti, La, Ti, Sr, and Ba, or a plurality of kinds. In this case, the sacrificial layer is preferably made of a metal oxide.

  In the capacitive element according to the present invention, the sacrificial layer is preferably an insulator.

  When the sacrificial layer having the above structure is used, thermal diffusion of the metal element from the capacitive insulating film to the lower electrode can be prevented.

  In the capacitive element according to the present invention, the thickness of the sacrificial layer is preferably 1 nm or more and 50 nm or less in view of the effect of suppressing the hole diameter and the composition deviation of the capacitive insulating film.

  In the capacitive element according to the present invention, the sacrificial layer is further formed in a region below the portion of the lower electrode that exists at the bottom of the hole, excluding a region where a potential is supplied from below to the lower electrode. It is preferable that

  This increases the amount of thermal diffusion of the metal element from the sacrificial layer to the lower electrode, so that the amount of thermal diffusion of the metal element from the capacitive insulating film to the lower electrode can be reduced. For this reason, composition deviation is prevented more and a capacitive insulating film having a more desired composition can be realized. Therefore, a large-capacity capacitive element having higher performance and higher reliability can be realized in a small area.

  In the capacitive element according to the present invention, an electrode including a conductive barrier layer having a barrier property against oxygen or hydrogen may be formed so as to be in contact with a lower portion of a portion existing at the bottom of the hole in the lower electrode. preferable.

  In this way, for example, during high-temperature oxygen annealing required for crystallization of the capacitive insulating film, the surface of the plug connected to the electrode can be prevented from being oxidized, and the barrier performance against hydrogen diffusion from below can be enhanced. Thus, it is possible to realize a capacitor element having a structure capable of preventing characteristic deterioration.

  In the capacitive element according to the present invention, the portion of the lower electrode existing at the bottom of the hole is connected to the semiconductor via a plug formed in the second interlayer insulating film between the semiconductor substrate and the first interlayer insulating film. It is preferable that the transistor is electrically connected to the source or drain of the transistor formed in the surface layer portion of the substrate.

  A first method for manufacturing a capacitive element according to the present invention includes a step of forming a first interlayer insulating film on a substrate, a step of forming a hole in the first interlayer insulating film, and a sacrifice on a side wall portion of the hole. A step of forming a layer, a step of forming a lower electrode on the bottom of the hole and a side surface of the sacrificial layer, a step of forming a capacitive insulating film made of a ferroelectric or a high dielectric so as to cover the surface of the lower electrode, A step of forming an upper electrode so as to cover the surface of the capacitor insulating film, and the sacrificial layer includes at least one element of metal elements constituting the capacitor insulating film.

  According to the first method for manufacturing a capacitive element according to the present invention, the sacrificial layer containing at least one element of the metal elements constituting the capacitive insulating film is formed. It is possible to prevent the elements constituting the insulating film from thermally diffusing to the lower electrode disposed on the side wall of the hole that occupies most of the area of the capacitor. For this reason, it is possible to form a capacitive insulating film having a desired composition in which composition deviation is prevented. Therefore, a high-capacity capacitive element having high performance and high reliability can be formed with a small area and an easy method.

In the first method for manufacturing a capacitive element according to the present invention, the step of forming the capacitive insulating film is performed using a metal organic chemical vapor deposition method (MOCVD method), an atomic layer deposition method (ALD method), or a sputtering method. _{, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3, (Bi x La 1-x) 4 Ti 3 O 12 _{and, (Ba x Sr 1-x} ) In the case of including a step of forming a capacitive insulating film made of any one material selected from the group consisting of TiO ₃ (wherein x satisfies the relational expression of 0 ≦ x ≦ 1) A ferroelectric material having a desired composition by preventing thermal diffusion of a metal element from the capacitive insulating film to the lower electrode, which is a problem when a capacitive insulating film is formed on the lower electrode using MOCVD A capacitive insulating film made of a film or a high dielectric film can be formed.

  In addition, a ferroelectric having a desired composition can be obtained by preventing thermal diffusion of a metal element from the capacitive insulating film to the lower electrode, which is particularly problematic when the temperature during film formation is 300 ° C. or higher. A capacitive insulating film made of a body film or a high dielectric film can be formed.

  In the first method for manufacturing a capacitive element according to the present invention, the step of forming the sacrificial layer includes a step of depositing a thin film for forming the sacrificial layer on the first interlayer insulating film including the side wall portion and the bottom portion of the hole. And a step of forming a sacrificial layer by etching back the thin film for forming the sacrificial layer. If it does in this way, a sacrificial layer can be formed in the side wall part of a hole by an easy method.

  The step of depositing the thin film for forming the sacrificial layer is preferably performed using a metal organic chemical vapor deposition method (MOCVD method), an atomic layer deposition method (ALD method), or a sputtering method. In this way, a thin film for forming a sacrificial layer can be formed with good step coverage.

  In the first method for manufacturing a capacitive element according to the present invention, the sacrificial layer is any one selected from the group consisting of Bi, Pb, Ta, Nb, Zr, Ti, La, Ti, Sr, and Ba. It is preferable that a kind of metal or a plurality of kinds of metals are included. In this case, the sacrificial layer is preferably made of a metal oxide.

  In the first method for manufacturing a capacitive element according to the present invention, the sacrificial layer is preferably an insulator.

  When the sacrificial layer having the above structure is used, thermal diffusion of the metal element from the capacitive insulating film to the lower electrode can be prevented.

  In the first method for manufacturing a capacitive element according to the present invention, the temperature is 300 ° C. or higher and 800 ° C. or lower after the step of forming the lower electrode and before the step of forming the capacitive insulating film. It is preferable to further include a step of diffusing the metal element constituting the sacrificial layer into the lower electrode by performing heat treatment in the temperature range.

  In this case, since at least one element constituting the capacitive insulating film is thermally diffused from the sacrificial layer into the lower electrode before the capacitive insulating film is formed, the capacitive insulation in the formation of the capacitive insulating film is performed. The thermal diffusion of the metal element from the film to the lower electrode can be further prevented. For this reason, a capacitive insulating film having a more desired composition can be formed. Therefore, a large-capacity capacitive element having higher performance and higher reliability can be formed with a small area and an easy method.

  In the first method for manufacturing a capacitive element according to the present invention, a conductive barrier layer having a barrier property against oxygen or hydrogen is included on the substrate before the step of forming the first interlayer insulating film. The step of forming the first interlayer insulating film further includes a step of forming an electrode, and the step of forming the first interlayer insulating film is a step of forming the first interlayer insulating film on the substrate so as to cover the electrode including the conductive barrier layer, The step of forming the hole is a step of forming a hole in the first interlayer insulating film so as to expose the upper surface of the electrode including the conductive barrier layer, and the step of forming the lower electrode is a bottom portion of the hole. In addition, it is preferable to form a lower electrode on the side surface of the sacrificial layer so as to be in contact with the upper portion of the electrode including the conductive barrier layer.

  In this way, for example, during high-temperature oxygen annealing required for crystallization of the capacitive insulating film, the surface of the plug connected to the electrode can be prevented from being oxidized, and the barrier performance against hydrogen diffusion from below can be enhanced. Thus, it is possible to realize a capacitor element having a structure capable of preventing characteristic deterioration.

  The second method for manufacturing a capacitive element according to the present invention includes a step of forming an electrode on a substrate, a step of forming a first interlayer insulating film on the substrate so as to cover the electrode, and a first interlayer insulation. Forming a hole in the film so that the upper surface of the electrode is exposed; depositing a thin film for forming a sacrificial layer on the first interlayer insulating film including the bottom and side walls of the hole; Forming a conductive film on the thin film for forming the sacrificial layer; and etching back the conductive film and the thin film for forming the sacrificial layer, so that the sacrificial layer and the part of the bottom of the hole The lower electrode is formed in the same process, and the upper surface of the electrode including the conductive barrier layer exposed during the etch back is sputter etched to sacrifice the metal constituting the electrode including the conductive barrier layer. Layer formed at the bottom of the hole in the layer. Forming a connection electrode that adheres to the edge surface of the substrate and connects the lower electrode and the electrode including the conductive barrier layer; and a portion exposed at the bottom of the hole in the electrode including the conductive barrier layer; Forming a capacitor insulating film made of a ferroelectric or high dielectric so as to cover at least the surface of the connection electrode and the surface of the lower electrode, and forming an upper electrode so as to cover the surface of the capacitor insulating film. The sacrificial layer includes at least one element of metal elements constituting the capacitor insulating film.

  According to the second method for manufacturing a capacitive element according to the present invention, as compared with the first method for manufacturing a capacitive element according to the present invention, the sacrifice including at least one element of the metal elements constituting the capacitive insulating film. By forming the layer not only on the side wall portion of the hole but also on a part of the bottom portion, the element constituting the capacitive insulating film occupies most of the area of the capacitive element when forming the capacitive insulating film. It is possible to further prevent thermal diffusion to the lower electrode disposed in the part. For this reason, a capacitive insulating film having a more desired composition can be formed. Therefore, a large-capacity capacitive element having higher performance and higher reliability can be formed with a small area and an easy method.

  In the second method for manufacturing a capacitive element according to the present invention, the electrode preferably includes a conductive barrier layer having a barrier property against oxygen or hydrogen.

  In this way, for example, during high-temperature oxygen annealing required for crystallization of the capacitive insulating film, the surface of the plug connected to the electrode can be prevented from being oxidized, and the barrier performance against hydrogen diffusion from below can be enhanced. Thus, it is possible to realize a capacitor element having a structure capable of preventing characteristic deterioration.

  According to the capacitive element and the method for manufacturing the same according to the present invention, by providing a sacrificial layer containing a part of the metal element constituting the capacitive insulating film as a part of the base of the lower electrode, the compositional deviation of the capacitive insulating film is reduced. Can be prevented. That is, for example, when a capacitive insulating film is formed on the lower electrode at about 300 ° C. or more using the MOCVD method or the like, thermal diffusion of the metal element from the sacrificial layer into the lower electrode occurs and is included in the lower electrode By increasing the concentration of the metal element constituting the capacitive insulating film, the amount of thermal diffusion of the metallic element constituting the capacitive insulating film from the capacitive insulating film into the lower electrode is greatly reduced. Therefore, a capacitive insulating film made of a ferroelectric or high dielectric having a desired composition can be realized, and a capacitive element having a three-dimensional structure with excellent characteristics can be provided with a structure that can be easily realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A semiconductor memory device using a capacitive element having a three-dimensional structure according to the first embodiment of the present invention will be described below.

  FIG. 1 is a cross-sectional view of a principal part showing the structure of a semiconductor memory device using a capacitive element having a three-dimensional structure according to the first embodiment of the present invention.

As shown in FIG. 1, a gate 3 is formed in the element formation region partitioned by the element isolation region 2 on the semiconductor substrate 1, and around the gate 3 in the surface layer portion of the semiconductor substrate 1, An active region 4 is formed. A first interlayer insulating film 5 made of SiO ₂ or SiN is formed on the entire surface of the semiconductor substrate 1 so as to cover the element isolation region 2, the gate 3 and the active region 4. In the first interlayer insulating film 5, a plug contact 6 made of tungsten or low-resistance polysilicon doped with n-type impurities and having a lower end connected to the active region 4 is formed.

A second interlayer insulating film 7 made of SiO ₂ or SiN is formed on the first interlayer insulating film 5 and the plug contact 6, and the plug contact is formed on the second interlayer insulating film 7. A hole 8 exposing the upper surface of 6 is formed. Here, in order to increase the capacitance of the capacitive element, it is desirable that the thickness of the second interlayer insulating film 7 is as thick as possible, but in the present embodiment, the thickness of the second interlayer insulating film 7 is 1 μm. That's it. Further, the diameter of the hole 8 is assumed to be in the range of 0.2 μm or more and 1 μm or less, and in the present embodiment, the diameter is about 0.6 μm. A capacitive element having a three-dimensional structure, which will be described later, is formed using the bottom and side walls of the hole 8.

Further, the side wall of the hole 8 is made of a material containing at least one of the metal elements constituting the capacitive insulating film 11 made of a ferroelectric or high dielectric, which will be described later, here, a metal oxide containing Bi. A sacrificial layer 9 made of a material is formed. Examples of the material constituting the sacrificial layer 9 include Bi _x O _y (where 0 <x ≦ 1, 0 <y ≦ 1), Bi _x Ta _y O _z (where 0 <x ≦ 1, 0). <Y ≦ 1, 0 <z ≦ 1) or SrBi ₂ (Ta _x Nb _1-x ) O ₉ (where 0 ≦ x ≦ 1) is used. Further, the thickness of the sacrificial layer 9 is set in a range of 1 nm or more and 50 nm or less in view of the effect of suppressing the diameter of the hole 8 and the composition deviation of the capacitive insulating film 11.

A lower electrode 10 is formed on the bottom of the hole 8 and on the surface of the sacrificial layer 9. Here, as a material constituting the lower electrode 10, a conductive material containing a noble metal such as Pt, Ir, IrO ₂ , Ru, or RuO ₂ or an oxide thereof is used. The thickness of the lower electrode 10 is assumed to be in the range of 10 nm or more and 50 nm or less. In this embodiment, IrO ₂ is used as the material of the lower electrode 10 and its film thickness is 30 nm.

On the lower electrode 10 and the second interlayer insulating film 7, a ferroelectric or high-dielectric material such as SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is formed so as to cover the surface of the lower electrode 10. A capacitor insulating film 11 made of (where 0 ≦ x ≦ 1) is formed. The capacitor insulating film 11 is formed by a film forming method with good step coverage of the recesses, that is, the MOCVD method. Further, the film forming temperature is about 300 ° C. or higher. Here, since the sacrificial layer 9 is made of a material containing at least one element among the metal elements constituting the capacitive insulating film 11, the metal element constituting the sacrificial layer 9 is formed when the capacitive insulating film 11 is formed. By thermally diffusing to the lower electrode 10, the lower electrode 10 contains a large amount of metal elements constituting the capacitive insulating film 11. For this reason, when the capacitor insulating film 11 is formed, the concentration at which the metal element constituting the capacitor insulating film 11 is thermally diffused from the capacitor insulating film 11 to the lower electrode 10 is higher than that in the case where the sacrificial layer 9 is not formed. Greatly reduced. Therefore, the capacitor insulating film 11 having a desired composition can be easily realized. The film thickness of the capacitive insulating film 11 is in the range of 12.5 nm or more and 100 nm or less. In the present embodiment, the thickness of the capacitive insulating film 11 is 50 nm.

An upper electrode 12 is formed on the capacitor insulating film 11 so as to cover the surface thereof. Here, as a material constituting the upper electrode 12, a conductive material containing a noble metal such as Pt, Ir, IrO ₂ , Ru, or RuO ₂ or an oxide thereof is used. The film thickness of the upper electrode 12 is assumed to be in the range of 10 nm or more and 50 nm or less. In this embodiment, IrO ₂ is used as the material of the upper electrode 12, and the film thickness is 30 nm. With the above configuration, the capacitive element 13 having a three-dimensional structure is completed.

  As described above, in the semiconductor memory device including the capacitive element having the concave three-dimensional structure according to the first embodiment of the present invention, a part of the hole 8 occupies a considerable area of the capacitive element 13 in the present embodiment. Since the sacrificial layer 9 including a part or all of the metal elements constituting the capacitive insulating film 11 is formed on the side wall portion of the hole 8, the capacitive insulating film 11 is formed when the capacitive insulating film 11 is formed. Since the constituent elements can be prevented from thermally diffusing to the lower electrode 9, compositional deviation of the capacitive insulating film 11 made of a ferroelectric or high dielectric can be prevented. That is, in the conventional example, when the capacitor insulating film 11 is formed using the MOCVD method or the like that is formed at a temperature of 300 ° C. or higher, the metal element constituting the capacitor insulating film 11 is thermally diffused to the lower electrode 10. However, according to the first embodiment of the present invention, this problem can be solved. In this way, the capacitive element 13 having excellent characteristics can be realized with a structure that can be easily realized.

  A method for manufacturing a semiconductor memory device using the capacitive element having the three-dimensional structure shown in FIG. 1 will be described below.

  2A to 2C and FIGS. 3A and 3B are cross-sectional views illustrating a method for manufacturing a semiconductor memory device including a capacitive element having a three-dimensional structure according to the first embodiment of the present invention. FIG.

First, as shown in FIG. 2A, after a gate 3 is formed in an element formation region partitioned by an element isolation region 2 on the semiconductor substrate 1, the surface layer portion of the semiconductor substrate 1 is formed using the gate 3 as a mask. The active region 4 is formed. Subsequently, a first interlayer insulating film 5 made of SiO ₂ or SiN is formed on the entire surface of the semiconductor substrate 1 by CVD so as to cover the element isolation region 2, the gate 3 and the active region 4. Subsequently, after opening a contact hole in the first interlayer insulating film 5, a plug contact 6 made of tungsten or low resistance polysilicon doped with n-type impurities is formed in the contact hole. .

Next, as shown in FIG. 2B, after the second interlayer insulating film 7 made of SiO ₂ or SiN is formed on the first interlayer insulating film 5 and the plug contact 6 by the CVD method, A hole 8 exposing the upper surface of the plug contact 6 is opened in the second interlayer insulating film 7.

  Next, as shown in FIG. 2C, a metal oxide containing Bi constituting a sacrificial layer 9 to be described later is formed on the bottom and side walls of the hole 8 and the second interlayer insulating film 7 by MOCVD. A thin film is deposited. Although the MOCVD method is used here, an ALD method or a sputtering method can also be used. Subsequently, the sacrificial layer 9 is formed only on the side wall of the hole 8 by etching back the thin film. Here, a gas containing chlorine or fluorine is used for etch back.

Next, as shown in FIG. 3A, Pt, Ir, IrO ₂ , Ru, or Ru are formed on the bottom of the hole 8, the surface of the sacrificial layer 9, and the surface of the second interlayer insulating film 7 by sputtering. After depositing a conductive material containing a noble metal such as RuO ₂ or its oxide, the conductive material is etched to form a lower electrode 10 that covers at least the surface of the sacrificial layer 9 and the bottom of the hole 8.

Next, as shown in FIG. 3B, SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ is formed so as to cover the surface of the second interlayer insulating film 7 and the surface of the lower electrode 10 by MOCVD. A capacitive insulating film 11 made of (0 ≦ x ≦ 1) is formed. As a film forming method, an ALD method or a sputtering method can be used instead of the MOCVD method. In forming the capacitive insulating film 11 using any of these methods, the film forming temperature is about 300 ° C. or higher. Here, in the conventional example, at this film formation temperature, the metal element constituting the capacitive insulating film 11, Bi in the case of the present embodiment, is thermally diffused to the lower electrode 10, whereby the capacitive insulating film 11. There was a possibility of causing a composition shift, that is, a decrease in Bi composition. However, in this embodiment, since the sacrificial layer 9 containing Bi is formed, Bi constituting the sacrificial layer 9 is also thermally diffused from the sacrificial layer 9 to the lower electrode 10 when the capacitor insulating film 11 is formed. As a result, the Bi concentration inside the lower electrode 10 increases. For this reason, the amount of Bi thermally diffused from the capacitive insulating film 11 to the lower electrode 10 is reduced. Therefore, a composition shift of the capacitor insulating film 11 can be prevented. In addition, before the capacitor insulating film 11 is formed, heat treatment is performed in a range of 300 ° C. or more and 800 ° C. or less, so that the metal element constituting the sacrifice layer 9 is transferred from the sacrifice layer 9 to the lower electrode 10 in advance. Thermal diffusion is also possible. In this embodiment, heat treatment is performed using the RTA method at 650 ° C. for 1 minute in an oxygen atmosphere. Thereby, the effect of preventing the composition deviation of the capacitive insulating film 11 can be enhanced. Subsequently, the upper electrode 12 made of a conductive material containing a noble metal such as Pt, Ir, IrO ₂ , Ru, or RuO ₂ or an oxide thereof is formed on the surface of the capacitive insulating film 11 by sputtering. Subsequently, for the purpose of crystallizing the capacitor insulating film 11, heat treatment is performed using an RTA method in an oxygen atmosphere at a temperature of 650 ° C. or higher and 800 ° C. or lower for about 1 minute. Through the above steps, the capacitive element 13 having a three-dimensional structure is completed.

  As described above, in the method for manufacturing the semiconductor memory device including the capacitive element having the concave three-dimensional structure according to the first embodiment of the present invention, a part of the hole 8, that is, the considerable amount of the capacitive element 13 in the present embodiment. When the capacitor insulating film 11 is formed by forming the sacrificial layer 9 including part or all of the metal elements constituting the capacitor insulating film 11 on the side wall portion of the hole 8 occupying the area, the capacitor insulating film 11 is formed. Can be prevented from thermally diffusing into the lower electrode 10, so that composition deviation of the capacitor insulating film 11 made of a ferroelectric or high dielectric can be easily prevented. That is, in the conventional example, when the capacitor insulating film 11 is formed using the MOCVD method or the like, which is formed at a temperature of 300 ° C. or higher, the metal element constituting the capacitor insulating film 11 is thermally diffused to the lower electrode 10. However, according to the first embodiment of the present invention, this problem can be solved. In this way, the capacitive element 13 having excellent characteristics can be realized with a structure that can be easily realized.

(Second Embodiment)
A semiconductor memory device using a capacitive element having a three-dimensional structure according to the second embodiment of the present invention and a manufacturing method thereof will be described below.

  FIG. 4 is a cross-sectional view of a main part showing the structure of a semiconductor memory device using a capacitive element having a three-dimensional structure according to the second embodiment of the present invention. In FIG. 4, the same reference numerals as those shown in FIG.

  The semiconductor memory device using the capacitive element having the three-dimensional structure according to the second embodiment of the present invention shown in FIG. 4 includes the capacitive element having the three-dimensional structure according to the first embodiment of the present invention shown in FIG. Compared with the semiconductor memory device used, the structure of the lower portion of the capacitive element 13 is different and the other portions are the same. Therefore, the following description will focus on the different points.

The structure of the semiconductor memory device according to the present embodiment shown in FIG. 4 is different from the structure of the semiconductor memory device according to the first embodiment shown in FIG. 1 in that the first interlayer insulating film 5 and the plug contact 6 are The electrode 14 is formed on the top. That is, as shown in FIG. 4, the electrode 14 formed of the laminated film of the first barrier layer 15 and the second barrier layer 16 has a region that is equal to or higher than the bottom region of the hole 8, and the upper end of the plug contact 6. And is arranged so as to be in contact with the lower electrode 10. Here, the first barrier layer 15 is a barrier layer against oxygen that constitutes the upper layer of the electrode 14, and is made of a single layer film or a laminated film made of a material selected from IrO ₂ , Ir, RuO ₂ , or Ru. The second barrier layer 16 is a barrier layer against oxygen or hydrogen constituting the lower layer of the electrode 14 and is made of TiAlN, TaAlN, TiSiN, or TaSiN. Further, the electrode 14 only needs to have a structure including at least a laminated film including the first barrier layer 15 and the second barrier layer 16. The thickness of the first barrier layer 15 is 10 nm or more and 100 nm or less, and the thickness of the second barrier layer 16 is 10 nm or more and 100 nm or less.

  Note that the semiconductor memory device manufacturing method according to the present embodiment may include a step of forming the electrode 14 in addition to the semiconductor device manufacturing method according to the first embodiment described above. Specifically, after the step shown in FIG. 2A used in the first embodiment and before the step shown in FIG. 2B, that is, in FIG. After forming the plug contact 6 shown, the electrode 14 composed of the second barrier layer 16 and the first barrier layer 15 is formed so as to cover the upper end of the plug contact 6. Thereafter, after the second interlayer insulating film 7 is formed on the first interlayer insulating film 5 and the electrode 14, a hole 8 exposing the upper surface of the electrode 14 is opened in the second interlayer insulating film 7. The subsequent steps are the same as those described with reference to FIGS. 2C, 3A, and 3B.

  As described above, according to the semiconductor memory device using the capacitive element having a three-dimensional structure and the manufacturing method thereof according to the second embodiment of the present invention, the electrode 14 is provided, and thus the first embodiment has been described. It is possible to prevent the surface of the plug contact 6 from being oxidized during high-temperature oxygen annealing required for crystallization of the capacitive insulating film 11 and to enhance the barrier performance against hydrogen diffusion from below the capacitive element 13. For this reason, characteristic deterioration of the capacitive element 13 can be prevented.

(Third embodiment)
A semiconductor memory device using a capacitive element having a three-dimensional structure according to the third embodiment of the present invention will be described below.

  FIG. 5 is a fragmentary cross-sectional view showing the structure of a semiconductor memory device using a capacitive element having a three-dimensional structure according to the third embodiment of the present invention. In FIG. 5, the same reference numerals as those used in FIG. 1 and FIG.

  Also for the semiconductor memory device using the capacitive element having the three-dimensional structure according to the third embodiment of the present invention shown in FIG. 5, the capacitive element having the three-dimensional structure according to the second embodiment of the present invention shown in FIG. The description will focus on the differences from the semiconductor memory device using the.

  In the semiconductor memory device using the capacitive element having a three-dimensional structure according to the third embodiment of the present invention shown in FIG. 5, the sacrificial layer 9 is formed on a part of the bottom in addition to the side wall of the hole 8. In this respect, the semiconductor memory device according to the second embodiment is different. Here, the portion of the sacrificial layer 9 formed at the bottom of the hole 8 is formed in a region other than the bottom region of the hole 8 and a region where potential is supplied to the lower electrode 10 from below. .

  Further, in the semiconductor memory device using the capacitive element having a three-dimensional structure according to the third embodiment of the present invention shown in FIG. 5, the connection having an inclined portion so as to connect the upper surface of the electrode 14 and the lower electrode 10. An electrode 17 is formed, and this is different from the semiconductor memory device according to the second embodiment. Since the connection electrode 17 having the inclined portion is formed, the bottom corner portion of the capacitor insulating film 11 and the bottom corner portion of the upper electrode 12 are inclined. Thus, the capacitive insulating film 11 and the lower electric strength 17 are formed with good step coverage.

  A method for manufacturing a semiconductor memory device using a capacitive element having a three-dimensional structure according to the third embodiment of the present invention will be described below.

  6 (a) and 6 (b) and FIGS. 7 (a) and 7 (b) are main parts showing a method for manufacturing a semiconductor memory device using a capacitive element having a three-dimensional structure according to the third embodiment of the present invention. It is process sectional drawing.

First, as shown in FIG. 6A, after forming a gate 3 in an element formation region partitioned by an element isolation region 2 on the semiconductor substrate 1, using the gate 3 as a mask, a surface layer portion of the semiconductor substrate 1 is formed. The active region 4 is formed. Subsequently, a first interlayer insulating film 5 made of SiO ₂ or SiN is formed on the entire surface of the semiconductor substrate 1 by CVD so as to cover the element isolation region 2, the gate 3 and the active region 4. Subsequently, after opening a contact hole in the first interlayer insulating film 5, a plug contact 6 made of tungsten or low resistance polysilicon doped with n-type impurities is formed in the contact hole. . Furthermore, in the present embodiment, a laminated film of the first barrier layer 15 and the second barrier layer 16 is formed on the first interlayer insulating film 5 and the plug contact 6 so as to cover the upper end of the plug contact 6. An electrode 14 is formed. Here, the electrode 14 has a region equal to or higher than the bottom region of the hole 8 to be described later, and the first barrier layer 15 is a barrier layer against oxygen constituting the upper layer of the electrode 14, and includes IrO ₂ , The second barrier layer 16 is made of a material selected from Ir, RuO ₂ , or Ru, and the second barrier layer 16 is a barrier layer against oxygen or hydrogen constituting the lower layer of the electrode 14, and includes TiAlN, TaAlN , TiSiN or TaSiN. Further, the electrode 14 only needs to have a structure including at least a laminated film including the first barrier layer 15 and the second barrier layer 16. The thickness of the first barrier layer 15 is 10 nm or more and 100 nm or less, and the thickness of the second barrier layer 16 is 10 nm or more and 100 nm or less.

Next, as shown in FIG. 6B, a second interlayer insulating film 7 made of SiO ₂ or SiN is formed on the first interlayer insulating film 5 so as to cover the electrode 14 by the CVD method. After that, a hole 8 exposing the upper surface of the electrode 14 is opened in the second interlayer insulating film 7.

Next, as shown in FIG. 7A, a metal oxide containing Bi constituting a sacrificial layer described later is formed on the bottom and side walls of the hole 8 and the surface of the second interlayer insulating film 7 by MOCVD. Deposit a thin film. Although the MOCVD method is used here, an ALD method or a sputtering method can also be used. Further, a conductive material containing a noble metal such as Pt, Ir, IrO ₂ , Ru, or RuO ₂ or an oxide thereof is deposited by sputtering so as to cover the thin film constituting the sacrificial layer. Subsequently, the sacrificial layer 9 and the lower electrode 10 are formed on the side wall portion and the bottom portion of the hole 8 by etching back the thin film constituting the sacrificial layer and the deposited conductive material. Here, a gas containing chlorine or fluorine is used for etch back. As described above, in this embodiment, the sacrificial layer 9 is disposed not only on the side wall of the hole 8 but also on a part of the bottom, and the portion formed on the bottom of the hole 8 in the sacrificial layer 9 is the hole. 8 is a bottom region and is formed in a region other than a region where a potential is supplied to the lower electrode 10 from below. Furthermore, in this embodiment, when the upper surface of the electrode 14 is exposed by the etch back, a part of the material constituting the electrode 14 is etched, and the material constituting the etched electrode 14 becomes the sacrificial layer 9 and the lower electrode. 10 is attached to the etching end face located at the bottom of the hole 8 to form a connection electrode 17 having an inclined portion. Thereby, the lower electrode 10 and the electrode 14 can be electrically connected. The connection electrode 17 is formed in this way by taking advantage of the feature that etching of the electrode 14 is physical sputter etching because the noble metal material constituting the electrode 14 is poor in chemical reactivity. Yes. Note that in this etch back, an inert gas such as argon is used in addition to a gas containing chlorine or fluorine.

Next, as shown in FIG. 7B, the surface of the second interlayer insulating film 7, the surface of the sacrificial layer 9, the surface of the lower electrode 10, the surface of the connection electrode 17, and the holes in the electrode 14 are formed by MOCVD. A capacitor insulating film 11 made of SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (0 ≦ x ≦ 1) is formed so as to cover the portion exposed at the bottom of 8. As a film forming method, an ALD method or a sputtering method can be used instead of the MOCVD method. Even when the capacitive insulating film 11 is formed using any of these methods, the film forming temperature is about 300 ° C. or higher. Here, in the conventional example, at this film formation temperature, the metal element constituting the capacitive insulating film 11, Bi in the case of the present embodiment, is thermally diffused to the lower electrode 10, whereby the capacitive insulating film 11. There was a possibility of causing a composition shift, that is, a decrease in Bi composition. However, in this embodiment, the sacrificial layer 9 containing Bi is formed not only on the side wall portion of the hole 8 but also on a part of the bottom portion. Bi constituting the sacrificial layer 9 is more thermally diffused to the lower electrode 10, and the Bi concentration inside the lower electrode 10 becomes higher. For this reason, the amount of Bi thermally diffused from the capacitive insulating film 11 to the lower electrode 10 is further reduced. Therefore, the composition shift of the capacitor insulating film 11 can be further prevented. In addition, before the capacitor insulating film 11 is formed, heat treatment is performed in a range of 300 ° C. or more and 800 ° C. or less, so that the metal element constituting the sacrifice layer 9 is transferred from the sacrifice layer 9 to the lower electrode 10 in advance. Thermal diffusion is also possible. In this embodiment, heat treatment using the RTA method is performed at 650 ° C. for 1 minute in an oxygen atmosphere. Thereby, the effect of preventing the composition deviation of the capacitor insulating film 11 can be further enhanced. Subsequently, the upper electrode 12 made of a conductive material containing a noble metal such as Pt, Ir, IrO ₂ , Ru, or RuO ₂ or an oxide thereof is formed on the surface of the capacitive insulating film 11 by sputtering. Since the connection electrode 17 having the inclined portion is disposed, the bottom corner portion of the capacitor insulating film 11 and the bottom corner portion of the upper electrode 12 are inclined. Further, since the connection electrode 17 has the inclined portion, the capacitor insulating film 11 and the upper electrode 12 can be formed with good step coverage. Subsequently, for the purpose of crystallizing the capacitor insulating film 11, a heat treatment is performed using an RTA method in an oxygen atmosphere at a temperature of 650 ° C. or higher and 800 ° C. or lower for about 1 minute. Through the above steps, the capacitive element 13 having a three-dimensional structure is completed.

  As described above, according to the semiconductor memory device including the capacitive element having the concave three-dimensional structure and the manufacturing method thereof according to the third embodiment of the present invention, in addition to the effects of the second embodiment described above, the sacrifice is performed. Since the layer 9 is formed not only on the side wall portion of the hole 8 but also on a part of the bottom portion, the suppression of the compositional deviation of the capacitive insulating film 11 can be further strengthened. For this reason, the capacitive element 13 with more excellent characteristics can be realized. Furthermore, a structure capable of further strengthening the suppression of the composition deviation of the capacitor insulating film 11 can be realized by an easy method. In addition, the capacitive insulating film 11 and the upper electrode 12 having excellent step coverage can be realized.

  In the first to third embodiments described above, the semiconductor memory device having a capacitor element having a concave three-dimensional structure has been described as an example. However, the present invention is not limited to this configuration. The present invention can be similarly realized even in the case of a semiconductor memory device having a three-dimensional capacitive element formed in a stepped portion such as a mold.

  The present invention relates to a capacitive element having a three-dimensional structure using a capacitive insulating film made of a ferroelectric material or a high dielectric material, and a method for manufacturing the same, particularly when the capacitive insulating film is formed at 300 ° C. or higher such as MOCVD. It is useful to apply the present invention.

It is principal part sectional drawing which shows the structure of the capacitive element which concerns on the 1st Embodiment of this invention. (A)-(c) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 1st Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 1st Embodiment of this invention. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on the 2nd Embodiment of this invention. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on the 3rd Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 3rd Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the manufacturing method of the capacitive element which concerns on the 3rd Embodiment of this invention. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on a 1st prior art example. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on a 2nd prior art example.

Explanation of symbols

1 semiconductor substrate 2 element isolation region 3 gate 4 active region 5 first interlayer insulating film 6 plug contact 7 second interlayer insulating film 8 hole 9 sacrificial layer 10 lower electrode 11 capacitive insulating film made of ferroelectric or high dielectric 12 Upper electrode 13 Capacitor element 14 Electrode 15 First barrier layer 16 for oxygen Second barrier layer 17 for oxygen or hydrogen Connection electrode

Claims (21)

A capacitive element in which a lower electrode, a capacitive insulating film, and an upper electrode are formed in this order so as to extend along at least the side wall and the bottom of a hole formed in the first interlayer insulating film,
A sacrificial layer containing at least one element of metal elements constituting the capacitive insulating film between a portion of the lower electrode formed on the side wall of the hole and the first interlayer insulating film A capacitor element is formed. The capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3, (Bi x La 1-x) 4 Ti 3 O 12, and (Ba _x sr _1-x) TiO ₃ (provided that the capacitor element according to claim 1, characterized in that consists of one kind of material selected from the group consisting of 0 ≦ x ≦ 1).   The sacrificial layer includes any one kind of metal selected from the group consisting of Bi, Pb, Ta, Nb, Zr, Ti, La, Ti, Sr, and Ba, or a plurality of kinds of metals. The capacitive element according to claim 1.   The capacitive element according to claim 3, wherein the sacrificial layer is made of a metal oxide.   The capacitive element according to claim 1, wherein the sacrificial layer is an insulator.   6. The capacitor element according to claim 3, wherein a thickness of the sacrificial layer is 1 nm or more and 50 nm or less.   The sacrificial layer is further formed in a region below a portion of the lower electrode that is present at the bottom of the hole, excluding a region where a potential is supplied to the lower electrode from below. The capacitive element according to claim 1.   2. An electrode including a conductive barrier layer having a barrier property against oxygen or hydrogen is formed so as to be in contact with a lower portion of a portion existing at the bottom of the hole in the lower electrode. The capacitive element of any one of -7.   A portion of the lower electrode existing at the bottom of the hole is a surface layer portion of the semiconductor substrate through a plug formed in a second interlayer insulating film between the semiconductor substrate and the first interlayer insulating film. 9. The capacitor according to claim 1, wherein the capacitor is electrically connected to a source or a drain of a transistor formed on the substrate. Forming a first interlayer insulating film on the substrate;
Forming a hole in the first interlayer insulating film;
Forming a sacrificial layer on the side wall of the hole;
Forming a lower electrode on the bottom of the hole and the side surface of the sacrificial layer;
Forming a capacitive insulating film made of a ferroelectric or a high dielectric so as to cover the surface of the lower electrode;
Forming an upper electrode so as to cover the surface of the capacitive insulating film,
The method of manufacturing a capacitor element, wherein the sacrificial layer includes at least one element of metal elements constituting the capacitor insulating film. The step of forming the capacitive insulating film is performed using SrBi ₂ (Ta _x Nb _1-x ) ₂ O using metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or sputtering. _{9, Pb (Zr x Ti 1} -x) O 3, (Bi x La 1-x) 4 Ti 3 O 12, and _{(Ba x Sr 1-x)} TiO 3 ( here, x of definitive to above, 0 ≦ x The method of manufacturing a capacitive element according to claim 10, further comprising: forming the capacitive insulating film made of any one kind of material selected from the group consisting of: Method.   The method for manufacturing a capacitive element according to claim 11, wherein the step of forming the capacitive insulating film is performed under a condition that a temperature during film formation is 300 ° C. or higher. The step of forming the sacrificial layer includes
Depositing a sacrificial layer forming thin film on the first interlayer insulating film including the side wall and bottom of the hole;
The method for manufacturing a capacitor element according to claim 10, further comprising: forming the sacrificial layer by etching back the thin film for forming the sacrificial layer.   14. The step of depositing the sacrificial layer forming thin film is performed using a metal organic chemical vapor deposition method (MOCVD method), an atomic layer deposition method (ALD method), or a sputtering method. The manufacturing method of the capacitive element as described in 2.   The sacrificial layer includes any one kind of metal selected from the group consisting of Bi, Pb, Ta, Nb, Zr, Ti, La, Ti, Sr, and Ba, or a plurality of kinds of metals. The capacitive element according to claim 10.   The method of manufacturing a capacitor element according to claim 15, wherein the sacrificial layer is made of a metal oxide.   The method of manufacturing a capacitive element according to claim 10, wherein the sacrificial layer is an insulator.   After the step of forming the lower electrode and before the step of forming the capacitive insulating film, the sacrifice is performed by performing a heat treatment in a temperature range of 300 ° C. or higher and 800 ° C. or lower. The method for manufacturing a capacitive element according to claim 10, further comprising a step of diffusing the metal element constituting the layer into the lower electrode. Before the step of forming the first interlayer insulating film, further comprising the step of forming an electrode including a conductive barrier layer having a barrier property against oxygen or hydrogen on the substrate;
The step of forming the first interlayer insulating film is a step of forming the first interlayer insulating film on the substrate so as to cover the electrode including the conductive barrier layer,
The step of forming the hole is a step of forming the hole in the first interlayer insulating film so as to expose an upper surface of the electrode including the conductive barrier layer.
The step of forming the lower electrode is a step of forming the lower electrode on the bottom of the hole and the side surface of the sacrificial layer so as to be in contact with the upper portion of the electrode including the conductive barrier layer. The method for manufacturing a capacitive element according to claim 10. Forming an electrode on the substrate;
Forming a first interlayer insulating film on the substrate so as to cover the electrodes;
Forming a hole in the first interlayer insulating film so that an upper surface of the electrode is exposed;
Depositing a thin film for forming a sacrificial layer on the first interlayer insulating film including the bottom and side walls of the hole;
Forming a conductive film on the sacrificial layer forming thin film;
Etching back the conductive film and the thin film for forming the sacrificial layer forms a sacrificial layer and a lower electrode on the side wall of the hole and a part of the bottom of the hole in the same process, and Sputter etching is performed on the upper surface of the electrode including the conductive barrier layer exposed during etch back, so that the metal constituting the electrode including the conductive barrier layer is formed at the bottom of the hole in the sacrificial layer. Forming a connection electrode attached to the etched end face and connecting the lower electrode and the electrode including the conductive barrier layer;
The electrode including the conductive barrier layer is made of a ferroelectric material or a high dielectric material so as to cover at least the portion exposed at the bottom of the hole, the surface of the connection electrode, and the surface of the lower electrode. Forming a capacitive insulating film;
Including at least a step of forming an upper electrode so as to cover the surface of the capacitive insulating film;
The method of manufacturing a capacitor element, wherein the sacrificial layer includes at least one element of metal elements constituting the capacitor insulating film. 21. The method of manufacturing a capacitor element according to claim 20, wherein the electrode includes a conductive barrier layer having a barrier property against oxygen or hydrogen.

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