JP2006203028A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a low continuity resistance and a high-voltage withstanding property. <P>SOLUTION: In the semiconductor device 1, main grooves 19 having wide widths which are formed in a processing layer 13 are surrounded by a plurality of annular auxiliary grooves 20 having narrower widths than the main grooves 19. In the inside of each main groove 19, semiconductor crystals are grown to fill it with the crystals to an incomplete extent while the inside of each auxiliary groove 20 is filled with the crystals completely. Each voltage withstanding region 23 is formed in each auxiliary groove 20, and each conductive region 22 is formed in each main groove 19. Then, after forming each gate insulating film 21 on the surface of each conductive region 22, each gate electrode 14 is disposed in the region surrounded by each gate insulating film 21, and each inversion layer is formed on the side surface of each gate insulating layer 21 in its depthwise direction to connect each source region 38 and each conductive region 22 by each inversion layer. Since each insulating buried region 10 is positioned on each bottom surface of each gate electrode 14, the semiconductor device 1 has a high-voltage withstanding property. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technical field of a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a channel region is formed along a groove side surface and a manufacturing method thereof.

Reference numeral 101 in FIG. 38 denotes a conventional MOS transistor.
In this MOS transistor 101, an n-type common layer 112 is formed by epitaxial growth on an n-type semiconductor single crystal substrate 111, and a plurality of elongated main grooves 119 are formed in parallel in the common layer 112.
Around the region where the main groove 119 is disposed, a plurality of rectangular ring-shaped sub-grooves 120 surrounding the main groove 119 are formed.

The depth of the main groove 119 and the depth of the sub groove 120 are the same. A gate insulating film 125 is formed on the bottom and side surfaces of the main groove 119, and a gate electrode 128 is filled in a region surrounded by the gate insulating film 125 inside the main groove 119.
A guard region 117 made of a p-type semiconductor single crystal is filled in the sub-groove 120 by epitaxial growth.

A p-type base region 132 is formed on the inner surface of the common layer 112 between the main grooves 119 by diffusing p-type impurities to a position shallower than the main groove 119.
An n-type source region 137 is formed at a position in contact with the gate insulating film 125 on the side of the main groove 119 on the inner surface of the base region 132.

  Since the depth of the main groove 119 is deeper than the depth of the base region 132, the gate insulating film 125 on the lower side surface of each main groove 119 contacts the source region 137, the base region 132, and the common layer 112 in this order from the top. is doing.

  The base region 132 is formed between adjacent main grooves 119, and a p-type ohmic region 145 is formed at a position between the adjacent source region 137 and the source region 137 on the inner surface thereof. .

  A source electrode wiring 150 is formed on the surface of the source region 137 and the ohmic region 145. An interlayer insulating film 147 is formed on the gate electrode 128, and the source electrode wiring 150 and the gate electrode 128 are insulated from each other by the interlayer insulating film 147.

  A drain electrode 114 is formed on the surface of the semiconductor single crystal substrate 111. The source electrode wiring 150 is grounded, and a positive voltage is applied to the drain electrode 114 to form a pn junction between the base region 132 and the common layer 112. When reverse bias is applied and a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 128 in that state, the portion of the base region 132 in contact with the gate insulating film 125 is inverted, and an n-type inversion layer is formed. The source region 137 and the common layer 112 are connected by the inversion layer, and current flows (conduction state).

When the voltage of the gate electrode 128 is switched to the ground potential from that state, the inversion layer disappears and no current flows (blocking state).
In the cutoff state, a large reverse bias is applied to the pn junction between the base region 132 and the common layer 112, and when the depletion layer spreading from the pn junction reaches the guard region 117, the guard region 117 further increases the outer peripheral direction. The breakdown voltage is increased as compared with the case where the guard region 117 is not provided.
JP 2004-064051 A JP 2001-135818 A

  In the semiconductor device 101, the common layer 112 has a high resistance in order to increase the breakdown voltage, and thus the conduction resistance is high. If an n-type high concentration layer is formed in the common layer 112 in order to reduce the conduction resistance, there is a problem that the number of processes increases.

In order to solve the above problems, the present invention provides a first conductivity type common layer, a second conductivity type processing layer disposed on the common layer, and a bottom surface formed on the processing layer. An elongated main groove that reaches the center of the main groove, and is located in the lower portion of the side surface of the main groove, the bottom surface portion is in contact with the common layer, and the center in the width direction along the longitudinal direction of the main groove A first-conductivity-type conductive region having a recess at a position; and a first-conductivity-type source region located in an upper portion of a side surface of the main groove and the main groove. A base region of a second conductivity type that is located at an intermediate position between the conductive region and the source region on the side surface of the main groove and separates the source region and the conductive region, and is disposed on the bottom surface of the recess Located on the insulating buried region of the recess, at least the insulating buried region A gate insulating film that is disposed on a side surface of the portion and is in contact with the source region, the base region, and the conductive region, and is located on the insulating filling in the recess, the source region, the base region, and the The semiconductor device includes a gate electrode disposed over a conductive region and in contact with the gate insulating film, and a source electrode wiring in contact with the source region.
Further, the present invention is a plurality of sub-grooves formed in the processed layer, narrower than the width of the main groove, spaced apart from each other in a concentric ring shape, surrounding the main groove and having a bottom surface reaching the common layer, A first conductivity type withstand voltage region filled in the sub-groove, and a second conductivity type guard region is formed concentrically between the adjacent withstand voltage regions. .
Further, the present invention is a semiconductor device in which the guard regions located between the sub-grooves are electrically separated from each other.
In the present invention, a plurality of the main grooves are arranged in parallel to each other, and the second conductive material having a higher concentration than the processed layer is formed on the inner surface of the processed layer at a position between the main grooves. A semiconductor device in which an ohmic region of a type is disposed, the source electrode wiring is in contact with the ohmic region, and an ohmic junction is formed.
The present invention is the semiconductor device in which the ohmic region is in contact with the base region.
According to the present invention, a drain layer having the same conductivity type as the common layer is disposed on the surface of the common layer, and a drain electrode that forms an ohmic junction with the drain layer is disposed on the drain layer surface. Device.
Further, the present invention is a semiconductor device in which a collector layer of a second conductivity type is disposed on the surface of the common layer, and a pn junction is formed between the common layer.
According to the present invention, a Schottky electrode film that forms a Schottky junction with the common layer is disposed on a surface of the common layer, and the conductive region and the base region are interposed between the base region and the Schottky electrode film. The Schottky junction is a semiconductor device configured to be forward-biased when a voltage having a polarity that reversely biases is applied.
The present invention also includes a first conductivity type common layer, a second conductivity type processing layer disposed on the common layer, and a plurality of gate electrodes disposed in parallel with each other inside the processing layer, An insulating buried region that is located under the gate electrode and insulates the gate electrode and the common layer; a gate insulating film that is disposed in close contact with at least a side surface of the gate electrode; and the processing layer A source region of a first conductivity type that is located on the inner surface of the gate insulating film and is in close contact with a surface opposite to the one surface of the gate insulating film, and an inner surface of the processed layer, surrounding the source region, A base region of a second conductivity type that is in close contact with the gate insulating film under the bottom surface of the source region, and that is in close contact with the gate insulating film under the bottom surface of the base region, with an upper portion in contact with the base region, and a lower portion with the base region. In contact with the common layer, said common layer The conductive region of the first conductivity type having a lower resistance and the region where the gate electrode is disposed are formed in the processed layer and surrounded by a plurality of ring-shaped subgrooves whose bottom surface reaches the common layer, Each sub-groove includes a first conductivity type withstand voltage region having a bottom surface connected to the common layer, and the processed layer between the withstand voltage regions has a bottom surface in contact with the common layer and separated from each other. A semiconductor device made into a region
Further, the present invention is a semiconductor device in which an equipotential ring region of a first conductivity type having a concentration higher than the surface concentration of the withstand voltage region is formed on the surface of at least one withstand voltage region of the withstand voltage region.
The present invention is the semiconductor device in which the equipotential ring region is formed in the breakdown voltage region located on the outermost periphery.
The present invention also provides an elongated main groove in which the processed layer is partially etched from the surface of the second conductive type processed layer disposed on the first conductive type common layer, and the common layer is exposed on the bottom surface. And forming a semiconductor filling made of a semiconductor single crystal of the first conductivity type in the main groove so as to leave a concave portion in the center in the width direction of the main groove, thereby forming the main groove incompletely. An incomplete filling step of filling and forming a conductive region made of the semiconductor filling in the main groove, and an embedded region for forming an insulating embedded region so that the upper portion of the recess remains on the bottom surface of the recess Forming a gate insulating film on the surface of the conductive region on the insulating buried region; forming a gate electrode in contact with the surface of the gate insulating film; and Second conductivity type on the inner surface of the conductive area A base region forming step of introducing and diffusing impurities to convert a region above the conductive region and in contact with the gate insulating film into a base region of a second conductivity type, and a first conductive on the inner surface of the base region A source region that converts a region that is shallower than the base region and is in contact with the gate insulating film and is separated from the conductive region into a first conductive type source region by introducing and diffusing impurities of a type And a forming step.
In the groove forming step, a plurality of sub-grooves that are narrower than the width of the main groove and have the same depth as the main groove in a ring shape surrounding the main groove are formed together with the main groove. In the incomplete filling step, when filling the main groove with the semiconductor filling, the sub-groove is filled with the semiconductor filling.

One of the semiconductor devices of the present invention includes a source region, a base region in contact with the bottom surface of the source region, and a bottom surface of the base region on the side surface of the gate insulating film disposed in the depth direction of the processed layer. And a conductive region having a bottom surface in contact with the common layer is disposed, and the source region is connected to the common layer by an inversion layer and a conductive region formed in the base region.
When the semiconductor device operates, the pn junction between the processed layer and the common layer is reverse-biased, and the depletion layer expands in the depth direction and the outer peripheral direction.

  An insulating buried region is disposed on the bottom surface of the gate electrode. When a large reverse bias is applied between the gate electrode and the common layer, the electric field between the gate electrode bottom surface and the common layer is insulative. The breakdown voltage and the avalanche breakdown voltage are increased by being relaxed in the buried region.

Further, the main groove is surrounded by a guard region, and the guard region is configured so as to widen the depletion layer in the outer peripheral direction and increase the breakdown voltage.
In another semiconductor device of the present invention, a main groove wider than the sub-groove is formed, and the main groove is surrounded by the ring-shaped sub-groove.

  When the sub-groove is filled with the first conductivity type semiconductor single crystal and the breakdown voltage region is formed, the main groove is incompletely filled with the first conductivity type semiconductor single crystal, and the central portion has a recess. A conductive region is formed.

  The upper portion of the first conductivity type conductive region is replaced with the second conductivity type base region, and the portion of the inner surface of the base region that is in contact with the gate insulating film is replaced with the first conductivity type source region.

  Since the main groove and the sub-groove have bottom surfaces that reach the common layer, the conductive region is connected to the common layer, and the processing layer located between the sub-grooves is separated by the pressure-resistant region and is formed in a ring shape.

  A gate insulating film is formed on the side surface of the recess in the main groove. The gate insulating film is in contact with the source region, the base region, and the conductive region. When an inversion layer is formed in the base region, the source region is connected to the conductive region by the inversion layer.

Since the current flowing in the depth direction passes through the low-resistance conductive region 22, the conduction resistance is small.
The current flowing from the conductive region 22 on the bottom surface of the main groove 19 to the common layer 12 also reduces the conduction resistance.

  Since the formation of the withstand voltage region 23 for forming the guard region 27 and the formation of the conductive region 22 are the same step, there is no need to provide a separate step for forming the conductive region 22.

  Since the insulating filling region 10 is disposed under the bottom surface of the gate electrode 14, the withstand voltage between the gate electrode 14 and the common layer 12 is increased, and avalanche breakdown is less likely to occur. In addition, the fracture resistance is improved.

Since the thick insulative filling region 10 is located between the gate electrode 14 and the common layer 12, the capacitance C _rss between the gate electrode 14 and the drain (common layer 12) is reduced, and the operation speed is increased.

  In the present invention, one of the p-type and the n-type will be described as the first conductivity type, and the other will be described as the second conductivity type. When the first conductivity type is n-type, the second conductivity type is p-type. Conversely, when the first conductivity type is p-type, the second conductivity type is n-type.

<First Example Semiconductor Device>
35 is a transverse cross-sectional view for explaining the diffusion structure of the semiconductor device 1 of the first example of the present invention, and FIG. 27 (a) is a longitudinal sectional view taken along the line VIIIa-VIIIa. FIG. 4B is a longitudinal sectional view taken along line VIIIb-VIIIb.

  The planar shape of the semiconductor device 1 is rectangular or square, and a plurality of elements are formed in one wafer.

  The plan views of FIGS. 28 to 35 are transverse sectional views showing the diffusion structure in a state along the manufacturing process of one semiconductor device, and only the upper half is shown here. The remaining lower half is not shown. The omitted part is symmetrical with the upper half.

  First, referring to FIGS. 27A, 27B, and 35, the semiconductor device 1 has a low-resistance semiconductor single crystal substrate 11 of the first conductivity type. On the semiconductor single crystal substrate 11, a first conductive type high resistance common layer 12 and a second conductive type relatively high resistance processed layer 13 are arranged in this order. A plurality of main grooves 19 and a plurality of sub grooves 20 each having a bottom surface reaching the common layer 12 are formed from the surface.

  The main groove 19 has a rectangular cross-sectional shape, and the shape in the direction along the surface of the semiconductor device 1, that is, the surface shape is elongated. A plurality of main grooves 19 are arranged in parallel at equal intervals. The width of each main groove 19 is the same.

  The cross-sectional shape of the sub-groove 20 is a rectangle that is narrower than the cross-sectional shape of the main groove 19, and the planar shape is a square ring shape. Each sub-groove 20 is disposed concentrically, and each main groove 19 is disposed inside the innermost sub-groove 20. That is, the sub-groove 20 is disposed concentrically surrounding the main groove 19.

The widths of the sub grooves 20 are the same, and the distances between adjacent sides of the sub grooves 20 are equal to each other. Further, the distances between the adjacent main grooves 19 are also equal to each other, and the four sides of the sub-groove 20 are parallel to or perpendicular to the main groove 19.
The inside of the sub-groove 20 is filled with a first conductivity type semiconductor single crystal, and a first conductivity type withstand voltage region 23 is formed by the semiconductor single crystal.

On the other hand, the inside of the main groove 19 is incompletely filled with the first conductivity type semiconductor single crystal, and the first conductivity type conductive region 22 is formed on the bottom surface and the side surface of the main groove 19 due to the incomplete filling. Is formed. Since it is incompletely filled, a recess is formed in the central portion of the conductive region 22 in the width direction.
The common layer 12 is exposed on the bottom surfaces of the main groove 19 and the sub-groove 20, and the conductive region 22 and the withstand voltage region 23 are connected to the common layer 12, respectively.

The processed layer 13 sandwiched between the adjacent pressure-resistant regions 23 is electrically separated from the portion of the processed layer 13 surrounded by the innermost pressure-resistant region 23 by the common layer 12 and the conductive region 22 and also separated from each other. Thus, a guard region 27 of the second conductivity type is configured. The guard region 27 is placed at a floating potential.
The pressure-resistant region 23 reflects the planar shape of the sub-groove 20 and has a square ring shape, and the guard region 27 positioned therebetween also has a square ring shape.

  On the other hand, the conductive region 22 has a U-shaped cross section, and the insulating buried region 10 is disposed on the bottom surface of the recess formed by the conductive region 22.

A gate insulating film 21 is disposed in close contact with the portion above the insulating buried region 10 on the surface of the conductive region 22 exposed inside the recess.
A gate electrode 14 in contact with the gate insulating film 21 is disposed in a region above the insulating buried region 10 in the recess and surrounded by the gate insulating film 21.

The upper portion of the conductive region 22 is replaced with a second conductivity type base region 32, and a first conductivity type source region 38 is formed on the inner surface of the base region 32.
The source region 38 is in contact with the gate insulating film 21, and the base region 32 is in contact with the gate insulating film 21 at a portion below the bottom surface of the source region 38.

A second conductivity type ohmic region 46 is disposed on the inner surface of the processed layer 13 at a position between adjacent main grooves 19.
A source electrode wiring 49 is disposed on the surface of the ohmic region 46 and the surface of the source region 38. The surface concentration of the ohmic region 46 is higher than the surface concentration of the base region 32. The ohmic region 46 is in contact with the base region 32. The source electrode wiring 49 is ohmically connected to the source region 38 and the ohmic region 46, and the base region 32 is connected to the source electrode wiring 49 through the ohmic region 46.

  On the surface of the semiconductor single crystal substrate 11, a back electrode 57a (drain electrode) that is in ohmic contact with the semiconductor single crystal substrate 11 is disposed, and the first conductivity type is n-type and the second conductivity type is p-type. When the source electrode wiring 49 is grounded and a positive voltage higher than the threshold voltage is applied to the gate electrode 14 with a positive voltage applied to the back surface electrode 57a, the polarity of the portion of the base region 32 in contact with the gate insulating film 21 is changed. An n-type inversion layer that is inverted and extends in the depth direction is formed. Source region 38 is connected to conductive region 22 by its inversion layer. Since the conductive region 22 is connected to the semiconductor single crystal substrate 11 by the common layer 12, a current flows between the back electrode 57 a and the source electrode wiring 49.

When the first conductivity type is p type and the second conductivity type is n type, the absolute value of the threshold voltage is applied to the gate electrode 14 with the source electrode wiring 49 grounded and a negative voltage applied to the back electrode 57a. When a negative voltage of the above magnitude is applied, the polarity of the portion of the base region 32 that is in contact with the gate insulating film 21 is inverted, and a p-type inversion layer is formed in the depth direction. A current flows between 49 and the back electrode 57a.
Also in this case, when the gate electrode 14 is connected to the ground potential, the inversion layer disappears and no current flows.

  In any case, the processed layer 13 is connected to the source electrode wiring 49 through the ohmic region 46, and the processed layer 13 and the base region 32 have the same potential as the source electrode wiring 49.

  When the semiconductor device 1 operates as a transistor, the pn junction between the second conductivity type processed layer 13 and the first conductivity type common layer 12 or the conductive region 22 is reverse-biased, and the depletion layer expands.

  Between the gate electrode 14 and the gate electrode 14, a depletion layer extends from the pn junction to both the processed layer 13 and the conductive region 22, and the space between the gate electrodes 14 is filled with the depletion layer, so that the electric field does not increase.

  On the other hand, since there is no pn junction immediately below the gate electrode 14, only the depletion layer extending from the gate electrode 14 is present without being filled with the depletion layer extending from the pn junction. And a voltage applied between the conductive region 22 immediately below the conductive region 22 is large.

  In the present invention, the insulating buried region 10 thicker than the gate insulating film 21 is disposed immediately below the gate electrode 14, and therefore, between the bottom surface of the gate electrode 14 and the conductive region 22 immediately below the gate electrode 14. Even if a large voltage is applied, dielectric breakdown does not occur during that time.

The thickness of the insulating buried region 10, that is, the distance between the bottom surface of the gate electrode 14 and the conductive region 22 located immediately below the gate electrode 14 is 3 × 10 ⁻⁶ m or more and 8 × 10 ⁻⁶ m. While the thickness of the gate insulating film 21 located on the side surface is in the range of 0.01 × 10 ⁻⁶ m to 0.2 × 10 ⁻⁶ m, the thickness is 15 times or more.

  In the present invention, the first conductivity of the portion located between the bottom surface of the base region 32 and the common layer 12 excluding the gate electrode 14 is inside the center in the width direction of the innermost guard region 27. The type impurity amount and the second conductivity type impurity amount are equal.

  Further, in the portion between the adjacent gate electrode 14 and the gate electrode 14 and between the bottom surface of the base region 32 and the common layer 12, the amount of impurities of the first conductivity type contained in the conductive region 22 and the processed layer 13. Is set to be equal to the amount of impurities of the second conductivity type contained in the.

  Further, the amount of the first conductivity type impurity contained in the conductive region 22 and the amount of the second conductivity type impurity contained in the processed layer 13 are determined before the pn junction between the conductive region 22 and the processed layer 13 is avalanche breakdown. The conductive region 22 and the inside of the processed layer 13 are set to values that are filled with the depletion layer.

  In the case of such an impurity amount, in the portion located between the bottom surface of the base region 32 and the common layer 12, when the inside of the processed layer 13 is filled with the depletion layer, the inside of the conductive region 22 located on both sides thereof is also Filled with depletion layer.

When the reverse bias applied to the pn junction is large and the depletion layer spreads further, it spreads in the depth direction and the outer peripheral direction inside the common layer 12.
When the depletion layer spreading toward the outer peripheral direction reaches the innermost guard region 27, the potential of the guard region 27 is stabilized, and the inside of the innermost guard region 27 and the innermost guard region 27 A depletion layer spreads in the pressure | voltage resistant area | region 23 which is contacting the outer periphery.

  Thus, when the reverse bias increases, the depletion layer spreads from the inner side toward the outer peripheral direction, and reaches a plurality of guard regions 27 sequentially. In this case, the depletion layer extends to the outside as compared with the case where there is no guard region 27.

  If the width, concentration, etc. of the guard region 27 and the breakdown voltage region 23 are set so that the avalanche breakdown occurs in the active region inside the innermost breakdown voltage region 23, the avalanche current flowing due to breakdown is Since it flows out to the source electrode wiring 49 through the processed layer 13 and the ohmic region 46, breakdown is less likely to occur than when the breakdown occurs in the outer peripheral region outside the innermost breakdown voltage region 23.

<Manufacturing process>
A manufacturing process of the semiconductor device 1 will be described.

  (A) of FIGS. 1 to 27 is an active region, and (b) of FIG. 27 is a longitudinal sectional view of an outer peripheral region outside thereof.

  Referring to FIGS. 1A and 1B, a first conductive type common layer 12 having a higher resistance than that of the semiconductor single crystal substrate 11 is formed on the first conductive type semiconductor single crystal substrate 11 by an epitaxial growth method. On the common layer 12, a second conductivity type processed layer 13 is formed by an epitaxial growth method.

  As shown in FIGS. 2A and 2B, a field insulating film 15 is formed on the surface of the processed layer 13 by a thermal oxidation method or the like. In this step and each step described later, an oxide film formed on the surface of the semiconductor single crystal substrate 11 by a thermal oxidation method is omitted.

  Next, the field insulating film 15 is patterned by a photolithographic process and an etching process, and as shown in FIGS. 3A and 3B, a plurality of elongated rectangular groove openings 17 and the main groove openings 17 are formed. Are formed in a plurality of rectangular ring-shaped sub-groove openings 18 concentrically surrounding each other.

  The main groove openings 17 have the same width, and the sub groove openings 18 have the same width, but the main groove opening 17 is wider than the sub groove opening 18.

  The planar shape of the main groove opening 17 is rectangular, the long sides are directed in the same direction, and are arranged at equal intervals in parallel to each other. The inner circumferential four sides and the outer circumferential four sides of the sub-groove opening 18 are arranged so as to be parallel or perpendicular to the long side of the main groove opening 17, and the sub-groove openings 18 are also equidistant from each other. Is arranged.

  The processed layer 13 is exposed at the bottom surfaces of the main groove and sub-groove openings 17 and 18, and when the exposed portion of the processed layer 13 is etched in the depth direction using the patterned field insulating film 15 as a mask, FIG. As shown in (a) and (b), a main groove 19 having the same planar shape as the main groove opening 17 is formed below the bottom surface of the main groove opening 17, and a plane is formed below the bottom surface of the sub groove opening 18. A sub-groove 20 having the same shape as the sub-groove opening 18 is formed. The main groove 19 is wider than the sub-groove 20.

  FIG. 28 is a cross-sectional view taken along line AA in FIGS. 4 (a) and 4 (b). 4A and 4B are longitudinal sectional views taken along lines Ia-Ia and Ib-Ib in FIG.

  The bottom surfaces of the main groove 19 and the sub-groove 20 reach the same depth as the surface of the common layer 12 or a position deeper than that. Therefore, the common layer 12 is exposed at the bottom surface of the main groove 19 and the bottom surface of the sub-groove 20. Has been. Since the main groove 19 and the sub groove 20 are formed together, the depth of the main groove 19 and the depth of the sub groove 20 are the same.

  Here, the bottom surfaces of the main groove 19 and the sub-groove 20 are deeper than the depth of the surface of the common layer 12, and are therefore located closer to the common layer 12 than the boundary surface between the common layer 12 and the processed layer 13. Of the side surfaces of the grooves 19 and 20, the common layer 12 is exposed at a portion close to the bottom surface. And the processed layer 13 is exposed to the side surface above it.

  The processed layer 13 and the common layer 12 are semiconductors. Here, it is a silicon single crystal, and therefore, the silicon single crystal is exposed on the side and bottom surfaces of the main groove 19 and the sub-groove 20.

The sub-grooves 20 have a square ring shape, the sub-grooves 20 are separated from each other, and the distances between the sub-grooves 20 are equal to each other. Further, the bottom surface of each sub-groove 20 reaches the common layer 12. Accordingly, the processed layer 13 remaining between the sub-groove 20 and the sub-groove 20 has a rectangular cross section and a square shape in plan view. The processed layers 13 are separated from each other by the sub-groove 20.
The innermost rectangular ring-shaped processed layer 13 is separated from the innermost processed layer 13 by the innermost sub-groove 20.

  Reference numeral 27 in FIG. 4B denotes a guard region, which is composed of a portion of the processing layer 13 located between the sub-grooves 20 and a portion located outside the outermost sub-groove 20.

  After the formation of the main groove 19 and the sub-groove 20, when the source material of the first conductivity type semiconductor is brought into contact with the inner and outer surfaces of the main and sub-grooves 19 and 20 by the CVD method, the raw material introduced into the exposed portions of the semiconductor A gas semiconductor single crystal grows.

  Since the semiconductor single crystals are exposed on the side and bottom surfaces of the main groove 19 and the sub-groove 20, the semiconductor single crystal of the source gas grows on the side and bottom surfaces. It does not grow on the surface of the field insulating film 15.

When the growth of the semiconductor single crystal proceeds and the growth is terminated when the inside of the sub-groove 20 is completely filled with the grown semiconductor single crystal, the same semiconductor is placed inside the main groove 19 wider than the sub-groove 20. Although the single crystal has grown, the filling state is incomplete, and a recess remains in the central portion of the main groove 19 in the width direction. Reference numeral 23 in FIG. A breakdown voltage region made of a semiconductor single crystal that grows and fills the sub-groove 20 is shown.

  Reference numeral 22 in FIG. 5A denotes a conductive region made of a semiconductor single crystal that grows in the main groove 19 and incompletely fills the main groove 19. Reference numeral 24 denotes a center position in the width direction of the conductive region 22. The recessed part formed in is shown.

Since the conductive region 22 and the breakdown voltage region 23 are of the first conductivity type and the guard region 27 is of the second conductivity type, a pn junction is formed between the guard region 27 and the breakdown voltage region 23 and between the guard region 27 and the common layer 12. Is formed. The guard regions 27 are electrically isolated from each other by the breakdown voltage region 23.
The innermost guard region 27 is electrically separated from the inner processing layer 13 by the innermost pressure-resistant region 23.

  FIG. 29 is a cross-sectional view taken along line BB in FIGS. 5 (a) and 5 (b). 5A and 5B are longitudinal sectional views taken along lines IIa-IIa and IIb-IIb in FIG. 29, respectively.

  In this state, the conductive region 22 is exposed on the surface of the recess 24. Next, as shown in FIGS. 6A and 6B, a base insulating film is formed on the surface of the conductive region 22 by a thermal oxidation method or the like. 16 is formed. Here, a base insulating film 16 made of a silicon oxide film is formed.

  The base insulating film 16 is thin, and a space surrounded by the base insulating film 16 remains in the recess 24. At this time, the base insulating film 16 is also formed on the breakdown voltage region 23.

  30 is a cross-sectional view taken along the line CC of FIGS. 6 (a) and 6 (b). FIGS. 6A and 6B are longitudinal sectional views taken along lines IIIa-IIIa and IIIb-IIIb in FIG. 30, respectively.

  Next, as shown in FIGS. 7A and 7B, an insulating material 26 is deposited on the surface where the main groove 19 and the sub-groove 20 are formed by a CVD method or the like. Here, a silicon oxide film is deposited, and the space surrounded by the base insulating film 16 in the main groove 19 is filled with the insulating material 26. In addition to the silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or the like can be used.

  FIG. 31 is a cross-sectional view taken along the line DD in FIGS. 7 (a) and 7 (b). FIGS. 7A and 7B are longitudinal sectional views taken along lines IVa-IVa and IVb-IVb in FIG. 31, respectively.

  Next, as shown in FIG. 8B, patterning was performed on the surface of the insulating material 26 located outside the active region inside by a certain distance from the innermost breakdown voltage region 23 by a photolithography process. In a state where the resist film 41 is disposed and the pressure-resistant region 23 and the guard region 27 are protected, the insulating material 26 between the adjacent recesses 24 and the recesses 24 is exposed, and an etching process is performed on the bottom surface of the recesses 24. The insulating material 26 is removed while leaving a part.

  Reference numeral 10 in FIG. 8A denotes an insulating buried region composed of the remaining portion of the base insulating film 16 and the insulating material 26, and this insulating buried region 10 is located on the bottom surface of the recess 24. The upper end is lower than the upper end of the conductive region 22. It is also possible to form the insulating buried region 10 with the insulating material 26 without providing the base insulating film 16.

  Here, the field insulating film 15 and the base insulating film 16 located under the insulating material 26 outside the recess 24 are also removed together with the insulating material 26, so that the insulating region of the conductive region 22 is insulatively embedded. The surface of the portion above the region 10 (this surface is a part of the side surface of the recess 24) and the surface of the processed layer 13 outside the recess 24 are exposed.

  After stripping the resist film 41 in this state, an insulating gate insulating film 21 is formed at least on the surface of the conductive region 22 exposed at the inner periphery of the recess 24 as shown in FIG. Here, the gate insulating film 21 made of a silicon oxide film is formed by a thermal oxidation method, but other insulating materials such as a silicon nitride film may be formed. The grown gate insulating film 21 is not shown outside the active region (FIG. 9B). Further, although a gate insulating film is also formed at the interface between the base insulating film 16 and the conductive region 22, illustration thereof is omitted. The insulating buried region 10 includes a gate insulating film at the interface between the base insulating film 16 and the conductive region 22.

  When the gate insulating film 21 is grown in the recess 24, a space 28 surrounded by the gate insulating film 21 is formed in the recess 24, and a conductive material 29 is deposited by a CVD method or the like. ), The space 28 in the recess 24 is filled with a conductive material 29. At this time, the conductive material 29 is deposited on the insulating material 26 in the outer peripheral region outside the active region. Here, the conductive material 29 made of polysilicon having conductivity was deposited by the CVD method.

  32 is a cross-sectional view taken along the line EE in FIGS. 10 (a) and 10 (b). 10A and 10B are longitudinal sectional views taken along lines Va-Va and Vb-Vb in FIG. 32, respectively.

  Next, by etching, the inside of the recess 24 is left out of the conductive material 29, and the portion outside the recess 24 and the portion on the insulating material 26 are removed. As shown in FIG. A gate electrode 14 is formed inside 24 in contact with the gate insulating film 21 on the side surface and in contact with the insulating buried region 10 on the bottom surface.

  At this time, a patterned resist film is disposed on the surface of the conductive material 29, and a part of the conductive material 29 located outside the recess 24 and connected to the gate electrode 14 is left, and this portion and a gate described later You may make it connect with electrode wiring.

  In any case, in the state where the gate electrode 14 is formed by etching the conductive material 29, the surface of the gate insulating film 21 is exposed at the upper end portion of the conductive region 22 and the surface of the processed layer 13, and the active region In the outer peripheral region on the outer side, the surface of the insulating material 26 is exposed.

  Next, as shown in FIG. 12B, a patterned resist film is formed on the surface of the insulating material 26 positioned outside the active region by a certain distance from the innermost breakdown voltage region 23 by a photolithography process. 42 is disposed to protect the breakdown voltage region 23 and the guard region 27 located outside the active region, and the conductive region 22 located between the gate electrodes 14 and the gate insulating film 21 on the surface of the processing layer 13 are exposed. In this state, an impurity of the second conductivity type is irradiated from above the gate insulating film 21.

  The impurities pass through the gate insulating film 21, and as shown in FIG. 13A, high-concentration impurities of the second conductivity type are formed on the upper portion of the conductive region 22 immediately below the gate insulating film 21 and on the inner surface of the processed layer 13. Layer 25 is formed. Since the impurities cannot permeate the resist film 42, the high concentration impurity layer 25 is not formed in the outer peripheral region as shown in FIG. 13B and FIG. 14B after the heat treatment described below.

  33 is a cross-sectional view taken along the line F-F in FIGS. 14 (a) and 14 (b). 14A and 14B are vertical sectional views taken along line VIa-VIa and VIb-VIb in FIG.

  Next, after removing the resist layer 42, heat treatment is performed to diffuse the high-concentration impurity layer 25. As shown in FIG. 14 (a), between the portions located on the side surfaces of the recess 24 of the gate insulating film 21. A base region 32 of the second conductivity type is formed. The base region 32 is in contact with the gate insulating film 21.

  Reference numeral 33 in FIG. 14A indicates a thermal oxide film formed on the gate electrode 14 by thermal oxidation.

  The depth of the base region 32 is shallower than the bottom surface of the gate electrode 14, and the upper portion of the first conductive type conductive region 22 is formed in the second conductive type base region 32 by the depth of the base region 32. Has been replaced. The surface concentration of the base region 32 is higher than the concentration of the processed layer 13.

  The depth of the base region 32 is shallower than the depth of the gate electrode 14, and the upper part of the side surface of the gate insulating film 21 is in contact with the base region 32 to the depth of the base region 32, and the lower part is in contact with the conductive region 22.

  Next, the patterned resist film protects the upper portion of the base region 32 and the surfaces of the withstand voltage region 23 and the guard region 27 and exposes the insulating material 26 in a state where a desired position inside the withstand voltage region 23 on the innermost periphery is exposed. The thin film and the field insulating film 15 are etched to partially expose the surface of the processed layer 13. The reference numeral 43 in FIGS. 15A and 15B indicates the resist film, and the reference numeral 34 in FIG. 15B is formed on the thin film of the insulating material 26 and the field insulating film 15, and the processed layer 13 is formed. An exposed window opening is shown.

  Next, after the resist film 43 is peeled off, a thermal oxidation process is performed to form a thin insulating film 36 made of a thermal oxide film on the exposed portion of the processed layer 13 as shown in FIG. As shown in a) and (b), the surface of the gate insulating film 21 above the conductive region 22 and the surface of the insulating material 26 above the breakdown voltage region 23 and the guard region 27 are protected by a patterned resist film 52, When the second conductivity type impurity is irradiated from above, the second conductivity type impurity passes through the gate insulating film 21 and the thin insulating film 36, and the second conductivity type high concentration impurity layer 45 is formed.

  The pattern of the high-concentration impurity layer 45 is the same as the pattern of the gate insulating film 21 and the thin insulating film 36 exposed on the bottom surface of the window opening 44. The concentration of the second conductivity type high concentration impurity layer 45 is higher than the surface concentration of the base region 32.

Next, when the heat treatment is performed after the resist film 52 is peeled off, as shown in FIGS. 19A and 19B, the second conductivity type impurities in the high concentration impurity layer 45 are diffused. Region 46 is formed. The surface concentration of the ohmic region 46 is higher than the surface concentration of the base region 32. Here, the depth of the ohmic region 46 is shallower than the depth of the base region 32.
The ohmic region 46 is located inside the innermost breakdown voltage region 23 and is not in contact with the breakdown voltage region 23.

  FIG. 34 is a lateral cross-sectional view taken along the line GG in FIGS. 19 (a) and 19 (b). 19 (a) and 19 (b) are longitudinal sectional views taken along line VIIa-VIIa and line VIIb-VIIb in FIG.

  Next, as shown in FIGS. 20A and 20B, a patterned resist film 53 is disposed on the surface. This resist film 53 has a ring-shaped window opening 54 that exposes the upper side of the outermost pressure-resistant region 23, and etches the insulating material 26 exposed on the bottom surface of the window opening 54, thereby At least a part of the breakdown voltage region 23 is exposed in a ring shape so as to surround the active region.

  Next, after the resist film 53 is peeled off, a resist film 55 is disposed on the surface as shown in FIGS. The resist film 55 has openings 56a and 56b on at least both longitudinal positions of the gate electrode 14 and on the outermost breakdown voltage region 23, respectively.

  Then, when an impurity of the first conductivity type is irradiated from above the resist film 55, the impurity passes through the gate insulating film 21 at a portion where the gate insulating film 21 is exposed, or is implanted into the silicon single crystal, or The portion where the silicon single crystal is exposed, such as the breakdown voltage region 23, is directly injected into the silicon single crystal, and the inner surface of the base region 32 on the bottom surface of the opening 56a along the longitudinal direction of the gate electrode 14 and the outermost breakdown voltage. A high-concentration impurity layer 37 of the first conductivity type is formed on the inner surface of region 23.

  Next, after removing the resist film 55, heat treatment is performed to diffuse the first conductivity type impurities in the high-concentration impurity layer 37, so that the gate electrode 14 is positioned on both side surfaces along the longitudinal direction of the gate electrode 14. An elongated first conductivity type source region 38 is formed along the outer periphery, and a ring-shaped first conductivity type equipotential ring region 39 surrounding the active region is formed on the inner surface of the outermost breakdown voltage region 23.

  The source region 38 is shallower than the base region 32 and is separated from the conductive region 22 by the base region 32. Further, one side of the side surface along the longitudinal direction of the source region 38 is in contact with the gate insulating film 21 to the depth of the source region 38. Two source regions 38 are formed between the adjacent gate electrodes 14, and an ohmic region 46 is located between the two source regions 38.

The width of the equipotential ring region 39 is about the same as the width of the outermost breakdown voltage region 23 and is in contact with the outermost breakdown voltage region 23, but is not in contact with the breakdown voltage region 23 inside the outermost periphery. ing.
Since the surface concentration of the equipotential ring region 39 is high, no p-type inversion layer is formed on the inner surface of the outermost breakdown voltage region 23 where the equipotential ring region 39 is formed.

  FIG. 35 is a cross-sectional view taken along the line HH in FIGS. 23A and 23B and the line JJ in FIGS. 27A and 27B described later. FIGS. 23 (a), (b) and FIGS. 27 (a), (b) are sectional views taken along lines VIIIa-VIIIa and VIIIb-VIIIb in FIG. 35, respectively.

In the state where the source region 38 is formed, a thin film of the gate insulating film 21 and the insulating material 26 is exposed on the surface of the object to be processed including the processed layer 13 and the gate electrode 14. 24A and 24B, an interlayer insulating film 47 made of an insulating material such as SiO ₂ is formed on the surface of the object to be processed, and then patterned on the interlayer insulating film 47. A resist film is disposed and etched to remove the interlayer insulating film 47 exposed on the bottom of the opening of the resist film and the gate insulating film 21 located therebelow so that at least part of the surface of the ohmic region 46 and the source region 38 is obtained. A plurality of openings that expose the surface are formed.

  In FIGS. 25A and 25B, reference numeral 57 denotes a patterned resist film on the interlayer insulating film 47, and reference numeral 58 denotes an interlayer insulating film 47 formed by the resist film 57, the gate insulating film 21 and the like. The opening is shown. Here, the interlayer insulating film 47 is a PSG film.

  Although not shown in FIGS. 25A and 25B, a part of the surface of all the gate electrodes 14 is exposed or is located outside the recess 24 and is electrically connected to the gate electrode 14. When a part of the surface of the material 29 is exposed and a conductive thin film is formed on the surface of the object to be processed by sputtering, vapor deposition or the like in this state, the conductive thin film is separated from the source region 38, the ohmic region 46, and the like. To touch.

  Reference numeral 48 in FIG. 26 indicates the conductive thin film. Here, although the conductive thin film 48 is an aluminum thin film, a conductive thin film such as a metal thin film that can make ohmic contact with the source region 38 and the ohmic region 46 can be widely used.

  The conductive thin film 48 has a portion in contact with the ohmic region 46 and the source region 38 and a portion in contact with the gate electrode 14. The conductive thin film 48 is patterned to form a source electrode wiring including a portion in contact with the ohmic region 46 and the source region 38 and insulated from the gate electrode 14. The source electrode wiring is indicated by reference numeral 49 in FIGS. 27 (a) and 27 (b). Further, when the source electrode wiring 49 is formed, a gate electrode wiring (not shown) connected to the gate electrode 14 is formed by patterning the conductive thin film 48.

  The gate electrode wiring may be directly connected to the gate electrode 14 or may be left when the conductive material 29 filled in the recess 24 is etched and connected to the conductive material 29 in contact with the gate electrode 14. You can also. In the gate electrode wiring, the ohmic region 46 and the source region 38 are insulated, and the source electrode wiring 49 and the gate electrode wiring are electrically separated.

  Next, a protective film (the protective film is not shown) is formed on the source electrode wiring 49 and the gate electrode wiring, a window opening is formed in the protective film by patterning, and then the surface of the semiconductor single crystal substrate 11 is formed. When the back surface electrode 57a that is in ohmic contact with the semiconductor single crystal substrate 11 is formed, the semiconductor device 1 is obtained. The JJ line horizontal direction sectional view of the semiconductor device 1 is the same as FIG.

  In this semiconductor device 1, after dividing into individual elements by dicing, the back electrode 57a is die-bonded to the lead, and the source electrode wiring 49 exposed on the bottom surface of the window opening portion of the protective film or the gate electrode wiring and the lead are made of metal. After connecting with thin wires, packaging is performed, and unnecessary portions of the leads are cut off and separated individually.

  Next, the relationship between the thickness of the insulating buried region 10 and the withstand voltage and conduction resistance of the semiconductor device 1 of the present invention will be described.

The graph of FIG. 39 is a calculation result of the relationship between the thickness T (horizontal axis) of the insulating buried region 10 and the breakdown voltage B _vdss (vertical axis). Regarding the graphs of FIG. 39 and FIGS. 40 and 41 described later, the calculation conditions are as follows.

Distance between adjacent gate electrodes 14 = 2.5 μm
Distance between the bottom surface of the base region 32 and the common layer 12 = 7.5 μm
Depth of base region 32 = 1.5 μm
Conductive region 22 thickness = 0.6 μm
In addition, the first conductivity type and the second conductivity type impurity amounts included in the region sandwiched between the adjacent gate electrodes 14 and included between the common layer 12 and the base region 32 are equal.

The planar shape of the gate electrode 14 is an elongated rectangle, and the amount of impurities in a region sandwiched between adjacent gate electrodes 14 is 1.13 when the length of the gate electrode 14 is L (cm). × 10 ⁹ × L.

  As can be seen from the graph of FIG. 39, the thickness of the insulating buried region 10 is less than 10 times that of the gate insulating film 21, and the breakdown voltage is low.

FIG. 40 is a graph showing the relationship between the thickness T (horizontal axis) of the insulating buried region 10 and the conduction resistance R _ON (vertical axis). When the thickness T of the insulating buried region 10 increases, the conduction resistance R _{ON is shown.} Has also increased.

Next, FIG. 41 is a graph showing the relationship between the breakdown voltage B _vdss (horizontal axis) and the conduction resistance R _ON (vertical axis).

  The curve of “conventional semiconductor device” in the drawing shows the second conductivity type base region and the first conductivity type source on one main surface of the first conductivity type common layer as shown in FIG. A trench gate structure in which the thickness of the insulating buried region between the bottom surface of the gate electrode and the common layer is the same as the thickness of the gate insulating film, and the bottom of the trench 119 reaches the common layer It is the graph which showed the relationship between the proof pressure of a semiconductor device, and conduction resistance.

The distance between adjacent gate electrodes, the impurity concentration and the depth of the base region and the source region are the same as the calculation conditions of the structure of the present invention. In order to change the horizontal axis (withstand voltage B _vdss ), the impurity concentration and depth of the common layer of the first conductivity type are changed.

_{Increasing the} breakdown voltage B _vdss is _achieved by lowering the impurity concentration of the common layer and increasing the depth.

  On the other hand, in the “semiconductor device of the present invention”, the thickness T of the insulating buried region 10 is changed in order to change the value of the horizontal axis.

As can be seen from the curve of the conventional semiconductor device, in the conventional structure, when the concentration of the common layer 12 is decreased or the depth is increased in order to increase the breakdown voltage, the conduction resistance _RON increases rapidly. in, the case of increasing the breakdown voltage by increasing the thickness T of the insulating buried region 10, the degree of increase in conduction resistance R _oN is small. That is, in the semiconductor device 1 of the present invention, compared to the effect of the pressure increase, increase in the conduction resistance R _ON is negligible.

<Other examples>
Although the semiconductor device 1 of the above embodiment is a MOSFET, the semiconductor device of the present invention is not limited thereto, and includes, for example, a pn junction type IGBT (Insulated gate bipolar transistor) and a Schottky junction type IGBT. .

  Reference numeral 2 in FIGS. 36A and 36B denotes a pn junction type IGBT in the semiconductor device of the present invention.

  Whereas the semiconductor single crystal substrate 11 of the semiconductor device 1 of the first example is of the first conductivity type and used as the drain layer, the semiconductor device 2 is replaced with the semiconductor single crystal substrate 11 of the first conductivity type. The second conductivity type semiconductor single crystal substrate 51 is used as a collector layer. Therefore, a pn junction is formed between the first conductivity type common layer 12 and the second conductivity type semiconductor single crystal substrate 51. Other configurations are the same as those of the semiconductor device 1 of the first example.

  36A and 36B, reference numeral 57b denotes a back electrode (collector electrode) that forms an ohmic junction with the semiconductor single crystal substrate 51.

  The pn junction formed between the second conductivity type semiconductor single crystal substrate 51 and the common layer 12 is forward-biased when the pn junction between the processed layer 13 and the common layer 12 is reverse-biased. When the semiconductor device 2 conducts, minority carriers are injected from the semiconductor single crystal substrate 51 into the common layer 12 so that the conduction resistance of the common layer 12 decreases.

  FIG. 35 is a transverse sectional view of the semiconductor device 2 taken along the line KK. 36 (a) and 36 (b) are longitudinal sectional views taken along lines VIIIa-VIIIa and VIIIb-VIIIb in FIG. 35, respectively.

  Next, reference numeral 3 in FIGS. 37A and 37B shows the semiconductor device of the present invention in the case of a Schottky junction type IGBT.

  In this semiconductor device 3, the semiconductor single crystal substrate 11 of the first embodiment is removed by a polishing process or the like, and the first conductivity type common layer 12 having a lower concentration than the semiconductor single crystal substrate 11 is exposed. A back electrode 57 c (Schottky electrode) is formed on the surface of the common layer 12.

  The material of at least the portion of the back electrode 57c that contacts the common layer 12 is a substance that forms a Schottky junction with the common layer 12, and is, for example, chromium. Other structures are the same as those of the semiconductor device 1 of the first example.

  The polarity of the Schottky junction is a polarity that is forward-biased when the pn junction between the common layer 12 and the processed layer 13 is reverse-biased. Therefore, when the semiconductor device 2 is conductive, the polarity is common to the back electrode 57c. Minority carriers are injected into the layer 12 so that the conduction resistance of the common layer 12 decreases.

  FIG. 35 is a lateral sectional view of the semiconductor device 3 taken along the line LL. FIGS. 37A and 37B are longitudinal sectional views taken along lines VIIIa-VIIIa and VIIIb-VIIIb in FIG. 35, respectively.

  When the semiconductor single crystal substrate 11 has a low concentration and can form a Schottky junction with the back surface electrode 57c, a Schottky electrode film can be formed on the surface of the semiconductor single crystal substrate 11. Also in this case, the semiconductor single crystal substrate 11 can be polished to reduce the thickness in order to reduce the conduction resistance.

  In each of the above embodiments, the four corners of the sub-groove 20 are right angles, and the four sides of each sub-groove 20 intersect at right angles. However, the present invention is not limited thereto, and the four corners of the sub-groove 20 are rounded. Also included. Also included are polygonal shapes in which two or more corners are formed at the four corners.

The conductive region 22 and the breakdown voltage region 23 are epitaxially grown semiconductor single crystals. In particular, a silicon single crystal is used, but a semiconductor single crystal other than silicon may be used.
Furthermore, instead of a single crystal, a polycrystalline semiconductor of the first conductivity type may be grown.

(a), (b): The figure for demonstrating the manufacturing-process figure of the semiconductor device of this invention (1). (a), (b): A diagram (2) for explaining the manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (3) for explaining the manufacturing process diagram of the semiconductor device of the present invention. (a), (b): It is figure (4) for demonstrating the manufacturing process figure of the semiconductor device of this invention, Comprising: (a): The Ia-Ia line longitudinal cross-sectional view of FIG. 28, (b) : Fig. Ib-Ib line longitudinal section view (a), (b): It is figure (5) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): The IIa-IIa line longitudinal cross-sectional view of FIG. 29, (b) : Fig. IIb-IIb longitudinal section view (a), (b): It is figure (6) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): The IIIa-IIIa line longitudinal cross-sectional view of FIG. 30, (b) : Fig. IIIb-IIIb longitudinal section view (a), (b): It is a figure (7) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): IVa-IVa line longitudinal cross-sectional view of FIG. 31, (b) : IVb-IVb line longitudinal section view (a), (b): Drawing (8) for demonstrating the manufacturing-process figure of the semiconductor device of this invention. (a), (b): A diagram (9) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): It is a figure (10) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): Va-Va line longitudinal cross-sectional view of FIG. 32, (b) : Vb-Vb line longitudinal section view (a), (b): A diagram (11) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (12) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (13) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): It is a figure (14) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): VIa-VIa line longitudinal cross-sectional view of FIG. 33, (b) : Vertical sectional view taken along line VIb-VIb in FIG. (a), (b): A diagram (15) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (16) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (17) for explaining the manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (18) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): It is a figure (19) for demonstrating the manufacturing-process figure of the semiconductor device of this invention, Comprising: (a): The VIIa-VIIa line longitudinal cross-sectional view of FIG. 34, (b) : VIIb-VIIb line longitudinal section view (a), (b): A diagram (20) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (21) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (22) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (23) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (24) for explaining a manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (25) for explaining the manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (26) for explaining the manufacturing process diagram of the semiconductor device of the present invention. (a), (b): A diagram (27) for explaining a manufacturing process diagram of the semiconductor device of the present invention. 4A and 4B cut along AA line Sectional view taken along line BB in FIGS. 5 (a) and 5 (b) CC sectional view of FIG. 6 (a), (b) A sectional view taken along line D-D in FIGS. 10A and 10B are cross-sectional views taken along the line EE of FIG. Fig. 14 (a) and Fig. 14 (b) are cross-sectional views taken along line FF. GG sectional view of FIGS. 19 (a) and 19 (b) 23 (a) and 23 (b), the JJ line in FIGS. 27 (a) and 27 (b), the KK line in FIG. 36, and the LL line in the longitudinal direction in FIG. Figure (a), (b): pn junction type IGBT in the semiconductor device of the present invention. (a), (b): Schottky junction type IGBT among the semiconductor devices of the present invention. (a), (b): The figure for demonstrating the semiconductor device which is related technology of this invention The graph which shows the calculation result of the relationship between the thickness (horizontal axis) of insulation embedding area _| region, and pressure _| voltage resistance _Bvdss (vertical axis). Graph showing the relationship between the thickness of the insulating buried region (horizontal axis) and the conduction resistance R _ON (vertical axis) Graph showing the relationship between breakdown voltage B _vdss (horizontal axis) and conduction resistance R _ON (vertical axis)

Explanation of symbols

11. Semiconductor substrate (drain layer)
12 ... Common layer 13 ... Processed layer 14 ... Gate electrode 19 ... Main groove 20 ... Sub-groove 21 ... Gate insulating film 22 ... Conductive region 23 ... Withstand voltage region 27 ... Guard region 32 ... Base Region 38 ... Source region 46 ... Ohmic region 49 ... Source electrode wiring 51 ... Semiconductor substrate (collector layer)
57a: Back electrode (drain electrode)
57b …… Back electrode (collector electrode)
57c …… Back electrode (Schottky electrode)

Claims (13)

A common layer of the first conductivity type;
A second conductivity type processed layer disposed on the common layer;
An elongated main groove formed in the processed layer and having a bottom surface reaching the common layer;
A first conductivity type that is located inside the main groove and below the side surface of the main groove, the bottom surface portion is in contact with the common layer, and has a recess at the center in the width direction along the longitudinal direction of the main groove A conductive region of
A source region of a first conductivity type located inside the main groove and above the side surface of the main groove;
A base region of a second conductivity type, which is located inside the main groove and is located at an intermediate position between the conductive region and the source region on the side surface of the main groove and separates the source region and the conductive region; ,
An insulating buried region disposed on the bottom surface of the recess;
A gate insulating film located on the insulating buried region of the recess, disposed at least on a side surface of the recess, and in contact with the source region, the base region, and the conductive region;
A gate electrode located on the insulating filling in the recess, disposed over the source region, the base region, and the conductive region, and in contact with the gate insulating film;
A semiconductor device having a source electrode wiring in contact with the source region. A plurality of sub-grooves formed in the processed layer, narrower than a width of the main groove, spaced apart from each other in a concentric ring shape, surrounding the main groove and having a bottom surface reaching the common layer;
2. A first conductivity type withstand voltage region filled in the sub-groove, and a second conductivity type guard region is formed concentrically between the adjacent withstand voltage region and the withstand voltage region. The semiconductor device described.   The semiconductor device according to claim 2, wherein the guard regions located between the sub-grooves are electrically separated from each other. A plurality of the main grooves are arranged in parallel to each other;
A second conductivity type ohmic region having a higher concentration than the processed layer is disposed on the inner surface of the processed layer at a position between the main groove and the source electrode wiring is in contact with the ohmic region. The semiconductor device according to any one of claims 1 to 3, wherein an ohmic junction is formed.   The semiconductor device according to claim 1, wherein the ohmic region is in contact with the base region.   6. The drain layer having the same conductivity type as that of the common layer is disposed on the surface of the common layer, and a drain electrode that forms an ohmic junction with the drain layer is disposed on the surface of the drain layer. The semiconductor device according to any one of the above.   6. The semiconductor device according to claim 1, wherein a second conductivity type collector layer is disposed on a surface of the common layer, and a pn junction is formed between the common layer and the common layer. On the surface of the common layer, a Schottky electrode film that forms a Schottky junction with the common layer is disposed,
The Schottky junction is configured to be forward-biased when a voltage having a polarity that reversely biases the conductive region and the base region is applied between the base region and the Schottky electrode film. The semiconductor device according to claim 5. A common layer of the first conductivity type;
A second conductivity type processed layer disposed on the common layer;
A plurality of gate electrodes arranged parallel to each other inside the processed layer;
An insulating buried region located under the gate electrode and insulating the gate electrode and the common layer;
A gate insulating film disposed in close contact with at least a side surface of the gate electrode;
A source region of a first conductivity type located on the inner surface of the processed layer and in close contact with a surface opposite to the one surface of the gate insulating film;
A base region of a second conductivity type that is an inner surface of the processed layer, surrounds the source region, and is in close contact with the gate insulating film under a bottom surface of the source region;
A first conductive type conductive region that is in close contact with the gate insulating film under a bottom surface of the base region, an upper portion is in contact with the base region, a lower portion is in contact with the common layer, and has a lower resistance than the common layer;
The region where the gate electrode is disposed is formed in the processed layer, and the bottom surface is surrounded by a plurality of ring-shaped subgrooves reaching the common layer,
Each sub-groove includes a first conductivity type withstand voltage region having a bottom surface connected to the common layer,
The processed layer between the breakdown voltage regions is a semiconductor device in which a bottom surface is in contact with the common layer and is a guard region separated from each other.   10. The semiconductor device according to claim 9, wherein an equipotential ring region of a first conductivity type having a concentration higher than a surface concentration of the withstand voltage region is formed on a surface of at least one of the withstand voltage regions.   The semiconductor device according to claim 10, wherein the equipotential ring region is formed in the breakdown voltage region located on an outermost periphery. A groove forming step of partially etching the processed layer from the surface of the second conductive type processed layer disposed on the first conductive type common layer to form an elongated main groove exposing the common layer on the bottom surface When,
A semiconductor filling made of a semiconductor single crystal of a first conductivity type is epitaxially grown in the main groove so as to leave a recess in the center in the width direction of the main groove, and the main groove is incompletely filled, An incomplete filling step of forming a conductive region of the semiconductor filling;
An embedded region forming step of forming an insulating embedded region on the bottom surface of the recess so that the upper portion of the recess remains;
Forming a gate insulating film on the surface of the conductive region on the insulating buried region; and
Forming a gate electrode in contact with the gate insulating film surface; and
A base region forming step of introducing an impurity of a second conductivity type into the inner surface of the conductive region and diffusing it to convert a region above the conductive region and in contact with the gate insulating film into a second conductivity type base region When,
A first conductivity type impurity is introduced into the inner surface of the base region, diffused, shallower than the base region, and a region that is in contact with the gate insulating film and is separated from the conductive region. A source region forming step for converting into a conductive type source region;
A method for manufacturing a semiconductor device comprising: In the groove forming step, a plurality of sub grooves which are narrower than the width of the main groove and surround the main groove and have the same depth as the main groove are formed together with the main groove,
13. The method of manufacturing a semiconductor device according to claim 12, wherein in the incomplete filling step, the sub-groove is filled with the semiconductor filling when the main groove is filled with the semiconductor filling.

Images