JP2006202268A - Cpu - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent breakage of a data area caused by a stack area exceeding previously assumed memory area and results in unexpected operation of a program, while restricting increase in a burden of software. <P>SOLUTION: This CPU is provided with a stack pointer register, a stack terminating register setting a terminal address of a first stack area, a second stack area starting register for setting a starting address of the second stack area, and a stack pointer control circuit. The stack pointer control circuit replaces the address of the stack pointer register with the starting address of the second stack area when the address of the stack pointer register reaches the terminal end of the first stack area, and replaces the address of the stack pointer register with the terminal address of the first stack area when the address of the stack pointer register reaches the starting address of the second stack area. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CPU including a stack pointer control circuit and a stack area control method in the CPU. In particular, in a CPU having a stack pointer register, the present invention relates to a technique for preventing a problem that a program or a program operates unexpectedly by destroying data or program code beyond the memory area initially assumed when the program is executed. .

  In response to the input of an external interrupt request signal or the occurrence of an interrupt factor such as an internal exception event, the CPU (Central Processing Unit) interrupts the currently executing process and proceeds to interrupt processing. An interrupt function for returning to the original process again after completion of the interrupt process is provided.

  Generally, an interrupt is an interrupt routine that is a process for realizing the function, and various register values at the time of execution of the original process prior to the interrupt routine process are stored in the stack area (last-in-first-out memory Interrupt input processing that performs processing to save to (area), and interrupt processing that restores the values of various registers saved in the interrupt input processing from the stack area to the original register after the completion of interrupt routine processing and returns to the previous processing. Consists of a process to finish loading. In this way, the values of various registers are saved in the stack area by interrupt input processing, and the values saved in the stack area by the interrupt end processing are restored to the original registers. Even if the value is rewritten, the value of the register is restored to the value of the register before the interrupt when returning to the process before the interrupt. That is, the register value can be kept unchanged before and after the interrupt, and the original process can be continued normally. Here, storing data in the stack area is called a push operation, and taking out data is called a pop operation.

  In general, a CPU is provided with a stack pointer register (hereinafter referred to as a stack pointer) that stores the start address of the current stack area, and a memory address that becomes an initial value in the stack pointer by software after the CPU is started. To use the stack area.

  As an example of the CPU, FIG. 8 shows a register structure of the Z80 CPU that is often used for embedded applications even now (see, for example, Non-Patent Document 1). In Z80CPU, A, A ′ and flag registers F and F ′ used as accumulators, B to L used as general purpose registers, B ′ to L ′ used as auxiliary registers, and dedicated registers are used as a register group. A stack pointer (SP), a program counter (PC), and the like are provided.

  Usually, there is one memory area for realizing the stack area, and it is not physically separated into a plurality. Therefore, as shown in FIG. 9, sometimes the stack area consumes memory beyond the originally assumed memory area due to overlap of interrupts and subroutines during actual program execution. In such a case, data such as program codes and variables that are originally held in a predetermined memory area are rewritten, which may cause a problem that the program operates unexpectedly.

  In order to deal with such problems, for example, Patent Document 1 compares a register that stores the upper limit address of the stack area with an address stored in the register and an address when accessing the storage circuit. A comparator that outputs an interrupt signal to the CPU when the value of the address for accessing the memory circuit is smaller than the value of the register, and allows the program being executed to recognize the abnormal use of the stack by a subroutine executed by the interrupt Thus, a technique is disclosed in which execution of a program is stopped to prevent destruction of the program.

In Patent Document 2, the CPU starts an interrupt process, executes a process for setting a stack pointer value in a general-purpose register, and executes a process for setting an address of an empty area in the main memory as a stack pointer. The technique of doing is disclosed.
“Transistor Technology SPECIAL No.6 Special Feature: All of Z80 Software & Hardware”, CQ Publisher, November 1, 1987 (first edition), p. 18, Fig. 2-1 Japanese Patent Laid-Open No. 7-219913 JP-A-8-77004

  However, the technique described in Patent Document 1 only prevents the program from being destroyed by stopping the execution of the program, and the technical content is that the stack area can be operated normally even if it exceeds the initially assumed area. Absent.

  On the other hand, in the technique described in Patent Document 2, destruction of the process space is prevented, and the system can be continuously executed. However, in order to realize this, software processing by the CPU is necessary, and there is a problem that the processing speed decreases.

  In view of the above circumstances, the present invention continues normal operation without stopping execution of a program even if the stack area may consume the memory area beyond the initially assumed memory area. It is an object of the present invention to provide a CPU capable of performing the above and a stack area control method using the CPU. In particular, it is an object of the present invention to provide a CPU and a stack area control method capable of continuing normal operation while suppressing a reduction in processing speed due to an increase in software load.

  The CPU of the present invention that achieves the above object sets the stack pointer register for storing the start address of the current stack area, the stack end register for setting the end address of the first stack area, and the start address of the second stack area In the next push operation when the address of the second stack area start register and the address of the stack pointer register reach the address set in the stack end register, the address of the stack pointer register is stored in the second stack area start register. In the next pop operation when the stack pointer register address reaches the address set in the second stack area start register, the stack pointer register address is replaced with the stack end register. Characterized in that a stack pointer control circuit to replace has been set to address.

  By providing a stack pointer control circuit, normal operation continues while restraining an increase in software load even if the stack area consumes memory area beyond the originally assumed area and data may be destroyed. can do.

  Here, when the address of the stack pointer register reaches the end address of the first stack area or an address in the first stack area by a predetermined value from the end address, a stack end determination that generates an internal interrupt request signal A second stack area is dynamically allocated in the interrupt routine that is shifted by the internal interrupt request signal, and a start address of the reserved second stack area is assigned to the second stack area start register It is preferable to set to. Since the stack end determination circuit is provided and the second stack area is dynamically secured, the memory area can be effectively used.

  Here, it is preferable that the stack end determination circuit generates different internal interrupt request signals during a push operation and a pop operation.

  The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and refers to the value of the enable flag to determine the internal interrupt request. It is preferable to generate a signal. This makes it possible to perform processing according to whether or not the second stack area is secured.

  Alternatively, it is preferable that the enable flag can be read from an interrupt routine that has been shifted by the internal interrupt request signal. This makes it possible to perform different processing depending on whether or not the second stack area is secured after the transition to the interrupt routine.

  Further, the second stack area start register is writable in the interrupt routine shifted by the internal interrupt signal, and when the interrupt routine dynamically secures the second stack area, The start address of the two stack areas is written, an invalid value is written when the interrupt routine releases the second stack area, and the stack end judgment circuit detects writing to the second stack area. It is preferable to further include an enable flag control circuit for setting the second stack area enable flag. By providing the enable flag control circuit, it is possible to appropriately set the second stack area enable flag value without increasing the software load.

  The stack area control method of the present invention that achieves the above object includes a stack pointer register that stores the start address of the current stack area, a stack end register that sets the end address of the first stack area, and the start of the second stack area When the address of the second stack area start register for setting the address and the address of the stack pointer register reaches the end address of the first stack area or an address in the first stack area by a predetermined value from the end address, an internal allocation is performed. A stack area control method in a CPU having a stack end determination circuit for generating an interrupt request signal, wherein the process proceeds to an interrupt routine in response to the internal interrupt request signal, and the second stack area is activated in the interrupt routine. And reserve the start address of the reserved second stack area. And setting the stack area start register.

  By setting the reserved start address of the second stack area in the second stack area start register, the CPU can use the second stack area while suppressing an increase in software load.

  Here, during the CPU push operation, in the interrupt routine, the second stack area is dynamically secured and the second stack area start address is set in the second stack area start register, and the CPU pops. In operation, the interrupt routine preferably releases the second stack area secured by the push-time interrupt routine. The memory area can be used more effectively by releasing the second stack area in the pop-up interrupt routine.

  The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and reads the value of the enable flag in the interrupt routine. It is preferable to perform different processing depending on the value of the enable flag.

  Further, the stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and detects writing to the second stack area start register. Including an enable flag control circuit for setting the enable flag, and when the second stack area is dynamically secured in the interrupt routine, the start address of the secured second stack area is set to the second stack area. It is preferable to write an invalid value to the second stack area start register when writing to the start register and releasing the second stack area. As a result, the stack end determination circuit can manage the value of the second stack area enable flag while suppressing an increase in software load.

  Since the CPU according to the present invention includes the stack pointer control circuit, even when the stack area consumes the memory area beyond the initially assumed area and the data may be destroyed, the increase in software load is suppressed, Normal operation can be continued.

  Hereinafter, a CPU and a stack area control method using the CPU according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram showing a configuration of a CPU according to an embodiment of the present invention. The CPU 1 shown in FIG. 1 includes an interrupt control unit 10, a control unit 20, an ALU (arithmetic logic unit) 30, a register group 40, and a stack end determination circuit 50. The register group 40 includes a register group 400 representing a plurality of registers not directly related to the present invention, a stack pointer (hereinafter also referred to as SP) 401, a first stack area (hereinafter referred to as an initial stack area as a first stack). A stack end register (hereinafter referred to as SPE1 register) 402 for holding the end address of the second area and a second stack area start register (hereinafter referred to as SPS2 register) for holding the start address of the second stack area. 403.

  The control unit 20 includes a stack pointer control circuit 22 of the present invention. The stack pointer control circuit 22 replaces the stack pointer address with the address set in the SPS2 register when the stack pointer address reaches the address set in the SPE1 register, and sets the stack pointer address in the SPS2 register. The stack pointer is controlled so that the address of the stack pointer is replaced with the address set in the SPE1 register when the address reached is reached.

  Further, the stack end determination circuit 50 includes a second stack area enable flag 52. The second stack area enable flag (hereinafter referred to as SP2ENB flag) stores a value indicating whether or not the second stack area is secured. For example, SP2ENB = H indicates that the second stack area is secured, and SP2ENB = L indicates that the second stack area is not secured (or is released after being secured once).

  In the block diagram shown in FIG. 1, description of circuit blocks not directly related to the present invention is omitted.

Example 1
A first example of the operation of the CPU shown in FIG. 1 will be described.

  After the CPU 1 is activated, the software sets an initial value to be the start address of the first stack area in the stack pointer, and starts using the stack area. As an example, as shown in FIG. 3, the range from address FFFFh (hexadecimal display, the same applies hereinafter) to FF00h is set in the first stack area, the side closer to FFFFh (address value is larger) is set as the start side, Let us consider a case where the side closer to (the address value is smaller) is the end side. Then, FFFEh is set as the initial value of SP 401. As the stack area grows, the value of SP 401 changes in the order of FFFCh, FFFAh,... Under the control of the stack pointer control circuit 22.

  That is, here, it is assumed that the stack area for two addresses is used at a time and the value of SP 401 changes by two. The value closer to the end (smaller value) of the two addresses is set as the SP401 value. For example, when the first two addresses FFFFh and FFFEh in the first stack area are used, the value of SP401 is set to FFFEh.

  The CPU 1 of the present invention includes an SPE1 register 402 for holding the end address of the first stack area. By using this, the stack pointer control circuit 22 knows where the first stack area ends and can appropriately control the use of the stack area.

  The operation mechanism of the stack pointer control circuit 22 will be described with reference to FIG. FIG. 2 is a circuit block diagram of an example of the stack pointer (SP) control circuit 22. The SP control circuit 22 includes a −2 / + 2 adder / subtractor 221, a switch 222, and a comparator 223. In addition, a control signal indicating whether the operation is a push operation or a pop operation is supplied to the comparator 223 by the control unit 20. Here, for example, it is assumed that FF00h is set in the SPE1 register 402 and F0FEh is set in the SPS2 register 403.

  The −2 / + 2 adder / subtractor 221 subtracts 2 from the SP value during the push operation, and adds 2 to the SP value during the pop operation. The comparator 223 selects the switch 222 so that the output of the −2 / + 2 adder 221 is output from the switch 222 when the SP value changes within one stack area.

  The comparator 223 compares the address set in the SPE1 register 402 with the address of the SP 401 during the push operation. When a comparison result is obtained in which the address of SP 401 is equal to the end address set in SPE1 register 402 (ie, FF00h), a selection signal is output so as to output the address set in SPS2 register to switch 222. Is output. That is, in the next push operation that has been used up to the end address of the first stack area by the previous operation, the start address of the second stack area is supplied from the switch 222 to the SP 401 and is taken in synchronization with the clock. As a result, the address of the SP 401 moves to the second stack area, and the second stack area is used.

  On the contrary, in the direction in which the stack is popped, after the value of SP401 becomes F0FEh, the next value becomes FF00h instead of F100h, and the address of SP401 moves to the first stack area. For this purpose, the comparator 223 compares the address set in the SPS2 register 403 with the address of SP401. When the comparison result is the same between the two, a selection signal is output to the switch 222 so as to output the address of the SPE1 register. That is, in the next pop operation used up to the start address of the second stack area by the previous operation, the end address of the first stack area is supplied from the switch 222 to the SP 401 and is taken in synchronization with the clock.

  The stack pointer control circuit 22 shown in FIG. 2 is configured as hardware in the CPU 1. The stack pointer control circuit 22 controls the stack pointer using the SPE1 register 402 and the SPS2 register 403, which are also configured as hardware. Therefore, unlike the case of Patent Document 2, it is possible to perform high-speed processing while realizing the use of the first and second stack areas without requiring processing by software.

  Next, the operation of the stack end determination circuit 50 will be described. When the value of SP 401 reaches the end of the first stack area, the stack end determination circuit generates an internal interrupt signal for securing or releasing the second stack area.

  Most simply, when the value of SP 401 reaches the end address set in the SPE1 register 402, it is determined that the end of the first stack area has been reached. However, in reality, when the address in the first stack area is reached by a predetermined value from the end address, it is determined that the end of the first stack area has been reached, and an internal interrupt for securing the second stack area It is preferable to generate a signal. For example, when SP = FF04h is changed to SP = FF02h, the stack end determination circuit 50 determines that the end of the first stack area has been reached. Then, the stack end determination circuit 50 generates an internal interrupt request signal and outputs it to the interrupt control unit 10. The interrupt control unit 10 outputs an interrupt signal to the control unit 20 in response to the internal interrupt request signal. As a result, the CPU 1 performs an interrupt operation, stores the current value of the program counter (PC) in the addresses FF01h and FF00h of the first stack area, and jumps to a specific address.

  An instruction or function that dynamically allocates a memory area, for example, an instruction conforming to C language malloc () is arranged at the specific address. By executing this instruction, the start address of the second stack area is obtained. This value is set in the SPS2 register 403.

  As an example, as shown in FIG. 3, it is assumed that the range of memory addresses F0FFh to F000h can be secured as the second stack area. As described above, assuming that the address closer to the end of the two addresses used at a time (smaller value) is set to the value of SP401, the end address set in SPS2 is set to F0FEh.

  Thereafter, the PC value stored in the addresses FF01h and FF00h is taken out, and the original program being executed is returned to. After the return, the stack grows further from F002h, and in the push operation after becoming FF00h, the value of SP401 is not FEFEh but F0FEh stored in the SPS2 register is loaded by the control of the stack pointer control circuit 22 Is done. Thereafter, the second stack area of memory addresses F0FFh to F000h is used.

  Further, when the pop operation returns from the second stack area to the first stack area and SP = FF02h changes to SP = FF04h, the stack end determination circuit 50 determines that the end of the first stack area has been reached. At this time, the stack end determination circuit 50 generates an internal interrupt request signal different from that at the time of push and transmits it to the interrupt control unit 10.

  Since this time is the case of a pop operation in which the memory address is FF02h → FF04h, a jump is made to a specific address different from the previous specific address. In the interrupt routine starting from the specific address, an instruction for releasing the memory area dynamically allocated first is arranged. As a result, the memory area reserved as the second stack area can be used again by the user for purposes other than the stack area. Thereafter, the stack transfers data again in the first stack area.

  As described above, the memory area can be effectively used by securing the second stack area dynamically when it becomes necessary and releasing it when it becomes unnecessary. In this embodiment, software processing (internal interrupt routine) is used for securing and releasing the second stack area. However, the secured start address of the second stack area is written into the SPS2 register 403 configured as hardware. Therefore, when the stack pointer control circuit 22 uses the reserved second stack area, no software processing is required.

  In this embodiment, the stack end determination circuit 50 generates different internal interrupt request signals for the push operation and the pop operation. Specifically, a request signal that requests an interrupt routine that secures the second stack area is generated during a push operation, and a request signal that requests an interrupt routine that releases the reserved second stack area is generated during a pop operation. To do.

  That is, in this embodiment, the second stack area is always secured when the end of the first stack area is detected in the push operation, and the end of the first stack area is detected during the pop operation. If this happens, the second stack area is always released. In this case, the second stack area enable (SP2ENB) flag 52 shown in FIG. 1 can be omitted.

(Example 2)
A second example of the operation of the CPU shown in FIG. 1 will be described. In this embodiment, the stack end determination circuit 50 generates different internal interrupt request signals depending on whether or not the second stack area is secured, and is different between the push operation and the pop operation. Other operations, for example, the operation of the stack pointer control circuit 22 are the same as those in the first embodiment.

  FIG. 4 is a flowchart showing an example of the operation of the stack end determination circuit 50 in this embodiment, which is performed using the second stack area enable (SP2ENB) flag 52.

  In the flowchart of FIG. 4, the stack end determination circuit 50 monitors the change of the SP 401 (ST11). When the change from FF04h to FF02h, that is, the arrival of the end of the first stack area in the push operation is detected (ST12), the value of the SP2ENB flag 52 is further referenced (ST13). If the value SP2ENB = L indicating that the second stack area is not secured is obtained, the stack end determination circuit 50 generates the first internal interrupt request signal INT1 (ST14). In response to the first internal interrupt request signal INT1, the interrupt control unit 10 outputs a signal for shifting to the first internal interrupt routine to the control unit 20. As a result, the first internal interrupt routine for securing the second stack area is started in the CPU 1 (ST15). Thereafter, the stack end determination circuit 50 continues to monitor SP401. On the other hand, when the value of SP2ENB = H indicating that the second stack area is secured is obtained, the stack end determination circuit 50 does not generate an internal interrupt request signal.

  On the other hand, when the stack end determination circuit 50 detects a change from FF02h to FF04h, that is, arrival at the end of the first stack area in the pop operation (ST16), the value of the SP2ENB flag 52 is referred to ( ST17). If SP2ENB = H, the stack end determination circuit 50 generates the second internal interrupt request signal INT2 (ST18). In response to the second internal interrupt request signal INT2, the interrupt control unit 10 outputs a signal for shifting to the second internal interrupt routine to the control unit 20. As a result, the second internal interrupt routine for releasing the second stack area secured by the previous operation is started in the CPU 1 (ST19). Thereafter, the stack end determination circuit 50 continues to monitor SP401. On the other hand, if SP2ENB = L, the stack end determination circuit 50 does not generate an internal interrupt request signal.

  Here, in the processing shown in FIG. 4, the first internal interrupt routine ST15 and the second internal interrupt routine ST19 are implemented by software. However, all other processing up to the generation of the first internal interrupt request signal INT1 or the generation of the second internal interrupt request signal INT2 is executed by the hardware in the stack end determination circuit 50. Therefore, in this embodiment, the second stack area can be secured and released at a high speed while suppressing an increase in software load.

  For example, even if the arrival of the end of the first stack area in the pop operation is detected and the process proceeds to the second internal interrupt routine, the second stack area is released according to the determination in the second internal interrupt routine. It is also possible not to perform. Specifically, it determines the degree of memory resource pressure by the second stack area, whether or not it is after completion of a specific process that requires a high processing speed, and depending on the determination result, It is possible not to release.

  As described above, when the second stack area is not released, when it is detected that the SP 401 has reached the end of the first stack area in the push operation, the second stack area is secured again. There is no need. As described above, when it is detected that the end of the first stack area is reached in the push operation or the pop operation, it is not always necessary to secure or release the second stack area. With such a flow, it is necessary to generate different internal interrupt request signals depending on whether or not the second stack area is secured. Here, in order to implement the flow of FIG. 4, the stack end determination circuit 50 preferably includes an SP2ENB flag control circuit 54 (see FIG. 6) for controlling the value of the SP2ENB flag 52.

  FIG. 5 shows an example of a flow for the enable flag control circuit to control the value of the SP2ENB flag 52. Here, when the second stack area is secured by the first internal interrupt routine, the second stack area is secured by executing an instruction according to malloc (), for example, It is assumed that the start address of the 2-stack area is written to the SPS2 register 403. Furthermore, when the second stack area is released by the second internal interrupt routine, for example, the second stack area is released by executing an instruction according to free (), and the SPS2 register 403 is set. It is assumed that dummy data is written which is meaningless in itself.

  In the flow shown in FIG. 5, the stack termination determination circuit 50 monitors writing to the SPS2 register 403 (ST21). When writing to the SPS2 is detected (ST22), the value of the SP2ENB flag 52 is referred to (ST23). If the value of the SP2ENB flag 52 is H, L is written (ST24), and if L H is written (ST25).

  FIG. 6 shows an example of the SP2ENB flag control circuit 54 for performing control according to the flow of FIG. In the SP2ENB flag control circuit 54 of FIG. 6, the SP2ENB flag 52 is realized by a flip-flop. The output of the XOR gate 56 is connected to the D input terminal of the SP2ENB flag 52, the input signal IN is connected to one input terminal of the XOR gate 56, and the Q output terminal of the SP2ENB flag 52 is connected to the other input terminal. ing. A write signal of the SPS2 register 403 is supplied as the input signal IN. On the other hand, the output signal OUT is supplied from the Q output terminal of the SP2ENB flag 52 to the control unit 20 and an internal interrupt signal generation circuit (not shown) in the stack termination determination circuit 50.

  In the SP2ENB flag control circuit 54 shown in FIG. 6, the write to the SPS2 register 403 is monitored by supplying the SPS2 register 403 write signal (one clock width) to one input terminal of the XOR gate 56. That is, when an H level signal is supplied to one input terminal of the XOR gate, writing to the SPS2 register 403 is detected. Then, when the Q output of the SP2END flag 52 is supplied to the other input terminal of the XOR gate 56, a signal obtained by inverting the value of the current SP2END flag 52 is output from the output terminal of the XOR gate 56 to the D of the SP2ENB flag 52. Supplied to the input terminal. This signal is written to the SP2ENB flag 52 in synchronization with the clock signal CK.

  In this embodiment, the stack end determination circuit 50 generates an internal interrupt request signal that varies depending on whether or not the second stack area is secured. Therefore, the second stack area can be secured and released more flexibly. Further, in the present embodiment, the control of the SP2ENB flag 52 according to the flow of FIG. 5 is performed by hardware in the stack end determination circuit 50, like the control circuit 54 illustrated in FIG. Therefore, in this embodiment, the value of the SP2ENB flag 52 can be controlled without increasing the burden on the software (internal interrupt routine).

(Example 3)
Still another example of the operation of the stack determination circuit 50 will be described.

  In the second embodiment, according to the flow shown in FIG. 4, the stack end determination circuit 50 generates the first internal interrupt request signal INT1 when the SP2ENB flag = L, and the second when the SP2ENB flag = H. Generated an internal interrupt request signal INT2. That is, the stack end determination circuit 50 generates different internal interrupt request signals depending on the value of the SP2ENB flag. Then, upon receiving the first internal interrupt request signal INT1 and the second internal interrupt request signal INT2, the interrupt control unit 10 receives an interrupt signal for shifting to the first internal interrupt routine, and An interrupt signal for shifting to the second internal interrupt routine is output to the control unit 20.

  However, the internal interrupt request signals generated by the stack end determination circuit 50 can be the same, and different processing can be performed by software processing after shifting to the internal interrupt routine.

  FIG. 7 shows an example of the processing flow in this case. In the flow of FIG. 7, the stack end determination circuit 50 monitors the change of the SP 401 (ST31). When a change from FF04h to FF02h, that is, arrival at the end of the first stack area in the push operation is detected (ST32), the value of the SP2ENB flag 52 is further referred to (ST33). If SP2ENB = L, the stack end determination circuit 50 generates the first internal interrupt request signal INT1 (ST34). On the other hand, if SP2ENB = H, the stack end determination circuit 50 does not generate an internal interrupt request signal.

  Further, when the stack end determination circuit 50 detects the change of FF02h → FF04h, that is, the arrival at the end of the first stack area in the pop operation (ST35), the value of the SP2ENB plug 52 is further referred to (ST36). ). If SP2ENB = H, the stack end determination circuit 50 generates the second internal interrupt request signal INT2 (ST37). On the other hand, if SP2ENB = L, the stack end determination circuit 50 does not generate an internal interrupt request signal.

  Then, the OR of INT1 and INT2 is taken to generate an internal interrupt request signal INT (ST38) and output to the control unit 20. As a result, the CPU 1 shifts to an internal interrupt routine (ST40). In this internal interrupt routine, the SP2ENB flag 52 is read and its value is checked (ST41). If SP2ENB = L, the second stack area is secured (ST42), and the start address of the second stack area is written to the SPS2 register (ST43). End the internal interrupt routine.

  On the other hand, if SP2ENB = H in ST41, it is confirmed whether or not the second stack area secured by the previous operation can be released (ST44). Also do not. If the second stack area can be released, the second stack area is released (ST45), a dummy is written to the SPS2 register (ST46), and the internal interrupt routine is terminated.

  Also in this embodiment, the SP2ENB flag 52 that detects writing to the SPS2 register is set by the flow shown in FIG.

  In the flow shown in FIG. 7, the software (internal interrupt routine ST40) checks the value of the SP2ENB flag 52 and performs different processing accordingly. Therefore, more flexible stack area management is possible as compared to the flow shown in FIG. In addition, the processing up to the generation of the internal interrupt request signal INT is performed by hardware. Compared to the technique disclosed in Patent Document 2, the software load is small and high-speed processing is possible.

  In order to realize the flow of FIG. 7, it is necessary to be able to read the SP2ENB flag from the internal interrupt routine. For example, like other general-purpose registers, a function that enables reading of the SP2ENB flag from a data bus (not shown) is required.

  The embodiment of the present invention has been described in detail above. It goes without saying that the present invention is not limited to the specific examples described above, and various modifications and improvements are possible.

  For example, in the above embodiment, the stack end determination circuit 50 compares the address (FF02h) larger by 2 than the address (FF00h) held in the register SPE1 with the value of the stack pointer SP401, and generates an internal interrupt request signal. Is generated. That is, considering the address of 2 bytes for storing the return value of the program counter, the stack pointer address changes from (SPE1 + 4) to (SPE1 + 2) or from (SPE1 + 2) to (SPE1 + 4). An interrupt request signal is output when a transition occurs. However, the number of bytes to be incremented at this time is not limited to two, but depends on the data length of instructions supported by the CPU.

  In the above embodiment, the stack area of two addresses is used at one time, and the address closer to the end (smaller value) is used as the SP 401 value. In accordance with this, the actual end address FF00h of the first stack area is set in the SPE1 register 402 as it is as the end address of the first stack area. On the other hand, in the SPS2 register 403, F0FEh obtained by subtracting 1 from the actual start address F0FFh of the second stack area is set as the start address of the second stack area.

  Thus, the setting of the end address of the first stack area in the SPE1 register 402 and the setting of the start address of the second stack area in the SPS2 register 403 for use in control in the stack pointer control circuit 22 are as follows: This is appropriately performed according to the usage form of the stack area and the setting of SP 401. It goes without saying that the setting is not limited to the case of the above embodiment.

  In the above embodiment, as shown in FIG. 3, the stack push direction is the direction in which the address decreases, but the stack pop direction may be used in the direction in which the address decreases. Furthermore, in the above embodiment, the end address of the second stack area that is dynamically secured is not considered. However, a register for setting the end address of the second stack area is provided, and the value of the stack pointer is set to the address. It is also possible to secure the third stack area when there is a risk of exceeding the threshold.

  In the above-described embodiment, the memory area used as the second stack area is dynamically secured by arranging an instruction for dynamically securing the memory area or an instruction for releasing the memory area in the internal interrupt routine. The value of the start address was set in the SPS2 register 403. However, an architecture in which the start address of the second stack area is set in the SPS2 register after resetting is possible instead of assuming a mechanism that dynamically secures the memory area. In this case, it is advantageous in terms of easy implementation in terms of hardware configuration.

  As described above, according to the present invention, when an actual program is executed, even if there is a possibility that the stack area may consume memory beyond the initially assumed memory area, the data is destroyed without stopping the program. Can be avoided, and the problem that the program operates unexpectedly can be prevented. Further, such management of the stack area can be realized while suppressing an increase in software load, and a reduction in processing speed can be suppressed.

It is a figure which shows the block diagram of CPU of one Embodiment of this invention. It is a block diagram which shows an example of the stack pointer control circuit of this invention. It is a figure which shows the usage example of the stack area | region in the memory area of this invention. It is a flowchart which shows an example of operation | movement of the stack | stuck termination | terminus determination circuit of this invention. It is a flowchart which shows an example of control of the 2nd stack area | region enable flag of this invention. It is a circuit diagram which shows an example of the 2nd stack area | region enable flag control circuit of this invention. It is a flowchart which shows the other example of operation | movement of the stack | stack termination determination circuit of this invention. It is a figure which shows the register structure of Z80 which is the conventional CPU. It is a figure which shows the malfunction of the memory area in the conventional CPU.

Explanation of symbols

1 CPU
10 interrupt control unit 20 control unit 22 stack pointer control circuit 221 -2 / + 2 adder / subtracter 222 switch 223 comparator 30 ALU
40, 400 Register group 401 Stack pointer register
402 First stack area end address register 403 Second stack area start address register 50 Stack end determination circuit 52 Second stack area enable flag 54 Enable flag control circuit

Claims (10)

A stack pointer register that stores the start address of the current stack area;
A stack end register for setting the end address of the first stack area;
A second stack area start register for setting a start address of the second stack area;
In the next push operation when the address of the stack pointer register reaches the address set in the stack end register, the address of the stack pointer register is replaced with the address set in the second stack area start register, and A stack that replaces the address of the stack pointer register with the address set in the stack end register in the next pop operation when the address of the stack pointer register reaches the address set in the second stack area start register A CPU comprising a pointer control circuit. A stack end determination circuit for generating an internal interrupt request signal when the address of the stack pointer register reaches the end address of the first stack area or an address in the first stack area by a predetermined value from the end address; Prepared,
In the interrupt routine to be shifted by the internal interrupt request signal, dynamically securing the second stack area and setting a start address of the secured second stack area in the second stack area start register. The CPU according to claim 1, wherein   3. The CPU according to claim 2, wherein the stack end determination circuit generates different internal interrupt request signals for a push operation and a pop operation.   The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and refers to the value of the enable flag to determine the internal interrupt request signal. The CPU according to claim 2, wherein the CPU is generated.   The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and the enable flag is shifted by the internal interrupt request signal. 3. The CPU according to claim 2, wherein the CPU can be read from the interrupt routine. The second stack area start register is writable in the interrupt routine shifted by the internal interrupt signal, and the second stack area secured when the interrupt routine dynamically secures the second stack area. The start address of the area is written, and an invalid value is written when the interrupt routine releases the second stack area,
And,
6. The CPU according to claim 4, further comprising an enable flag control circuit for detecting the write to the second stack area start register and setting the enable flag. A stack pointer register for storing the start address of the current stack area, a stack end register for setting the end address of the first stack area, a second stack area start register for setting the start address of the second stack area, and the stack A stack end determination circuit for generating an internal interrupt request signal when the address of the pointer register reaches the end address of the first stack area or an address in the first stack area by a predetermined value from the end address. A stack area control method in a CPU,
In response to the internal interrupt request signal, the process proceeds to an interrupt routine, in which the second stack area is dynamically secured, and the start address of the secured second stack area is assigned to the second stack area start register. A stack area control method, characterized in that: During the push operation of the CPU, in the interrupt routine, dynamically securing the second stack area and setting the second stack area start address in the second stack area start register,
8. The stack area control method according to claim 7, wherein, during the pop operation of the CPU, the second stack area secured in the push-time interrupt routine is released in the interrupt routine. The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured;
8. The stack area control method according to claim 7, wherein in the interrupt routine, the value of the enable flag is read and different processing is performed according to the value of the enable flag. The stack end determination circuit includes a second stack area enable flag for storing a value indicating whether or not the second stack area is secured, and detects writing to the second stack area start register to Including an enable flag control circuit for setting the enable flag;
In the interrupt routine, when the second stack area is dynamically secured, the start address of the secured second stack area is written to the second stack area start register, and when the second stack area is released, the second stack area is released. 10. The stack area control method according to claim 7, wherein an invalid value is written to the two stack area start register.

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