JP2006197571A - Semiconductor integrated circuit device and radio communication equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a voltage controlled oscillation circuit capable of obtaining stable phase/noise characteristics is integrated, and radio communication equipment using the same. <P>SOLUTION: The semiconductor integrated circuit device comprises: a voltage controlled oscillation circuit 12; a maximum value detection circuit 13 for detecting a maximum value of oscillation outputs; a minimum value detection circuit 14 for detecting a minimum value; a reference voltage generation circuit 16 for outputting a predetermined voltage Vref; a bias current control circuit 17 connected in series to the voltage controlled oscillation circuit 12 for varying a bias current of the voltage controlled oscillation circuit 12 in accordance with a control voltage Vbias; and a differential amplifier 18 for outputting the control voltage Vbias to the bias current control circuit so that a difference between the maximum value of the oscillation outputs and the minimum value of the oscillation outputs becomes equal with a predetermined voltage Vref. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device in which a voltage controlled oscillation circuit is integrated and a wireless communication device using the same, and more particularly to a semiconductor integrated circuit device capable of obtaining stable oscillation characteristics and a wireless communication device using the semiconductor integrated circuit device.

  A wireless communication device such as a mobile communication terminal typified by a mobile phone has a voltage controlled oscillator (VCO) in which an oscillation frequency can be varied by an externally applied voltage in an RF (radio frequency) signal processing unit. There is something to do.

  In the conventional voltage controlled oscillator circuit, when the amplitude of the oscillation output signal is too small, the phase noise is deteriorated by noise, and when the amplitude of the oscillation output is excessive, the phase noise is deteriorated by distortion of the oscillation output signal. is there.

  When the voltage controlled oscillation circuit is composed of an insulated gate field effect transistor (MOS transistor), when the operation of the MOS transistor enters the linear region, that is, when the oscillation output amplitude exceeds the point at which the threshold voltage of the MOS transistor is reached. The oscillation output signal is distorted and the phase noise is deteriorated. Therefore, the amplitude of the oscillation output signal is adjusted by changing the bias current of the voltage controlled oscillation circuit so as to be equal to the threshold voltage.

  However, since the operating conditions such as the bias current and the threshold voltage of the MOS transistor vary depending on the usage environment such as temperature and power supply voltage and the oscillation frequency, there is a problem that the oscillation amplitude varies and the phase noise characteristics vary. Further, since the threshold voltage of the MOS transistor has manufacturing variations, there is a problem that the phase noise characteristic varies even if the amplitude of the oscillation output is fixed.

  On the other hand, a voltage-controlled oscillation circuit is known in which the amplitude of the oscillation output is fixed to a reference signal representing the maximum level immediately before distortion starts to occur in the transmission waveform, and phase noise is suppressed (see, for example, Patent Document 1). ).

  The voltage-controlled oscillation circuit disclosed in Patent Document 1 includes a constant collector / bias current source, a variable collector / bias voltage circuit, and a voltage-tuned resonance circuit.

  The variable collector bias voltage circuit detects the collector output amplitude of the transistor and changes the collector bias voltage using the integrated value of the difference from the reference signal to control the output amplitude to be constant.

  In addition, since the collector bias current is kept constant by the constant collector bias current source, the operating point of the transistor is kept in a constant relationship with respect to the emitter cutoff of the transistor.

  This makes the collector voltage sufficiently high according to the initial setting values of the constant collector bias current and reference voltage for each tuning voltage, and the bias is controlled so that a certain instantaneous current is zero, that is, the state immediately before emitter cut-off occurs. is doing.

However, in the voltage controlled oscillation circuit disclosed in Patent Document 1, the bias voltage that minimizes the phase noise is predicted by detecting the maximum value or the minimum value, not the amplitude of the oscillation output, and is fixed to the expected value. Since the amplitude of the oscillation output is controlled, there is a problem that sufficient phase noise characteristics cannot be obtained depending on manufacturing variations of transistors.
Japanese Patent Laid-Open No. 11-163631 (page 3, FIG. 2)

  The present invention provides a semiconductor integrated circuit device in which a voltage controlled oscillation circuit capable of obtaining stable phase noise characteristics is integrated, and a wireless communication device using the same.

  In order to achieve the above object, a semiconductor integrated circuit device according to one embodiment of the present invention includes a voltage controlled oscillation circuit, a maximum value detection circuit that detects a maximum value of an oscillation output of the voltage controlled oscillation circuit, and the voltage controlled oscillation. A minimum value detection circuit that detects the minimum value of the oscillation output of the circuit, a reference voltage generation circuit that outputs a predetermined voltage, and the voltage control oscillation circuit are connected in series, and a bias current of the voltage control oscillation circuit is determined by a control signal. A variable bias current control circuit; a control circuit that outputs the control signal to the bias current control circuit so that a difference between a maximum value of the oscillation output and a minimum value of the oscillation output is equal to the predetermined voltage; It is characterized by comprising.

  According to the present invention, the amplitude of the oscillation output can be maintained equal to the threshold voltage of the MOS transistor of the voltage controlled oscillation circuit that can obtain good phase noise characteristics.

  As a result, an oscillation output having good phase noise characteristics can be stably obtained, and a small and highly accurate wireless communication apparatus can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a circuit configuration of each block.

  As shown in FIG. 1, a semiconductor integrated circuit device 10 of this embodiment includes a voltage-controlled oscillation circuit 12 having a coil formed on a semiconductor substrate 11, for example, a silicon substrate, a variable capacitance diode, and an amplifier circuit. And a maximum value detection circuit 13 for detecting the maximum value Vmax of the oscillation output RFout of the voltage controlled oscillation circuit 12 and a minimum value detection circuit 14 for detecting the minimum value Vmin.

  Further, the reference voltage generating circuit 16 that outputs a predetermined reference voltage Vref, and one end of the current path of the voltage controlled oscillation circuit 12 and the power source Vdd are connected, and the voltage controlled oscillation circuit 12 is controlled by a control voltage (control signal) Vbias. A bias current control circuit 17 for changing the bias current Ibias of the input signal, a positive input terminal connected to the output terminal of the maximum value detection circuit 13 via the reference voltage generation circuit 16, and a negative input terminal connected to the output terminal of the minimum value detection circuit 14 And a differential amplifier 18 whose output end is connected to the control terminal of the bias current control circuit 17.

  When the bias current Ibias flows, the voltage controlled oscillation circuit 12 oscillates at the parallel resonance frequency of the resonance circuit having the coil and the variable capacitance diode by the positive feedback action of the amplifier circuit, and outputs the oscillation output RFout to the outside. The oscillation frequency is varied by the frequency control voltage Vctrl.

  The maximum value detection circuit 13 outputs a value corresponding to the maximum value Vmax of the oscillation output RFout. Similarly, the minimum value detection circuit 14 outputs a value corresponding to the minimum value Vmin of the oscillation output RFout.

  The reference voltage generation circuit 16 generates a predetermined reference voltage Vref. When the output Vmax of the maximum value detection circuit 13 is input, a voltage Vmax−Vref level-shifted by the reference voltage Vref is output.

  When the voltage Vmax−Vref is input to the positive input terminal and the voltage Vmin is input to the negative input terminal, the differential amplifier 18 outputs a control voltage Vbias proportional to the difference to the bias current control circuit 17.

  When the control voltage Vbias is applied to the bias current control circuit 17, the bias current Ibias of the voltage controlled oscillation signal circuit 12 is varied according to the control voltage Vbias, and the oscillation output RFout is controlled.

  Since the differential amplifier 18 operates so that the potentials at the positive and negative input terminals are equal, feedback control is performed so that the amplitude Vmax−Vmin of the oscillation output RFout becomes equal to the reference voltage Vref of the reference voltage generation circuit 16.

  Here, by setting the reference voltage Vref equal to the threshold voltage of the MOS transistor included in the amplifier circuit of the voltage control transmission circuit 12, a good phase noise characteristic of the oscillation output RFout can be obtained. As a result, it is possible to always maintain good phase noise characteristics even if the threshold voltage fluctuates due to manufacturing variations and usage environments of MOS transistors.

  Specifically, as shown in FIG. 2, the voltage controlled oscillation circuit 12 includes a resonance circuit 21 in which a reverse polarity series circuit of a coil L and variable capacitance diodes VC1 and VC2 is connected in parallel, and between the resonance circuit 21 and the ground GND. And a second amplifier circuit 23 connected between the power supply Vdd via the resonance circuit 21 and the bias current control circuit 17.

  The first amplifier circuit 22 includes first and second n-type MOS transistors (hereinafter simply referred to as transistors) M1 and M2 each having a drain (first electrode), a source (second electrode), and a gate (control electrode). The drain D1 of the first transistor M1 is connected to the gate G2 of the second transistor M2 and one end a of the coil L. The drain D2 of the second transistor M2 is connected to the gate G1 of the first transistor M1 and the other end b of the coil L. The sources S1 and S2 of the first and second transistors M1 and M2 are connected to ground.

  The second amplifier circuit 23 includes third and fourth p-type MOS transistors M3 and M4 having a drain (first electrode), a source (second electrode), and a gate (control electrode). The drain D3 is connected to the gate G4 of the fourth transistor M4 and one end a of the coil L, the drain D4 of the fourth transistor M4 is connected to the gate G3 of the third transistor M3 and the other end b of the coil L, and the third and third The sources S 3 and S 4 of the four transistors M 3 and M 4 are commonly connected to the bias current control circuit 17.

  As a result, the resonant circuit 21 having the coil L and the variable capacitance diodes VC1 and VC2 and the first and second amplification circuits 22 and 23 for positive feedback constitute a voltage controlled oscillation circuit 12.

  When a bias current Ibias is passed through the voltage controlled oscillation circuit 12, oscillation occurs at the parallel resonance frequency of the resonance circuit 21, and the oscillation output RFout is output to the outside from the output terminals Vout1 and Vout2 connected to one end a and the other end b of the coil L. Is done. The oscillation frequency is varied by the frequency control voltage Vctrl.

  The maximum value detection circuit 13 includes fifth and sixth n-type MOS transistors M5 and M6, and gates G5 and G6 are connected to the first and second output terminals Vout1 and Vout2 of the voltage controlled oscillation circuit 12, respectively. The drains D5 and D6 are commonly connected to the power supply Vdd, and the sources S5 and S6 are grounded through a parallel circuit of the constant current source 24 and the capacitive element C1, respectively.

  Here, the threshold voltages Vthn of the first, second, fifth, and sixth transistors M1, M2, M5, and M6 are all set equal.

  Due to the rectifying action of the fifth and sixth transistors M5 and M6 and the capacitive element C1, the potential of the terminal c is held at a value when the voltage of the oscillation output becomes maximum. Further, since the fifth and sixth transistors M5 and M6 are driven by the current at the start of conduction by the constant current source 24, the voltage Vgs between the gate G5 and the source S5 is substantially the threshold value of the fifth and sixth transistors M5 and M6. It becomes equal to the voltage Vthn.

  As a result, the maximum value Vmax of the oscillation output RFout and the threshold voltage Vthn of the fifth and sixth transistors M5 and M6 at the connection point c between the sources S5 and S6 of the fifth and sixth transistors M5 and M6 and the constant current source 24 A difference voltage Vmax−Vthn is obtained.

  The minimum value detection circuit 14 includes seventh and eighth p-type MOS transistors M7 and M8, and gates G7 and G8 are connected to the first and second output terminals Vout1 and Vout2 of the voltage controlled oscillation circuit 12, respectively. The sources S7 and S8 are commonly connected to the power source Vdd via a parallel circuit of the constant current source 25 and the capacitive element C2, and the drains D7 and D8 are commonly grounded.

  In the same manner as the maximum value detection circuit 13, the minimum value Vmin of the oscillation output RFout and the seventh and eighth transistors M7, M7, M8, the drain D7, D8 of the seventh and eighth transistors M7, M8 and the constant current source 25 are connected to the connection point d. A voltage Vmin + | Vthp | which is the sum of the threshold voltage | Vthp | of M8 is obtained.

  The reference voltage generation circuit 16 includes a ninth p-type MOS transistor M9, the gate G9 is connected to the connection point c between the sources S5 and S6 of the MOS transistors M5 and M6 and the constant current source 24, and the source S9 is a constant current. The power source Vdd is connected via the source 26, and the drain D9 is grounded.

  When a conduction start current is passed through the ninth transistor M9 by the constant current source 26, the threshold voltage | Vthp | of the ninth transistor M9 is obtained as the voltage | Vgs | between the source S9 and the gate G9.

  When the voltage Vmax−Vthn is applied to the gate G9 of the ninth transistor M9, the level is shifted by the threshold voltage | Vthp | of the ninth transistor M9 to the connection point e between the drain D9 of the ninth transistor M9 and the constant current source 26. An output voltage Vmax−Vthn + | Vthp | is obtained.

  Here, the threshold voltages | Vthp | of the p-type MOS transistors M7, M8, and M9 are all set equal.

  The differential amplifier 18 has a positive input terminal connected to the connection point e of the source S9 of the ninth transistor M9 and the constant current source 26, and a negative input terminal fixed to the sources D7 and D8 of the seventh and eighth transistors M7 and M8. The connection point d of the current source 25 is connected.

  When the voltage Vmax−Vthn + | Vthp | is input to the positive input terminal and the voltage Vmax + | Vthp | is input to the negative input terminal, the differential amplifier 18 supplies the control voltage Vbias proportional to the difference to the bias current control circuit 17. Output to.

  The bias current control circuit 17 includes a tenth p-type MOS transistor M10, the gate G10 is connected to the output terminal of the differential amplifier 12, the source S10 is connected to the power supply Vdd, and the drain D10 is connected to the second amplifier circuit 23. The third and fourth transistors M3 and M4 are commonly connected to the sources S3 and S4.

  When the control voltage Vbias is applied to the gate G10 of the tenth transistor M10, the tenth transistor M10 is turned on according to the control voltage Vbias, the bias current Ibias of the voltage controlled oscillation circuit 12 is varied, and the oscillation output RFout is controlled. The

  That is, since the differential amplifier 18 operates so that the potentials at the positive and negative input terminals are equal, feedback control is performed so that the amplitude Vmax−Vmin of the oscillation output RFout is equal to the threshold voltage Vthn of the n-type MOS transistor.

  As a result, the amplitude Vmax−Vmin of the oscillation output RFout is always kept equal to the threshold voltage Vthn at which a good phase noise characteristic can be obtained. It is possible to suppress fluctuations in the phase noise characteristics.

  3 to 5 show the phase noise characteristics of the semiconductor integrated circuit device 10 having the voltage controlled oscillation circuit 12. FIG. 3 shows the threshold voltage dependence of the phase noise characteristics, and FIG. 4 shows the operating temperature of the phase noise characteristics. FIG. 5 is a simulation result showing the power supply voltage dependency of the phase noise characteristic.

  In each figure, the figure (a) shows the result of the oscillation frequency of 4.8 GHz and the detuning frequency of 200 KHz, and the figure (b) shows the result of the oscillation frequency of 4.8 GHz and the detuning frequency of 6 MHz. As a comparison, this is the case of the conventional example that does not have the maximum value detection circuit 13, the minimum value detection circuit 14, the reference voltage generation circuit 16, the bias current control circuit 17, and the differential amplifier 18.

  As apparent from FIG. 3, according to the present embodiment, the phase noise characteristics at the detuning frequency of 200 KHz and the detuning frequency of 6 MHz are −105 dBc / Hz and −135 dBc /, respectively, regardless of the change in the threshold voltage Vthn of the MOS transistor. On the other hand, in the conventional example, when the threshold voltage Vthn used as a reference varies by ± 0.1 V from the design value, the phase noise characteristics deteriorate rapidly.

  In this embodiment, even if the threshold voltage Vthn changes due to manufacturing variations, the bias current Ibias changes so that the amplitude Vmax−Vmin of the oscillation output follows the threshold voltage Vthn. This is because the bias current is set so that the amplitude of the oscillation output in accordance with the reference threshold voltage Vthn can be obtained, so that the amplitude Vmax−Vmin of the oscillation output deviates from the condition for obtaining good phase noise characteristics. .

  As apparent from FIG. 4, according to the present embodiment, the phase noise characteristics at the detuning frequency of 200 KHz and the detuning frequency of 6 MHz are substantially constant at −105 dB / Hz and −135 dBc / Hz, respectively, regardless of the change in the operating temperature. On the other hand, in the conventional example, when the operating temperature is lowered or increased from 27 ° C. as a reference, the phase noise characteristics are rapidly deteriorated.

  In this embodiment, even if the threshold voltage Vthn changes due to a temperature change, the bias current changes so that the amplitude Vmax−Vmin of the oscillation output follows the change in the threshold voltage Vthn, whereas in the conventional example, This is because, since the bias current is fixed, the amplitude Vmax−Vmin of the oscillation output deviates from the condition for obtaining good phase noise characteristics.

  As apparent from FIG. 5, according to the present embodiment, the phase noise characteristics at the detuning frequency of 200 KHz and the detuning frequency of 6 MHz are substantially constant at −105 dB / Hz and −135 dBc / Hz, respectively, regardless of the change in the power supply voltage. On the other hand, in the conventional example, when the power supply voltage is lowered or increased from 2.5 V as a reference, the phase noise characteristic is rapidly deteriorated.

  In this embodiment, the bias current changes so that the amplitude Vmax−Vmin of the oscillation output becomes constant even when the power supply voltage increases or decreases, whereas in the conventional example, the bias current changes according to the increase or decrease of the power supply voltage. This is because the amplitude Vmax−Vmin of the oscillation output also changes and deviates from the condition for obtaining good phase noise characteristics.

  As a result, it is recognized that an oscillation characteristic having a good phase noise characteristic can be obtained regardless of manufacturing variations of the threshold voltage Vthn and changes in the use environment.

  FIG. 6 is a block diagram showing a configuration of a wireless communication apparatus using the semiconductor integrated circuit device 10 having the voltage controlled oscillation circuit shown in FIG.

  As shown in FIG. 6, the wireless communication device 40 of this embodiment includes an antenna 41 that transmits or receives a radio signal, a switch 42 that selects whether the antenna 41 transmits or receives a radio signal, A signal transmission unit 43 that outputs a radio signal processed from an input signal input from a baseband LSI or the like to the antenna 41, and a signal reception unit 44 that processes the radio signal received by the antenna 41 and outputs the signal to the outside. is doing.

  The signal transmission means 43 outputs an output signal of the input signal processing circuit 45 based on an output signal of an input signal processing circuit 45 that processes an externally input signal and a first semiconductor integrated circuit device 46 having a voltage controlled oscillation circuit. A modulation circuit 47 that modulates the signal and a power amplifier 48 that amplifies the output signal of the modulation circuit 47 and outputs the amplified signal to the antenna 41 are provided.

  The signal receiving means 44 mixes the output signal of the low-noise amplifier 49 that amplifies the radio signal received by the antenna 41, the output of the low-noise amplifier 49, and the second semiconductor integrated circuit device 50 having the voltage-controlled oscillation circuit to generate the radio signal. A demodulating circuit 51 for demodulating and an output signal processing circuit 52 for processing the demodulated signal and outputting the processed signal to the outside are provided.

  This makes it possible to transmit externally input signals such as audio / image signals compressed by a predetermined compression method and to encode or decode received signals to reproduce the original audio / image signals due to noise malfunction. It is possible to carry out stably.

  As described above, according to this embodiment, since the amplitude Vmax−Vmin of the oscillation output is detected and feedback controlled to the bias current Ibias of the voltage controlled oscillation circuit 12, the amplitude Vmax−Vmin of the oscillation output is always obtained. Can be kept equal to the threshold voltage of the MOS transistor of the voltage-controlled oscillation circuit that provides good phase noise characteristics.

  As a result, it is possible to stably obtain an oscillation output having a favorable phase noise characteristic even if there is a manufacturing variation in the threshold voltage Vthn of the MOS transistor or a change in use environment, and a small and highly accurate wireless communication device is provided. Can do.

  Here, the case where the wireless communication apparatus 40 includes both the signal transmission unit 43 and the signal reception unit 44 has been described, but only one of them may be provided.

FIG. 7 is a circuit diagram showing a main part of the semiconductor integrated circuit device according to the second embodiment of the present invention, and shows a portion replaced in place of the differential amplifier 18 shown in FIG.
In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment differs from the first embodiment in that the control voltage is swept so that the amplitude of the oscillation output is equal to the threshold voltage of the MOS transistor.

  That is, the output Vmax of the maximum value detection circuit 13 level-shifted by the reference voltage Vref of the reference voltage generation circuit 16 shown in FIG. 1 is compared with the output Vmin of the minimum value detection circuit 14, and the control voltage Vbias is determined according to the comparison result. And the bias current Ibias of the current control circuit 17 is controlled.

  As a result, it is possible to tune the phase noise characteristic by controlling the amplitude Vmax−Vmin of the oscillation output only when the power is turned on or when necessary.

  Specifically, as shown in FIG. 7A, in the semiconductor integrated circuit device of this embodiment, the positive input terminal is connected to the connection point e in the reference voltage generation circuit 16, and the negative input terminal is the minimum value detection circuit. 14 and a control signal sweep circuit 61 connected between the comparator 60 and the bias current control circuit 17.

  The comparator 60 compares the voltage Vmax−Vthn + | Vthp | with the voltage Vmin + | Vthp | in synchronization with the clock signal CLK, and outputs the comparison result to one input terminal of the AND circuit 62.

  The control signal sweep circuit 61 includes an AND circuit 62 that obtains a logical product of the output of the comparator 60 and the tuning signal TUNE, a counter 63 that counts the clock signal CLK based on a calculation result of the AND circuit 62, and an analog value of the count value of the counter 63. A D / A converter 64 for converting the voltage into a voltage and outputting the conversion result to the gate G10 of the tenth transistor M10.

  When the tuning signal TUNE is input to the AND circuit 62 when the power is turned on or when tuning is required, the enable signal ENABLE is activated and the counter 63 is reset at the same time, and the counter 63 starts counting the clock signal CLK.

The D / A converter 64 converts the count value (digital value) of the counter 63 into an analog voltage and outputs a control voltage Vbias.
As a result, as shown in FIG. 7B, the control voltage Vbias is swept linearly from the power supply voltage Vdd to the ground GND potential here, so that the bias current Ibias is controlled according to the control voltage Vbias, and the oscillation The amplitude Vmax−Vmin of the output RFout increases.

  When the amplitude Vmax−Vmin of the oscillation output RFout exceeds the threshold voltage Vthn of the n-type MOS transistor, the output of the comparator 60 is inverted and the enable signal ENABLE becomes inactive, so the counter 63 stops counting the clock signal CLK. To do.

  Therefore, since the control voltage Vbias is held at the value when the count of the clock signal CLK is stopped, the amplitude Vmax−Vmin of the oscillation output RFout can be made equal to the threshold voltage Vthn of the n-type MOS transistor.

  Thus, the semiconductor integrated circuit device having the voltage controlled oscillation circuit in which the differential amplifier 18 shown in FIG. 2 is replaced with the comparator 60 and the control signal sweep circuit 61 is replaced with the first and second semiconductor integrated circuit devices 46 shown in FIG. 50.

  As described above, the semiconductor integrated circuit device of the present embodiment is necessary because the control voltage Vbias is swept so that the amplitude Vmax−Vmin of the oscillation output RFout becomes equal to the threshold voltage Vthn of the n-type MOS transistor. The phase noise characteristic can be tuned only when

  Therefore, there is an advantage that the degree of freedom is increased in the design of a PLL (Phase Locked Loop) circuit using a voltage controlled oscillation circuit, which is suitable for incorporation in a digital integrated circuit.

  FIG. 8 is a circuit diagram showing the main part of the semiconductor integrated circuit device according to the third embodiment of the present invention. The replacement part of the control signal sweep circuit 61 shown in FIG. 7 and the replacement of the bias current control circuit 17 shown in FIG. The part to be replaced with is shown.

  In the present embodiment, the same components as those in the first embodiment and the second embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment differs from the first and second embodiments in that the bias current control circuit is a parallel circuit of a plurality of MOS transistors.

  That is, the bias current Ibias of the bias current control circuit 17 shown in FIG. 1 is controlled from an analog value to a digital value.

  As a result, the bias current control circuit 17 can be replaced from an analog circuit to a digital circuit more suitable for integration.

  Specifically, as shown in FIG. 8A, the semiconductor integrated circuit device of this embodiment includes an AND circuit 62 that obtains the logical product of the output of the comparator 60 and the tuning signal TUNE, and the operation result of the AND circuit 62. A control signal sweeping circuit 71 having a counter 63 that counts the clock signal CLK and a decoder 70 that decodes the count value (digital value) of the counter 63 and outputs a control signal.

  Further, the gates G72 of the plurality of p-type MOS transistors 72 are connected to the respective output terminals of the decoder 70, the sources S72 of the plurality of MOS transistors 72 are commonly connected to the power supply Vdd, and the drains D72 of the plurality of MOS transistors 72 are connected to the voltage. A bias current control circuit 73 is commonly connected to the common connection point of the drains D3 and D4 of the third and fourth transistors M3 and M4 of the control oscillation circuit 12.

  When the tuning signal TUNE is input to the AND circuit 62 when the power is turned on or when tuning is required, the enable signal ENABLE is activated and the counter 63 is reset at the same time, and the counter 63 starts counting the clock signal CLK.

  The decoder 70 decodes, for example, the n-bit count value of the counter 63 into 2 n power signals and outputs them to the gates G 72 of the 2 n MOS transistors 72, respectively. N-th MOS transistors 72 are sequentially turned on.

  As a result, as shown in FIG. 8B, the bias current Ibias of the voltage controlled oscillation circuit 12 is swept in steps, so that the amplitude Vmax−Vmin of the oscillation output RFout increases.

  When the amplitude Vmax−Vmin of the oscillation output RFout exceeds the threshold voltage Vthn of the n-type MOS transistor, the output of the comparator 60 is inverted and the enable signal ENABLE becomes inactive, so the counter 63 stops counting the clock signal CLK. To do.

  Accordingly, since the plurality of MOS transistors 72 are held in the conductive state when the counting of the clock signal CLK is stopped, the amplitude Vmax−Vmin of the oscillation output RFout can be made equal to the threshold voltage Vthn of the n-type MOS transistor. It is.

  Thus, the semiconductor integrated circuit device having the voltage controlled oscillation circuit in which the control signal sweep circuit 61 shown in FIG. 7 is replaced with the control signal sweep circuit 71 and the bias current control circuit 17 shown in FIG. The first and second semiconductor integrated circuit devices 46 and 50 shown in FIG.

  As described above, in the semiconductor integrated circuit device of this embodiment, the bias current control circuit is changed from an analog circuit to a digital circuit that sweeps the bias current by switching a plurality of MOS transistors 72, so that it is incorporated in the digital integrated circuit. There are further advantages.

  FIG. 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

This embodiment differs from the first embodiment in that the phase noise characteristic and amplitude of the oscillation output can be controlled independently.
In the first embodiment, the amplitude Vmax−Vmin of the oscillation output RFout is fixed to a voltage equal to the threshold voltage Vthn of the n-type MOS transistor exhibiting good phase noise characteristics.

  In this embodiment, the threshold voltage Vthn of the n-type MOS transistor is varied using the substrate bias effect, so that the amplitude Vmax−Vmin of the oscillation output RFout can be varied while maintaining good phase noise characteristics. It is in.

  That is, a circuit for applying a voltage for controlling the threshold voltage to the back gate of the MOS transistor included in the amplifier circuit of the voltage controlled oscillation circuit 12 shown in FIG.

  As a result, it is possible to obtain an oscillation output RFout having an amplitude Vmax−Vmin equal to the varied threshold voltage and good phase noise characteristics. Further, the present invention can be applied to the second and third embodiments.

  Specifically, as shown in FIG. 9, in the semiconductor integrated circuit device 80 of the present embodiment, an eleventh n-type in which the drain D11 is connected to the power supply Vdd via the constant current source 81 and the source S11 is grounded. The MOS transistor M11, the positive input terminal is connected to the gate G11 of the eleventh transistor M11, the negative input terminal is connected to the power supply 82 that outputs a predetermined reference voltage Vref2, and the output terminal is the back gate B11 of the eleventh transistor M11. A threshold voltage control circuit 84 having a differential amplifier 83 connected to the back gates B1 and B2 of the first and second transistors M1 and M2 of the first amplifier circuit 22 is provided.

  Furthermore, the source S12 is grounded via the constant current source 85, the drain D12 is connected to the power supply Vdd, and the gate G12 has a twelfth n-type MOS transistor M12 connected to the connection point d of the minimum value detection circuit 14. The second reference voltage generation circuit 86 has a positive input terminal connected to the connection point e of the reference voltage generation circuit 16 and a negative input terminal connected to the source S12 of the twelfth transistor M12 of the second reference voltage generation circuit 86 and the constant current source 85. The subtractor 87 is connected to the connection point f.

  The eleventh transistor M11 has a threshold voltage equal to the threshold voltage of the first and second transistors M1 and M2 of the first amplifier circuit 22.

  Since the eleventh transistor 11 is driven by the current at the start of conduction by the constant current source 81, the voltage Vgs between the gate G11 and the source S11 is substantially equal to the threshold voltage Vthn of the eleventh transistor M11.

  Since the differential amplifier 83 feeds back the output voltage to the back gate B11 of the eleventh transistor M11 so that the potential difference between the positive and negative input terminals becomes zero, the potential of the back gate B11 shifts, and the threshold voltage Vthn of the eleventh transistor M11 is It becomes equal to the reference voltage Vref2.

  Similarly, the back gates B1 and B2 of the first and second transistors M1 and M2 of the first amplifier circuit 22 are commonly connected to the output terminal of the differential amplifier 83, so that the first and second transistors M1 and M2 The threshold voltage is also equal to the reference voltage Vref2.

  Since the voltage Vmax−Vthn + | Vthp | is input to the positive input terminal of the subtractor 87 and the voltage Vmin + | Vthp | −Vthn is input to the negative input terminal, the difference voltage Vmax−Vmin is obtained at the output terminal. It is done.

  The positive input terminal of the differential amplifier 18 is connected to the output terminal of the subtractor 87, the amplitude Vmax−Vmin of the oscillation output RFout is input, the negative input terminal is connected to the reference voltage 82, and the reference voltage Vref2 is input. .

  As a result, feedback control is performed by the differential amplifier 18 so that the amplitude Vmax−Vmin of the oscillation output RFout is equal to the reference voltage Vref2 and equal to the threshold voltage Vthn of the n-type MOS transistor exhibiting good phase noise characteristics.

  Therefore, it is possible to vary the amplitude Vmax−Vmin of the oscillation output RFout according to the reference voltage Vref2 while maintaining good phase noise characteristics.

  Thereby, the semiconductor integrated circuit device 80 can be made into the 1st and 2nd semiconductor integrated circuit devices 46 and 50 shown in FIG.

  As described above, in the semiconductor integrated circuit device 80 of the present embodiment, the threshold voltage Vthn of the first and second transistors M1 and M2 of the first amplifier circuit 22 is shifted to the reference voltage Vref2, so that favorable phase noise is achieved. While maintaining the characteristics, the amplitude Vmax−Vmin of the oscillation output RFout can be varied in accordance with the reference voltage Vref2.

  Therefore, there is an advantage that the oscillation output RFout can be set according to the external circuit while maintaining good phase noise characteristics.

  In the above-described embodiment, the circuit in which the amplitude of the oscillation output is equal to the threshold voltage vthn of the n-type MOS transistor has been described. However, the phase noise characteristic is improved by the p-type MOS transistor of the voltage controlled oscillation circuit 12 entering the linear region. In a circuit configuration that deteriorates, for example, when the bias current control circuit 17 is connected between the voltage controlled oscillation circuit 12 and the ground GND, the amplitude of the oscillation output RFout becomes the threshold voltage | Vthp | of the p-type MOS transistor. You may control as follows.

  In that case, as shown in FIG. 10, the transistor of the reference voltage generation circuit 16 is changed from the p-type MOS transistor M9 to the source follower of the n-type MOS transistor M13, and the transistor of the bias current control circuit 17 is changed to the p-type MOS transistor. The M10 is changed to the n-type MOS transistor M14.

  As a result, the positive input terminal of the differential amplifier 18 is connected to the output terminal d of the minimum value detection circuit 14 via the reference voltage generation circuit 16, and the negative input terminal is connected to the output terminal c of the maximum value detection circuit 14. .

  Further, the case where both the first and second amplifier circuits 22 and 23 are used as the positive feedback amplifier of the voltage controlled oscillation circuit 12 has been described, but either one may be used.

  Further, the case where a MOS transistor (insulated gate type field effect transistor) is used as the transistor has been described. However, a bipolar transistor having a collector (first electrode), an emitter (second electrode), and a base (control electrode) is used. Is also possible.

1 is a block diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 3 is a diagram showing the relationship between the phase noise characteristic of the semiconductor integrated circuit device according to the first embodiment of the present invention and the threshold voltage of a MOS transistor. FIG. 3 is a diagram showing a relationship between phase noise characteristics and operating temperature of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a relationship between a phase noise characteristic and a power supply voltage of the semiconductor integrated circuit device according to the first embodiment of the present invention. 1 is a block diagram showing a wireless communication device using a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 5 is a circuit diagram showing a main part of a semiconductor integrated circuit device according to a second embodiment of the invention. FIG. 6 is a circuit diagram showing a main part of a semiconductor integrated circuit device according to Example 3 of the invention. FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. The circuit diagram which shows the structure of the semiconductor integrated circuit device based on another Example of this invention.

Explanation of symbols

10, 80, 90 Semiconductor integrated circuit device 11 Semiconductor substrate 12 Voltage controlled oscillation circuit 13 Maximum value detection circuit 14 Minimum value detection circuit 16 Reference voltage generation circuit 17, 73 Bias current control circuit 18, 83 Differential amplifier 21 Parallel resonant circuit 22 First amplifier 23 Second amplifier 24, 25, 26, 81, 85 Constant current source 40 Wireless communication device 41 Antenna 42 Switch 43 Signal transmission means 44 Signal reception means 45 Input signal processing circuit 46 First semiconductor integrated circuit device 47 Modulation Circuit 48 Power amplifier 49 Low noise amplifier 50 Second semiconductor integrated circuit device 51 Demodulator circuit 52 Output signal processing circuit 60 Comparator 61, 71 Control signal sweep circuit 62 AND circuit 63 Counter 64 D / A converter 70 Decoder 82 Power supply 84 Threshold voltage control circuit 86 Second reference voltage generation circuit 87 Subtractor 1, M2, M5, M6, M11, M12, M13, M14 n-type MOS transistors M3, M4, M7, M8, M9, M10, 72 p-type MOS transistors L coils C1, C2 capacitance elements CV1, VC2 variable capacitance diode RFout Oscillation output Vmax Maximum value of oscillation output Vmin Minimum value of oscillation output Vthn Threshold voltage of n-type MOS transistor | Vthp | Threshold voltage of p-type MOS transistor Vbias Control voltage Ibias Bias current Vdd Power supply Vref, Vref2 Reference voltage CLK Clock signal out1, out2 output terminal

Claims (5)

A voltage controlled oscillator circuit;
A maximum value detection circuit for detecting the maximum value of the oscillation output of the voltage controlled oscillation circuit;
A minimum value detection circuit for detecting a minimum value of the oscillation output of the voltage controlled oscillation circuit;
A reference voltage generating circuit for outputting a predetermined voltage;
A bias current control circuit that is connected in series to the voltage controlled oscillation circuit and varies a bias current of the voltage controlled oscillation circuit according to a control signal;
A control circuit for outputting the control signal to the bias current control circuit so that a difference between the maximum value of the oscillation output and the minimum value of the oscillation output is equal to the predetermined voltage;
A semiconductor integrated circuit device comprising:   2. The semiconductor integrated circuit device according to claim 1, wherein the voltage-controlled oscillation circuit includes an LC resonance circuit and an insulated gate field effect transistor for positive feedback.   2. The semiconductor integrated circuit device according to claim 1, wherein the predetermined voltage is equal to a threshold voltage of an insulated gate field effect transistor for positive feedback of the voltage controlled oscillation circuit. A constant current source;
An insulated gate field effect transistor connected in series to the constant current source;
One input terminal is connected to the gate of the insulated gate field effect transistor, the other input terminal is connected to a predetermined reference power source, the output terminal is a substrate terminal or a source terminal of the insulated gate field effect transistor, and the voltage control A differential amplifier connected to the substrate terminal or source terminal of the insulated gate field effect transistor in the oscillation circuit;
The semiconductor integrated circuit device according to claim 1, further comprising: 5. A first semiconductor integrated circuit device according to claim 1, wherein an input signal input from the outside is modulated based on an oscillation output signal of the first semiconductor integrated circuit device, and modulated. Signal transmitting means for transmitting the output signal from an antenna;
5. A second semiconductor integrated circuit device according to claim 1, wherein the received signal received by the antenna is demodulated and demodulated based on the oscillation output signal of the second semiconductor integrated circuit device. Signal receiving means for outputting the received signal to the outside;
A wireless communication apparatus comprising at least one of the following.

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