JP2003110386A - Amplifier circuit and disk device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier circuit for amplifying a detected signal to obtain a signal which has optimum amplitude to be decoded and a disk device which uses this amplifier circuit. SOLUTION: In a disk device (100, 200) having a detector section (15) for detecting a signal from a disk (10) and a decoder (43) for decoding data recorded on the disk (10) based on the signal detected at the detector section (15), there are provided an amplifier section (111; 212) having a variable amplification factor for amplifying the detected signal, an amplitude detector circuit (112, 113, 114; 214) for detecting the amplitude of the detected signal, and an amplification factor control circuit (115; 22) for detecting the difference between the amplitude detected at the amplitude detector circuit (112, 113, 114; 214) and the target amplitude, and controlling the amplification factor of the amplifier circuit so that the output signal amplitude becomes the target amplitude, in response to the detected difference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit and a disk device using the same, and more particularly to an amplifier circuit for amplifying a detection signal for decoding and a disk device using the same.

[0002]

2. Description of the Related Art FIG. 1 shows a block diagram of an optical disk device.

The optical disk device 1 is a CD-R (record-a
ble) / RW (rewrite-able) device, which includes a drive disc tray 11, a loading motor 12, a turntable 13, a spindle motor 14, and a pickup 1.
5, a sled motor 16, drivers 17 and 18, a laser driver 19, an analog signal processing unit 20, a digital signal processing unit 21, a CPU 22, a ROM 23, and an eject button 24.

By loading the disk 10 on the disk tray 11 and operating the eject button 24, the loading motor 12 is driven and the tray 11 is drawn into the apparatus. The disk 10 mounted on the tray 11 is engaged with the turntable 13 by pulling the tray 11 into the apparatus. The turntable 13 is fixed to the rotation shaft of the spindle motor 14, and rotates according to the rotation of the spindle motor 14. The disk 10 rotates as the turntable 13 rotates. The loading motor 12 and the spindle motor 14 are driven by a drive signal from the driver 17. The driver 17 generates a loading motor drive signal based on the loading control signal supplied from the CPU 22, supplies the loading motor drive signal to the loading motor 12, and generates a spindle motor drive signal based on the spindle control signal from the digital signal processing unit 21. Spindle motor 1
Supply to 4.

A pickup 15 is arranged on the disk 10 so as to face it. The pickup 15 has a built-in laser diode for irradiating the disk 10 with laser light. The output of the laser diode is controlled according to the drive signal from the LD control unit 34. In addition, the LD control unit 34 monitors the monitor signal for monitoring the emission light amount of the laser diode, and drives so that the emission light amount from the laser diode becomes the light amount according to the laser control signal generated inside the analog signal processing unit 20. Control the signal. Further, the pickup 15 has a built-in photodetector that detects a focus error signal, a tracking error signal, and a reproduction signal from the reflected light of the disk 10. The focus detection signal, tracking detection signal, and reproduction signal detected by the photodetector are supplied to the analog signal processing unit 20.

The analog signal processing section 20 includes a high frequency amplifier 31, an error signal generating circuit 32, a wobble signal generating circuit 33, a laser control circuit 34 and an interface 3.
It is configured to include 5.

The high frequency amplifier 31 includes a pickup 15
The detection signal from is supplied. The high frequency amplifier 31 amplifies the detection signal with a preset fixed gain. At this time, if the amplitude of the detection signal becomes too large, the detection signal is clipped inside the analog signal processing unit 20, and normal decoding cannot be performed at the time of decoding. Therefore, the gain is set within a range in which the amplitude of the detection signal does not clip during decoding.

The focus detection signal and the tracking detection signal are supplied to the error signal generation circuit 32.
The error signal generation circuit 32 generates a focus error signal from the focus detection signal and a tracking error signal from the tracking detection signal, and the digital signal processing unit 21.
Supply to.

The wobble signal generation circuit 33 extracts a wobble component from the detection signal, generates a wobble signal, and supplies it to the digital signal processing section 21. LD driver 19
Uses a digital laser control signal from the digital signal processing unit 21 to convert a drive signal for driving the laser diode into pulses at appropriate intervals, and supplies the pulse to the laser diode.

The digital signal processing section 21 includes a servo circuit 41, a spindle control circuit 42, and a decoder 4.
3, the demodulator 44, the encoder 45, and the interface 46 are included.

A focus error signal and a tracking error signal are supplied to the servo circuit 41 from the analog signal processing section 20. The servo circuit 41 generates a focus control signal based on the focus error signal and a tracking control signal based on the tracking error signal, and supplies the tracking control signal to the driver 18. The driver 18 drives the focus control actuator built in the pickup 15 based on the focus control signal from the digital signal processing unit 21. Further, the driver 18 drives the tracking control actuator built in the sled motor 16 and the pickup 15 based on the tracking control signal from the digital signal processing unit 21.

The spindle control circuit 42 is supplied with rotation information from the servo circuit 41 and a rotation frequency signal from the spindle motor 14. The spindle control circuit 42 controls the rotation of the spindle motor 14 based on the rotation information from the servo circuit 41 and the rotation frequency signal from the spindle motor 14.

The decoder 43 includes an analog signal processing section 2
The detection signal is supplied from the high frequency amplifier 31 of 0. The decoder 43 slices the detection signal from the high frequency amplifier 31 with a predetermined threshold value and decodes it into data according to the obtained pulse. A wobble signal is supplied to the demodulator 44 from the wobble signal generation circuit 33 of the analog signal processing unit 20. The demodulator 44 demodulates information from the wobble signal. The encoder 45 encodes the information from the interface 46 and supplies it to the LD driver 19. The interface 46 interfaces with an external device.

A ROM 23 and an eject button 24 are connected to the CPU 22. CPU22 is a ROM
The entire operation is controlled based on the firmware stored in 23. In addition, the CPU 22 uses the eject button 2
When the operation of No. 4 is detected, the driver 17 is controlled by the firmware to drive the loading motor 12 to open / close the disc tray 11.

[0015]

However, in the conventional high frequency amplifier 31, the first condition is not to clip,
Further, since the gain of the high frequency amplifier 31 is set to a fixed value, in consideration of variations in the detection signal due to various factors, it is unavoidable to set the gain such that an amplitude smaller than the best amplitude can be obtained.

The present invention has been made in view of the above points, and an object of the present invention is to provide an amplifier circuit which can obtain a signal having an optimum amplitude for decoding, and a disk device using the amplifier circuit.

[0017]

An amplifier circuit (101; 201) according to claim 1 of the present invention comprises an amplifier section (111; 212) for amplifying an input signal with a variable amplification degree, and the amplifier section (111). 212) and an amplitude detection circuit (112, 113, 114; 214) for detecting the amplitude of the output signal, and a difference between the amplitude detected by the amplitude detection circuit (112, 113, 114; 214) and the target amplitude. An amplification degree control circuit (1) that controls the amplification degree of the amplification circuit so that the amplitude of the output signal becomes the target amplitude according to the detected difference.
15; 22).

A second aspect of the present invention is the amplitude detection circuit (1
12, 113, 114; 214) is the amplification unit (11
1; 212), a peak value detection circuit (112; 214) for detecting the peak value of the output signal, and the amplification section (111;
212) and a bottom value detection circuit (113; 214) for detecting the bottom value of the output signal.

According to a third aspect of the present invention, a detector (15) for detecting a detection signal from the disc (10) and data recorded on the disc based on the detection signal (15) detected by the detector (15). (43) that decodes
In a disk device (100; 200) having
An amplification unit (111; 212) for amplifying the detection signal, the amplification degree of which is changed, and the amplification unit (111; 212).
Amplitude detection circuit (112, 1 for detecting the amplitude of the output signal of the
13, 114; 214) and the amplitude detection circuit (11
2, 113, 114; 214), the difference between the detected amplitude and the target amplitude is detected, and the amplification degree of the amplifier circuit is controlled according to the detected difference so that the amplitude of the output signal becomes the target amplitude. And an amplification degree control circuit (115; 22) for controlling.

Further, in a fourth aspect of the present invention, a disk device (10
0; 200), the amplitude detection circuit (112, 1)
13, 114; 214), the amplification unit (111; 21)
2) a peak value detection circuit (112; 214) for detecting the peak value of the output signal, and the amplification section (111; 212)
Value detection circuit (1
13; 214) are provided.

Further, a fifth aspect of the present invention is a disk device (10
0; 200) constituting the amplification degree control circuit (115;
22) is realized by firmware that controls the operation of the device.

According to the present invention, the amplitude of the output signal of the amplification section is detected, the difference between the detected amplitude and the target amplitude is detected, and the amplitude of the output signal becomes the target amplitude according to the detected difference. By controlling the amplification degree of the amplification section, it is possible to adjust the amplitude to the optimum level for the decoder input without the occurrence of clipping during analog signal processing.

[0023]

1 is a block diagram of the first embodiment of the present invention. 10, those parts which are the same as those corresponding parts in FIG. 10 are designated by the same reference numerals, and a description thereof will be omitted.

The disk device 100 of this embodiment is different from that of FIG. 10 in the structure of the high frequency amplifier 101.

FIG. 2 is a block diagram of the high frequency amplifier according to the first embodiment of the present invention.

The high frequency amplifier 101 of this embodiment is a VCA.
(Voltage controlled amplifier) circuit 111, peak detection circuit 112, bottom detection circuit 113, differential amplifier 1
It is configured to include 14, 115.

The VCA circuit 111 includes a pickup 15
From which a detection signal is supplied. The VCA circuit 111 amplifies and outputs the detection signal with an amplification degree according to the output of the differential amplifier circuit 115. The output signal of the VCA circuit 111 is supplied to the decoder 43 and the peak detection circuit 112 and the bottom detection circuit 103.

The peak detection circuit 112 includes a diode D1.
And a capacitor C1. Diode D1
Has an anode connected to the output of the VCA circuit 111 and a cathode connected to one end of the capacitor C1. The reference voltage Vss is applied to the other end of the capacitor C1. When the output of the VCA circuit 111 is smaller than the peak value, the diode D1 is turned off because the cathode potential becomes higher due to the peak value voltage charged in the capacitor C1. When the diode D1 is turned off, the peak value voltage charged in the capacitor C1 is output.

The bottom detection circuit 113 includes a diode D2
And a capacitor C2. Diode D2
Has a cathode connected to the output of the VCA circuit 111 and an anode connected to one end of the capacitor C2. The reference voltage Vss is applied to the other end of the capacitor C2. When the output of the VCA circuit 111 is smaller than the peak value, the diode D2 is turned off because the cathode potential becomes higher due to the peak value voltage charged in the capacitor C2. When the diode D2 is turned off, the peak value voltage charged in the capacitor C2 is output.

The charging voltage of the capacitor C1 of the peak detection circuit 112, that is, the peak value is applied to the non-inverting input terminal of the differential circuit 114, and the charging voltage of the capacitor C2 of the bottom detection circuit 113, that is, the bottom value is the difference. It is applied to the inverting input terminal of the driving circuit 114. Differential circuit 114
Outputs a voltage corresponding to the difference between the charging voltage of the capacitor C1 of the peak detection circuit 112 and the charging voltage of the capacitor C2 of the bottom detection circuit 113. The output of the differential circuit 114 is applied to the inverting input terminal of the differential circuit 115.

In the differential circuit 115, a voltage corresponding to the target value, that is, the target amplitude value is applied to the non-inverting input terminal, and the output of the differential circuit 114, that is, the difference from the actual amplitude value. Output voltage. The differential circuit 1
The target value supplied to 15 is supplied from the CPU 22. Therefore, the type of the disk 10 is detected, and the target value is changed according to the type of the disk 10.

The output of the differential circuit 115 is the VCA circuit 11
1 is supplied. The VCA circuit 111 has a differential circuit 115.
The detection signal from the pickup 15 is amplified with an amplification degree according to the voltage from.

As described above, according to the high frequency amplifier 101 of this embodiment, since the amplitude of the detection signal can be controlled to the target value, when the detection signal is supplied to the decoder 43, the decoder 43 may clip it. Therefore, the decoding operation can be performed accurately.

Although the amplitude control is performed by analog control in this embodiment, FIG. 3 shows a block diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The disk device 200 of this embodiment differs from the disk device 1 shown in FIG. 1 in the configuration of the high-frequency amplifier 201 and the operation of the CPU 23.

FIG. 4 shows a block diagram of a high frequency amplifier according to the second embodiment of the present invention.

The high frequency amplifier 201 of this embodiment is composed of a buffer amplifier 211, a VCA circuit 212 and a filter circuit 21.
3. The peak hold circuit 214 is included.

The VCA circuit 212 includes a pickup 15
The reproduction signal is supplied from. The VCA circuit 212 has a CP
The detection signal is amplified with an amplification degree according to the set value from U23. The detection signal amplified by the VCA circuit 212 is supplied to the decoder 43 and the peak hold circuit 214. The filter circuit 213 is composed of a capacitor C11 and a resistor R11, and passes a signal with a DC component cut.

The detection signal passed through the filter circuit 213 is supplied to the peak hold circuit 214. The peak hold circuit 214 detects the peak value and the bottom value of the detection signal and supplies them to the CPU 23.

The CPU 23 has a peak hold circuit 214.
VCA based on peak and bottom values supplied by
A process of determining the amplification degree of the circuit 212 is performed.

FIG. 5 is a flowchart of the gain adjusting process of the CPU according to the second embodiment of the present invention.

When a play or write operation command is issued, a start-up routine is executed in step S1-1. The startup routine is focus control,
This is a process for turning on various servo processes such as tracking control, determining the type of the disk 10, executing offset process for error signals, and executing calibration process for determining the recording level.

After the startup routine is executed in step S1-1, a jump operation to a desired position is performed in step S1-2. Next, in step S1-3, the presence or absence of a high frequency signal is determined.

If the high frequency signal is present in step S1-3, the gain adjusting process is started in step S1-4. When the gain adjustment process starts, step S
In 1-5, the peak value and the bottom value of the high frequency signal are acquired from the peak hold circuit 214, and the amplitude of the high frequency signal is detected.

Next, in step S1-5, it is determined whether the amplitude of the high frequency signal is larger than a preset target value. If the amplitude of the high frequency signal is smaller than the target value in step S1-5, the gain of the VCA circuit 111 is set to 1
The level is increased, and the process returns to step S1-5.

Next, when the amplitude of the high frequency signal is larger than the target value in step S1-6, step S1-8
Then, the VCA circuit 212 is controlled so that the gain closer to the target value between the amplitude of the high frequency signal at the previous gain and the amplitude of the high frequency signal at the current gain becomes the optimum gain. In step S1-9, the gain adjustment processing is completed, and in step S1-10, the operation is instructed to read, play, or write. According to this embodiment, the gain of the VCA circuit 212 can be set to the optimum gain. That is, the amplitude of the output signal of the VCA circuit 212 is determined by the decoder 4
It can be set to the maximum value that can be decoded without being clipped at 3. Therefore, the decoding operation of the decoder 43 can be reliably performed.

6 and 7 are views for explaining the effect of the second embodiment of the present invention. 6A is a land jitter characteristic with respect to β value, FIG. 6B is a pit jitter characteristic with respect to β value, and FIG. 6C is an error rate C with respect to β value.
The characteristics of No. 1 are shown. In FIG. 6, ● indicates characteristics when the gain adjustment processing shown in FIG. 5 is executed, and ■ indicates characteristics when the gain adjustment processing shown in FIG. 5 is not executed. FIG. 7A shows the error rate, β value, land jitter, and pit jitter when the gain adjustment process is executed, and FIG. 7B shows the error rate, β value, land jitter, and pit jitter when the gain adjustment process is executed. Numerical examples are shown.

As shown in FIGS. 6A and 7, it can be seen that the land jitter is smaller when the gain adjustment processing is executed than when the gain adjustment processing is not executed. Further, as shown in FIGS. 6B and 7, it can be seen that the pit jitter is smaller when the gain adjustment processing is executed than when the gain adjustment processing is not executed. Further, as shown in FIGS. 6C and 7, it can be seen that the error rate C1 is smaller when the gain adjustment processing is executed than when the gain adjustment processing is not executed.

As described above, it is understood that good decoding can be performed by performing the gain adjustment processing.

In this embodiment, the gain adjustment process is performed when the operation is instructed. However, the gain adjustment process may be performed for each tune during reproduction.

FIG. 8 shows a flow chart of a modification of the gain adjusting process of the second embodiment of the present invention.

When there is a play command, a start-up routine is executed in step S2-1. The start-up routine turns on various servo processes such as focus control and tracking control as in step S1-1, and also determines the type of the disk 10, the offset cancellation of the error signal, and the calibration for determining the recording level. It is a process for executing a process.

Next, in step S2-2, the TOC (table of
contents) It is determined whether the information has been acquired. If the TOC information has already been acquired in step S2-2, based on the already acquired TOC information,
If the TOC information has not been acquired in 2-2, the TOC information is acquired in step S2-3, and then the process jumps to the desired reproduction position in step S2-4 based on the TOC information.

Next, in step S2-5, reproduction is performed. When the stop command is issued in step S2-6, the reproduction is stopped. Further, if the stop command is not issued in step S2-6, it is determined in step S2-7 whether or not it is between songs. If it is not between the songs in step S2-7, the process returns to step S2-5 to continue the reproduction. If it is between songs in step S2-7, after the gain adjustment processing of steps S1-4 to S1-9 is executed in step S2-8,
Returning to step S2-5, the reproduction is continued.

According to this modification, since the gain adjustment process is performed for each tune, the gain can be finely adjusted. Therefore, even if the amplitude of the detection signal changes between the inner circumference and the outer circumference due to factors such as the in-plane distribution characteristics of the disk 10 and the drive skew, the gain can be adjusted so that the optimum amplitude is obtained.

In this modification, the gain adjustment process is performed for each song, but it may be performed at any time during reproduction.

FIG. 9 shows a flowchart of another modification of the gain adjusting process of the CPU according to the second embodiment of the present invention.

When there is a play command, a start-up routine is executed in step S3-1. The startup routine turns on various servo processes such as focus control and tracking control as in steps S1-1 and S2-1, determines the type of the disk 10, and
This is processing for executing offset processing of an error signal and calibration processing for determining a recording level.

Next, at step S3-2, TOC (table of
contents) It is determined whether the information has been acquired. If the TOC information has already been acquired in step S3-2, based on the already acquired TOC information,
If the TOC information is not acquired in 3-2, the TOC information is acquired in step S3-3, and then the jump to the desired reproduction position is performed in step S3-4 based on the TOC information.

Next, reproduction is performed in step S3-5. When the stop command is issued in step S3-6, the reproduction is stopped. If the stop command is not issued in step S3-6, step S3-7 is performed.
After the gain adjustment processing of 1-4 to S1-9 is executed, the process returns to step S2-5 and the reproduction is continued.

According to this modification, since the gain adjustment process is performed as needed, the gain can be finely adjusted. Therefore, even if the amplitude of the detection signal changes between the inner circumference and the outer circumference due to factors such as the in-plane distribution characteristics of the disk 10 and the drive skew, the gain can be adjusted so that the optimum amplitude is obtained.

[0062]

As described above, according to the present invention, the amplitude of the output signal of the amplifier is detected, the difference between the detected amplitude and the target amplitude is detected, and the amplitude of the output signal is detected according to the detected difference. By controlling the amplification degree of the amplifier so that the amplitude becomes the target amplitude, the amplitude can be adjusted to the optimum amplitude for the decoder input without the occurrence of clipping during analog signal processing, so the signal is clipped during decoding. Since it does not occur, it has a feature that the error rate can be reduced.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a first embodiment of the present invention.

FIG. 2 is a block configuration diagram of a high-frequency amplifier according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block configuration diagram of a high frequency amplifier according to a second embodiment of the present invention.

FIG. 5 is a flowchart of a gain adjustment process of the CPU according to the second embodiment of the present invention.

FIG. 6 is a diagram for explaining the effect of the second embodiment of the present invention.

FIG. 7 is a diagram for explaining the effect of the second embodiment of the present invention.

FIG. 8 is a flowchart of a modified example of the gain adjustment processing of the CPU according to the second embodiment of the present invention.

FIG. 9 is a flowchart of another modification of the gain adjustment processing of the CPU according to the second embodiment of the present invention.

FIG. 10 is a block diagram of an example of a conventional disk device.

[Explanation of symbols]

100,200 disk drive 10 discs 11 trays 14 Spindle motor 15 pickups 16 thread motor 20 Analog signal processor 21 Digital signal processor 22 CPU 23 ROM 43 decoder 101, 201 high frequency amplifier 111 VCA circuit 112 Peak detection circuit 113 Bottom detection circuit 114, 115 differential circuit

Claims (5)

[Claims] 1. An amplification unit for amplifying an input signal with a variable amplification degree, an amplitude detection circuit for detecting an amplitude of an output signal of the amplification unit, and an amplitude detected by the amplitude detection circuit and a target amplitude. An amplification circuit, comprising: an amplification degree control circuit that detects a difference and controls the amplification degree of the amplification section so that the amplitude of the output signal becomes the target amplitude according to the detected difference. 2. The amplitude detection circuit includes a peak value detection circuit that detects a peak value of an output signal of the amplification section, a bottom value detection circuit that detects a bottom value of the output signal of the amplification section, and the peak value. The amplifier circuit according to claim 1, further comprising a differential circuit that detects a difference between a peak value detected by the detection circuit and a bottom value detected by the bottom value detection circuit. 3. A disc device comprising: a detection unit for detecting a detection signal from the disc; and a decoder for decoding data recorded on the disc based on the detection signal detected by the detection unit. And an amplitude detection circuit that detects the amplitude of the output signal of the amplification unit, and a difference between the amplitude detected by the amplitude detection circuit and the target amplitude, And a gain control circuit that controls the gain of the amplifier so that the amplitude of the output signal becomes the target amplitude according to the difference. 4. The amplitude detection circuit, a peak value detection circuit for detecting a peak value of the output signal of the amplification section, a bottom value detection circuit for detecting a bottom value of the output signal of the amplification section, the peak value 4. The disk device according to claim 3, further comprising a differential circuit that detects a difference between the peak value detected by the detection circuit and the bottom value detected by the bottom value detection circuit. 5. The disk device according to claim 3, wherein the amplification degree control circuit is realized by firmware that controls the operation of the device.