JP2006197375A - Method for receiving and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cope with synchronization signals of a plurality of patterns by simple constitution. <P>SOLUTION: When one unit of synchronization signals are transmitted repeatedly for a prescribed period as already known synchronization signals to be received and patterns of a transmission frequency to be set by each unit and patterns of a signal polarity to be set by each unit exist plurally, received signals are delayed by a plurality of stages in a period of one unit, and a plurality of received signals at two or more delay positions are taken out by different combinations from the received signals delayed by the plurality of stages. Then, from the received signals of the plurality of combinations, received signals at two or more delay positions of the combination selected according to a synchronization signal patterns to be received is selected by a selector 133, and correlation detection is carried out from each selected received signal. Then, a running average is obtained from a signal obtained by complex multiplication of each correlation detection signal, and synchronization signal detection is carried out. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reception method for performing processing for establishing synchronization when receiving data in a wireless or wired digital communication system and a receiver to which the reception method is applied, and in particular, detection of synchronization timing using preamble correlation. It is related with the technique to perform.

  In digital communication, in order to perform demodulation by a receiving circuit, it is necessary to first establish synchronization of received signals. FIG. 9 shows a configuration example of a conventional synchronization circuit. Here, it is assumed that a preamble signal including a synchronization signal used for detection of synchronization timing or the like is incorporated in the transmission signal.

  First, the received signal in the RF frequency band received by the antenna 1 is frequency-converted by the frequency converter 2 into a received baseband signal in the baseband by using the carrier signal generated by the carrier signal generator 3. Next, the reception baseband signal is adjusted to a reception signal of a predetermined level by an AGC (automatic gain control) circuit 4 and then sampled and converted into a digital signal by an A / D converter 5.

  The converted digital reception signal is sent to the correlator 6 to correlate the reception baseband digital signal with a known preamble code and output a correlation value. Since this correlation value is generally a complex number, the absolute value square calculator 8 obtains the absolute value square and outputs it to the local maximum value detection circuit 9. The maximum value detector 8 outputs the maximum of the correlation value or the timing exceeding a predetermined threshold as the synchronization timing.

  Although the synchronization detection configuration shown in FIG. 9 is a general reception configuration, in recent years, there are signals having a relatively complicated synchronization signal pattern as signals transmitted wirelessly, and a configuration for detecting a synchronization signal is present. It can be very complex.

  That is, for example, in recent years, a method called “ultra-wide band (UWB) communication” for performing wireless communication by placing information on a very weak impulse train has attracted attention as a wireless communication system that realizes short-range ultrahigh-speed transmission. Practical use is expected. Currently, in the IEEE802.15.3 standard and the like, a data transmission system having a packet structure including a preamble is proposed as an access control system for such ultra-wideband communication.

  In general, when a wireless network is constructed indoors, a multipath environment in which a reception device receives a superposition of a direct wave and a plurality of reflected waves / delayed waves is formed, and intersymbol interference occurs due to delay distortion. For this reason, a multicarrier transmission scheme represented by an OFDM (Orthogonal Frequency Division Multiplexing) scheme is applied.

  For example, in the IEEE 802.15.3 standard, the standardization of the UWB communication system adopting the OFDM modulation system is underway. In the case of the OFDM_UWB communication system, three subbands each having a frequency of 3.1 to 4.8 GHz are frequency hopped (FH) each having a width of 528 MHz, and OFDM modulation using IFFT / FFT in which each frequency band is composed of 128 points. Is being considered.

Japanese Patent Application Laid-Open No. 2004-228561 discloses an example in which synchronization detection is performed from this type of signal.
Japanese Patent Laid-Open No. 11-215097

  The OFDM system that performs frequency hopping, as in the communication system defined by the IEEE 802.15.3 standard, is usually called a Multi-Band OFDM (MB-OFDM) system. In this system, preamble transmission, which is a signal for acquiring synchronization, is used. In addition, hopping is performed, and the hopping pattern and data transmission pattern (hereinafter referred to as Time Frequency Code; hereinafter referred to as TFC) are defined to have various types.

  That is, for example, as shown in FIG. 10, seven patterns from TFC1 to TFC7 are defined, and a preamble signal which is a synchronization signal is transmitted in any of the seven patterns. Specifically, three frequencies f1, f2, and f3 are prepared as frequencies to be transmitted, and one unit of preamble signal (synchronization signal) is used by using any one of the three frequencies f1, f2, and f3. Are repeatedly sent 24 times (24 slots). In FIG. 10, only 12 periods are shown.

  Each pattern will be described. In the TFC1 pattern, as shown in FIG. 10A, the frequency f1, f2, and f3 are changed in order for each unit of preamble signal (synchronization signal). In the TFC2 pattern, as shown in FIG. 10B, the frequency f1, f3, and f2 are changed in order for each preamble signal in one slot. In the TFC3 pattern, as shown in FIG. 10C, the frequency is changed in the order of the frequencies f1, f2, and f3 for each 2-slot preamble signal. In the TFC4 pattern, as shown in FIG. 10D, the frequency is changed in the order of the frequencies f1, f3, and f2 for each 2-slot preamble signal. In the TFC5 pattern, the preamble signals of all slots are transmitted at the frequency f1, as shown in FIG. 10 (e). In the TFC6 pattern, the preamble signals of all slots are transmitted as shown in FIG. 10 (f). In the TFC7 pattern, as shown in FIG. 10G, the preamble signals of all slots are transmitted at the frequency f3. Although not shown here (see Table 2 described in the embodiment described later), the signal polarity (+ or-) of the preamble signal is also set to a specific pattern.

  In order to receive and detect a synchronization signal having such a TFC pattern, there is a problem that a very complicated synchronization detection circuit is required. FIG. 11 is a diagram showing a conventional reception configuration example corresponding to the seven types of preamble signals TFC1 to TFC7 shown in FIG. FIG. 11 shows a synchronization detection configuration after the A / D converter 5 shown in FIG. 10, and the digital signal obtained at the terminal 10a is sent to the reception energy and moving average detection unit 10 and a plurality of correlations. The data is sent to devices 31, 32, 33, 34, 35, and 36. Each of the correlators 31 to 36 is a circuit that correlates a received signal with a known preamble signal pattern.

  Here, the signal obtained at the terminal 10a is directly sent to the correlator 31, and the signal obtained at the terminal 10a is supplied to the correlator 32 after being delayed by the shift register 21. The shift register 21 is a delay circuit that delays a signal for a period of three slots of the preamble signal (one slot of the preamble signal here is 165 clock cycles).

  When the signals are supplied to the correlators 31 and 32 in this way, for example, if the reception frequency is fixed at any one of the frequencies f1 to f3 (FIG. 10), the two correlators 31 and 32 have 3 slots. Correlation is detected by the difference, and when the correlation with the preamble signal is detected simultaneously every three slots, the synchronization signal having the TFC1 or TFC2 pattern is detected. The detection outputs of both correlators 31 and 32 are complex-multiplied by a complex multiplier 41 to become a correlation detection signal in which a TFC1 or TFC2 pattern is detected.

  Further, the signal obtained at the terminal 10 a is directly sent to the correlator 33, and the signal obtained at the terminal 10 a is delayed by the shift register 22 and supplied to the correlator 34. The shift register 22 is a delay circuit that delays the signal for one slot period of the preamble signal.

  When signals are supplied to the correlators 33 and 34 in this way, for example, if the reception frequency is fixed at one of the frequencies f1 to f3 (FIG. 10), the two correlators 33 and 34 have one slot. Correlation is detected by the difference, and when the correlation with the preamble signal is detected at every 6 slots at the same time, the synchronization signal of the TFC3 or TFC4 pattern is detected. The detection outputs of both correlators 33 and 34 are complex-multiplied by a complex multiplier 42 to become a correlation detection signal in which a TFC3 or TFC4 pattern is detected.

  Further, the correlator 35 is supplied with a signal obtained by adding the signal obtained at the terminal 10a and the signal delayed by the shift register 23 for two slots by the adder 26. The correlator 36 is supplied with the signal obtained by adding the signal obtained by delaying the signal obtained at the terminal 10 a by the shift register 23 for one slot period and the signal delayed by the shift register 23 for three slot periods by the adder 27.

  By supplying the signals to the correlators 35 and 36 in this way, for example, assuming that the reception frequency matches the transmission frequency of the preamble signal, the correlator 35 detects the correlation from the added signals of the first slot and the third slot. In the correlator 36, the correlation is detected from the addition signal of the second slot and the fourth slot, and when the correlation with the preamble signal is detected in each, the pattern of any one of TFC5, TFC6, and TFC7 is detected. A synchronization signal is detected. The detection outputs of both the correlators 35 and 36 are complex-multiplied by the complex multiplier 43 to become a correlation detection signal in which any pattern of TFC5, TFC6, and TFC7 is detected.

The correlators 31 and 32, 33 and 34, and 35 and 36 that are paired with each other output correlation values of signals that have undergone a predetermined time shift.
Here, the signal polarity pattern of the preamble signal is not specifically described (described in detail in an embodiment described later), but the polarity of the preamble signal is inverted only in a specific slot position among the 24 slots to be transmitted. Therefore, the result of complex multiplication of the paired correlator outputs becomes a maximum value (or minimum value) only at that position, so that synchronization can be detected.

  The outputs of the complex multipliers 41, 42 and 43 are supplied to the selector 44, and a system corresponding to the preamble signal pattern received at that time is selected. The signal selected by the selector 44 is sent to the moving average detection unit 50 to detect the moving average. Specifically, the subtractor 52 detects the difference between the input signal delayed by the shift register 51 and the non-delayed signal, and supplies the output of the subtractor 52 to the adder 53 for addition. The output of the unit 53 is added to the signal delayed by one clock period by the delay circuit 4, and the added output is used as a moving average signal.

  The moving average signal detected by the moving average detector 50 is supplied to the divider 61 and divided by the average value of the received energy and the received energy output by the moving average detector 10 to make the signal level a certain range. Normalization is performed, and the output of the divider 61 is supplied to the synchronization detector 62 to perform synchronization detection processing for determining the synchronization detection timing.

  In the reception energy and moving average detection unit 10, the absolute value square calculator 12 calculates the absolute value square of the signal obtained by delaying the input signal by the shift register 11 for 6 slots, and the input signal is directly converted to the absolute value 2 The absolute value is squared by supplying to the multiplier 13 and the difference between the two signals is obtained by the subtractor 14 to obtain received energy. The obtained reception energy value is supplied to the adder 15, and the output of the adder 15 is added to a signal that is delayed by one clock period in the delay circuit 16, and the addition output is the moving average signal and the received energy. The moving average is supplied to the divider 61.

  Synchronization detection is performed in this way, but for each received preamble signal pattern, an individual correlation detector and complex multiplier and a shift register connected to each correlation detector are required, and the circuit configuration is very high. It becomes complicated. That is, when receiving a preamble signal transmitted with various hopping patterns and data transmission patterns with a single receiver, naturally it is difficult to acquire synchronization with one synchronization acquisition algorithm, and it is necessary to have multiple algorithms. Therefore, the configuration becomes very complicated as shown in FIG. After all, the synchronization detection unit of the receiver becomes complicated, the digital circuit becomes large, and it is inevitable that it is disadvantageous in terms of portability and cost.

  The present invention has been made in view of this point, and an object thereof is to be able to cope with a plurality of patterns of synchronization signals with a simple configuration.

  In the present invention, as a known synchronization signal to be received, one unit of the synchronization signal is repeatedly transmitted for a predetermined period, and a transmission frequency pattern set for each unit and a signal polarity pattern set for each unit are When there are a plurality of received signals, the received signals are delayed by a plurality of stages in one unit cycle, and a plurality of received signals at at least two delay positions are extracted from the received signals delayed by the plurality of stages in different combinations, and the received signals of the combinations are combined. Select a received signal of at least two delay positions in a combination selected according to the received synchronization signal pattern, perform correlation detection from each selected received signal, and perform complex multiplication on each correlation detection signal The moving average is obtained from the obtained signal and the synchronization signal is detected.

  In this way, since the selection process corresponding to the synchronization signal pattern is performed at the input stage of the correlation detection means, the correlation detection can be performed for any pattern of synchronization signals by one set of correlation detection means. .

  According to the present invention, a single set of correlation detection means can detect correlation of any pattern with excellent characteristics, and simplify the configuration for synchronization detection corresponding to a large number of synchronization signal patterns. Can do. For example, it can be applied to communication systems having various TFC patterns in the MB-OFDM specification.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

  In this example, the present invention is applied to a receiver that receives a wireless transmission signal of the MB-OFDM system defined by the IEEE 802.15.3 standard. First, a preamble signal pattern that is a synchronization signal of a signal received in this example will be described. The preamble signal pattern has seven patterns TFC1 to TFC7 as already described with reference to FIG. The frequency changes of the seven patterns TFC1 to TFC7 shown in FIG.

  In the case of this example, one unit (one slot) preamble signal is configured to be transmitted continuously for 24 slots (24 cycles). The polarity of the preamble signal in each slot is shown in Table 2 below. Are classified into the following three patterns (sequence numbers 1 to 3). The slot shown as -1 in Table 2 has a negative polarity. The state where the polarity is negative here is a state where all the codes are inverted with respect to the code sequence with a positive polarity.

  As can be seen from Table 2, regardless of the pattern, the polarity of the preamble signal is reversed in the vicinity of the last slot period of the 24 slot period. Detection is performed. In the case of this example, it is assumed that when performing reception processing, it is known in advance which pattern the preamble signal is received.

  FIG. 1 shows the configuration until the synchronization detection of the receiver of this example. In the following, the configuration will be described with reference to FIG. 1. The received signal in the RF frequency band received by the antenna 101 is received by the frequency converter 102 using the carrier signal generated by the carrier signal generator 103. The frequency is converted into a band signal. Next, the reception baseband signal is adjusted to a reception signal of a predetermined level by an AGC (automatic gain control) circuit 104, and then sampled and converted into a digital signal by an A / D converter 105.

  The converted digital received signal is delayed by shift registers 106, 107, 108 connected in series in a plurality of stages. Each shift register 106, 107, 108 functions as a delay circuit that delays one slot period (ie, 165 clock periods) of the received preamble signal.

  The output of the shift register 108 is supplied to the reception energy and moving average detection unit 120. In the received energy and moving average detection unit 120, the supplied delay signal is further delayed by the shift register 121, and then the absolute value square calculator 122 calculates the absolute value square, and the A / D converter 105 The output is directly supplied to the absolute value square calculator 124 to calculate the absolute value square, and the moving average is detected by the moving average detection unit 123 from both signals, and the moving average of the received energy (received power) that has been detected is detected. The value is supplied to a divider 137 described later.

  In this example, the output of the A / D converter 105 and the output of the shift register 108 are supplied to the selector 133 as a first set, and the output of the A / D converter 105 and the output of the shift register 106 are supplied. The second set is supplied to the selector 133. Further, the output of the A / D converter 105 and the output of the shift register 107 are added by the adder 131, and the output of the shift register 106 and the output of the shift register 108 are added by the adder 132, whereby both adders are added. The added outputs 131 and 132 are supplied to the selector 133 as a third set.

  In the selector 133, one of the first set to the third set is selected according to the preamble pattern received by the receiver. Then, one of the two signals in the selected set is supplied to the correlator 134, and a correlation with a known preamble signal pattern is detected. The other of the two signals in the selected set is supplied to the correlator 135 to detect a correlation with a known preamble signal pattern.

  The outputs of the two correlators 134 and 135 are supplied to the complex multiplier 136 and complex-multiplied, and the complex-multiplied signal is supplied to the moving average detector 140 to detect the moving average of the correlation detection signal. The detected moving average signal is supplied to the divider 137, and is divided by the average value of the received energy and the received energy output from the moving average detector 120 to normalize the signal level within a certain range. Then, the output of the divider 137 is supplied to the synchronization detector 138, and the synchronization detection process for determining the synchronization detection timing is performed.

  Next, a more detailed synchronization detection configuration around the correlators 134 and 135 is shown in FIG. Referring to FIG. 2, the configuration of the reception energy and moving average detection unit 120 will be described first. In the shift register 121, a process of delaying the preamble signal by 3 slots (that is, delaying 495 clock periods) is performed. The two absolute value square calculators 122 and 124 calculate signals having different timings in the 6 slot period. The difference between the arithmetic outputs of the absolute value square calculators 122 and 124 is detected by the subtractor 125, and the output is supplied to the adder 126. The output of the adder 126 is delayed by one clock period by the delay circuit 127. The signal is added to the signal, and the addition output is used as a moving average signal and supplied to the divider 137.

  As shown in FIG. 2, there are three combinations of the first set a, the second set b, and the third set c already described in FIG. One set is selected by the selector 133 in accordance with the preamble signal pattern to be performed. Here, as shown in detail in FIG. 3, the first set a is selected when the received preamble signal pattern is TFC1 or TFC2, and the second set when the received preamble signal pattern is TFC3 or TFC4. The set b is selected, and when the preamble signal pattern to be received is any one of TFC5 to TFC7, the third set c is selected and the received signals are supplied to the two correlators 134 and 135.

  For example, as shown in FIG. 7, the correlation detection signals of the two correlators 134 and 135 have a maximum value when the preamble signal is detected. Returning to the description of FIG. 2, the correlation detection values of the two correlators 134 and 135 are complex-conjugated by the complex multiplier 136 after taking one of the complex conjugates. By performing complex multiplication in this way, polarity inversion can be detected. Then, the complex multiplication output is supplied to the moving average detection unit 140 to detect the moving average of the correlation detection signal. As a configuration for detecting the moving average, a subtractor 142 detects a difference between a signal delayed by the shift register 141 and a signal not delayed by the shift register 141, and supplies the output of the subtractor 142 to the adder 143. Then, the output of the adder 143 is added to the signal delayed by one clock period by the delay circuit 144, and the added output is used as a moving average signal. Here, the shift register 141 is delayed for 32 clock periods.

  The moving average signal detected by the moving average detector 137 is supplied to the divider 137 and divided by the received energy and the average value of the received energy output by the moving average detector 120.

  By performing the moving average process in this way, it is possible to reduce the influence of delay wave superposition due to multipath. In other words, if a delayed wave is superimposed on the data, the maximum value of the correlator output is not a single peak, but a plurality of peaks are generated, and the heights of the peaks also vary, making synchronization determination very difficult. . By performing the moving average process, a plurality of local maximum values can be bundled into one mountain, and variations in the height can be suppressed to be small, so that stable synchronization can be obtained. Here, the order of the moving average should be optimized from the order of the multipath, the usage environment, and the device cost, and cannot be determined uniquely, but the example of FIG. 2 shows a preferred example.

  The received energy and moving average detector 120 calculates the average power of the observed data series. The absolute value square of the data series is used as an input, and the moving average is calculated in an appropriate section. The average power is measured. For example, in the example of FIG. 2, a moving average of 6 slots (990 clock intervals) is performed. This is determined from various data observation patterns of the received preamble signal pattern. Of course, this section should be optimized from the usage environment and the cost of the apparatus, and is not limited to the configuration shown in FIG.

  In this way, by normalizing (dividing) the moving averaged data from the complex multiplier 136 with the average power, it is possible to perform synchronization determination and acquire synchronization by using the normalized data. Become.

  Here, taking as an example the case where the received preamble signal pattern is TFC1 or TFC2, FIG. 8 shows a detailed description of data calculated by the processing of each unit. In this case, as shown in FIGS. 8A and 8B, signal data without time delay and signal data delayed by three slots are input to the correlators 134 and 135, respectively. As a result, each correlator output has a sharp peak as shown in FIGS. 8 (c) and 8 (d). The peak shown in FIG. 8 also represents a delayed wave in consideration of multipath. The result obtained by performing complex multiplication by taking one of these outputs as a complex conjugate is the waveform shown in FIG. As shown in FIG. 8E, this output has many peaks due to multipath. This mountain group is averaged by moving average processing, and becomes a single peak as shown in FIG. After that, this data is normalized (divided) by the average power, and it is possible to obtain synchronization by making the synchronization determination using the normalized data.

Next, the synchronization determination process in this example will be described with reference to the flowchart of FIG. This synchronization determination algorithm has a two-stage configuration of a maximum value detection unit and a threshold comparison unit.
First, the buffer data and the initial value of the counter are set to zero. New data is acquired (step S11). The acquired data is compared with the data in the buffer (step S12), and if it is larger than the data stored in the buffer, it is replaced with the data in the buffer (step S13). If the data in the buffer does not change more than the predetermined number of times (MaxCount) with respect to the new data, it is recognized as the maximum value and enters the next threshold comparison (steps S14 and S15). In other words, if a maximum value is not observed in 32 sections after the data, it is recognized as a maximum value. If it is recognized as a local maximum, it becomes a candidate for synchronization.

  Next, it is determined whether or not the data recognized as the maximum value is synchronized (step S16). This determination is made based on whether or not it is larger than a predetermined threshold value. If it is larger than the threshold value, it is determined that the synchronization is made, and if not, the synchronization is not determined and the operation is continued. Return to the top-level flow and resume from acquiring new data.

  In this case, since it was recognized as a local maximum, it was not synchronized, so it is clear that even if a local maximum is recognized with a value smaller than this local maximum in future data, it is clear that it is not synchronized. It is necessary to exceed this maximum value. Therefore, the counter is reset, but the buffer data is not reset.

  In addition, in the algorithm shown in the flowchart of FIG. 4, there is a possibility that synchronization is detected a plurality of times. However, since how to use the synchronization depends on design, it will not be described in detail here. Only need to be synchronized.

  Next, the process of synchronous detection in this way will be described in detail for each preamble pattern with reference to FIG. 5 and FIG.

  First, the process for acquiring the synchronization of the TFC1 and TFC2 patterns will be described with reference to FIG. In the case of these two patterns, the receiver receives data at a rate of once every three slots when receiving continuously at one specific frequency. As can be seen from Table 2, since only the last received data has a negative polarity and all other data have a positive polarity, synchronization is achieved by utilizing this change of positive to negative. That is, the result of correlation detection of the data of the two slots indicated by the last diagonal line in FIG. 5A is subjected to complex multiplication, and synchronization detection is performed from the complex multiplied value.

  Since the data received in this way is preamble data, a maximum value appears due to the correlation when passed through the correlator. FIG. 7 shows an example of an actual correlator output. Therefore, in this type, the maximum value appears once every three slots. Since only the last data has a negative polarity, only the slot of this portion has a negative maximum value.

  In order to detect a portion where positive changes to negative, for example, multiplication may be performed. Multiplication is positive by multiplying positive and positive by nature, but becomes negative by multiplying positive and negative, so if you multiply yourself and the correlator output one slot before, only the last result is negative. It becomes possible to detect the portion where the positive value changes to negative. The actual received data is a complex number, but mathematically it can be detected in the same way by replacing the multiplication with a complex multiplication. In this way, if the place where the output is negative is detected and the synchronization determination is made, the synchronization of the TFC1 and TFC2 patterns can be acquired.

  Next, a process for acquiring the synchronization of the TFC3 and TFC4 patterns will be described with reference to FIG. Also in the case of these two patterns, synchronization can be obtained by the same processing as the above-described TFC1 and TFC2 patterns. That is, as shown in FIG. 5B, data is observed by repeating a pattern in which data is obtained continuously for two slots and then there is no 4-slot data. The data ends when the polarity of the data behind the last two observation data is inverted.

  Also in this case, first, a maximum value is obtained through a correlator, and then complex multiplication is performed. However, since the difference from the previous TFC1 and TFC2 is continuous when data comes, complex multiplication must be performed on data at a certain time and data one slot before. By doing so, it is possible to obtain the same synchronization as in the case of the TFC 1 and 2 patterns.

  Next, a process for acquiring the synchronization of the TFC5, TFC6, and TFC7 patterns will be described with reference to FIG. In this case as well, the basic idea is the same as in the other two cases. However, since the polarity inversion of the received data has occurred even in the middle, some contrivance is required. In this example, every other data is extracted from every other 4 slots, summed (added), and the result of the sum is complex multiplied (signal set c in FIGS. 2 and 3). . Thereby, the influence of polarity reversal that occurs in the middle can be eliminated, and a negative maximum value can be obtained correctly.

  FIG. 6 shows details when the synchronization of the patterns of TFC5, TFC6, and TFC7 is acquired. In the case of TFC5, TFC6, and TFC7 patterns, all the observed patterns are classified into four from timing a to timing d in FIG. For example, at timing a, complex multiplication is performed by taking the sum of odd-numbered slots and even-numbered slots. However, since the odd-numbered slots have different polarities, the sum is zeroed. On the other hand, the sum of the even numbers is a negative value, but if it is multiplied by 0, the result is 0. In this type of timing a, only an output of 0 is output.

  Next, in the case of the timing b type, the sum of the even-numbered units is now 0, so that the multiplication result is 0. In this timing b type, only 0 output is output. In addition, in the case of the timing c type, the sum of both odd-numbered and even-numbered ones is 0, so that the multiplication result is naturally 0. In this type of timing c, only 0 output is output. . Therefore, in the three timings a to c, the output becomes 0 even though the polarity inversion occurs, so that the synchronization detection is not performed in this portion, and a desired result is obtained. It will be.

  On the other hand, in the case of the type of timing d which is a pattern in which synchronization is detected, the sum of odd numbers becomes a negative maximum value, and the sum of even numbers becomes a positive value. Can be obtained. Therefore, when a pattern of the timing d type comes, that is, when the last synchronization is to be obtained, a negative value is correctly calculated, and it can be seen that synchronization can be acquired at the correct position.

  The above is the synchronization acquisition process corresponding to each TFC1 to TFC7 in this example, and the only difference is that the time of the other party performing the complex multiplication is different. Therefore, a plurality of shift registers are prepared in hardware, and the selector 133 shown in FIG. 2 selects which data and which data are extracted from the predetermined TFC and subjected to complex multiplication. Therefore, it becomes possible to support each TFC.

  In the embodiment described so far, the description has been given of an example in which the circuit configuration shown in FIGS. 1 and 2 is applied. However, for example, a part or all of the same synchronization detection processing method is programmed. And may be performed by executing the program.

  In the above-described embodiment, the present invention is applied to the case of receiving an MB-OFDM wireless signal defined by the IEEE 802.15.3 standard. The present invention can also be applied to reception processing of other communication methods for detecting a synchronization signal from the other synchronization signal pattern.

It is a block diagram which shows the example of a receiving structure by one embodiment of this invention. It is a block diagram which shows the example of a synchronous detection structure by one embodiment of this invention. It is the block diagram which showed the example of the selector by one embodiment of this invention. It is the flowchart which showed the example of the synchronous detection process by one embodiment of this invention. It is explanatory drawing which shows the example of a detection of the signal of each pattern by one embodiment of this invention. It is explanatory drawing which showed the reception state in each timing at the time of the synchronous signal reception of TFC5, TFC6, and TFC7 by one embodiment of this invention. It is a wave form diagram which shows the example of the detection waveform by one embodiment of this invention. It is a timing diagram which shows the example of a detection by one embodiment of this invention. It is a block diagram which shows the example of a conventional receiving structure. It is explanatory drawing which shows the example of the transmission pattern of a preamble signal. It is a block diagram which shows the example of a conventional synchronous detection structure.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Antenna, 102 ... Frequency converter, 103 ... Carrier wave signal generator, 104 ... AGC circuit, 105 ... A / D converter, 106, 107, 108 ... Shift register, 120 ... Received energy and moving average detection unit, 131 , 132 ... adder, 133 ... selector, 134, 135 ... correlator, 136 ... complex multiplier, 137 ... divider, 138 ... synchronization detector, 140 ... moving average detector

Claims (6)

A reception method of receiving the transmission signal by performing synchronization detection processing of the reception signal based on a known synchronization signal included in the transmission signal,
As the known synchronization signal, one unit of synchronization signal is repeatedly transmitted for a predetermined period, and there are a plurality of transmission frequency patterns set for each unit and a plurality of signal polarity patterns set for each unit. In case of receiving method,
The received signal is delayed by a plurality of stages in the unit cycle, and a plurality of received signals at at least two delay positions are extracted from the received signals delayed by the plurality of stages in different combinations, and received from the received signals of the plurality of combinations. Selecting a received signal of at least two delay positions in a combination selected according to the synchronization signal pattern to be
Perform correlation detection from each of the selected received signals,
A receiving method comprising: obtaining a moving average from a signal obtained by complex multiplication of each correlation detection signal, and performing the synchronization signal detection. The receiving method according to claim 1,
The reception energy and the moving average are obtained from the received signal, the moving average value obtained from the complex multiplication signal is divided by the obtained value, and the synchronization signal is detected from the divided signal. Characteristic reception method. The receiving method according to claim 1,
The received signals at the at least two delay positions are
A combination of a first received signal and a second received signal one unit period away from the first received signal;
A combination of a first received signal and a second received signal that is 3 unit periods away from the first received signal;
A combination of a signal obtained by adding the first and second received signals separated by two unit periods and a signal obtained by adding the third and fourth received signals delayed by one unit period from the first and second received signals, respectively. Yes,
The reception method, wherein the correlation detection is performed from a received signal of a combination selected from the three combinations. A receiver that receives the transmission signal by performing synchronization detection processing of the reception signal based on a known synchronization signal included in the transmission signal,
As the known synchronization signal, one unit of synchronization signal is repeatedly transmitted for a predetermined period, and there are a plurality of transmission frequency patterns set for each unit and a plurality of signal polarity patterns set for each unit. In the receiver in case
Delay means for delaying a received signal by a plurality of stages in the unit period;
A plurality of received signals of at least two delay positions are extracted from the received signals delayed by a plurality of stages by the delay means in different combinations, and selected from the received signals of the plurality of combinations according to the received synchronization signal pattern Selecting means for selecting received signals of at least two delay positions of the combination;
A plurality of correlation detection means for performing correlation detection from each received signal selected by the selection means;
Complex multiplication means for complex multiplication of the correlation detection signals detected by the plurality of correlation detection means;
Moving average detection means for obtaining a moving average from the signal complex-multiplied by the complex multiplication means;
A receiver comprising: synchronization detection means for detecting a synchronization signal from the moving average detected by the moving average detection means. The receiver of claim 1, wherein
Received energy and moving average calculating means for calculating received energy and moving average from the received signal;
Dividing means for dividing the detected value of the moving average detecting means by the value calculated by the received energy and the moving average calculating means and sending the divided signal to the synchronization detecting means. Receiving machine. The receiver according to claim 4, wherein
The received signals of at least two delay positions selected by the selection means are:
A combination of a first received signal and a second received signal one unit period away from the first received signal;
A combination of a first received signal and a second received signal that is 3 unit periods away from the first received signal;
A combination of a signal obtained by adding the first and second received signals separated by two unit periods and a signal obtained by adding the third and fourth received signals delayed by one unit period from the first and second received signals, respectively. Yes,
A receiver characterized in that selection is made from the three combinations.

Images