JP2009141634A - Radio receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a frequency offset between transceivers by a relatively small circuit scale in a radio receiver of a direct-conversion system. <P>SOLUTION: A determination part 12 selects output of a matched filter 11 corresponding to a channel (a TFC) capturing synchronization at timing of detecting the synchronization and outputs the output (an output signal a). An n-symbol delay circuit 21 and a complex-conjugate calculator 22 take a complex conjugate by delaying the output signal a by n symbols. A multiplier 23 multiplies the complex conjugate by the output signal a. The output of the multiplier 23 is input to an arctangent calculator 24 as it is, and consequently, there is no need for an integrator. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a radio receiver using a direct conversion method such as an OFDM method.

  In recent years, a wireless personal area network (WPAN) for transmitting a short distance at a very high speed as compared with a mobile phone or a wireless LAN has been studied. As a technique for realizing WPAN, ultra wideband wireless (UWB) using 3.1 GHz to 10.6 GHz is considered promising.

  As one UWB system, a multiband OFDM (MB-OFDM) system promoted by the WiMedia Alliance is being studied. The MB-OFDM scheme is a scheme that combines OFDM (Orthogonal Frequency Division Multiplex) modulation and frequency hopping that switches a carrier frequency according to a specific frequency pattern.

  In recent wireless communication systems, not limited to the MB-OFDM system and OFDM system, a direct conversion system is often used as a receiver configuration. In particular, in the case of the MB-OFDM system, since the modulation band is very wide with respect to the carrier frequency, the direct conversion system is usually used.

  The direct conversion method is also referred to as a zero IF method, and is a method of converting a signal received by a receiver into a baseband at once without converting (down-converting) a radio frequency band to an intermediate frequency.

A general configuration example of a direct conversion wireless receiver is shown in FIG.
In the configuration example shown in FIG. 6, the reception signal received by the antenna is amplified by the amplifier 51 and then input to the quadrature detection unit 52. In addition, although AGC (Automatic Gain Control) control is performed regarding amplification, it abbreviate | omits here. The quadrature detection unit 52 receives Lo oscillation signals orthogonal to each other from the Lo oscillation unit 53, and thereby converts the input signal into a baseband signal. This baseband signal is A / D converted by the A / D converter 54. Thereafter, synchronization / demodulation processing and the like are performed by digital signal processing.

  The output of the A / D converter 54 is input to a synchronization acquisition unit 55, a multiplier 56, and a frequency correction unit 57, and synchronization detection is performed by the synchronization acquisition unit 55, and a frequency deviation is detected by the multiplier 56 and the frequency correction unit 57. to correct. The corrected signal is input to an FFT (Fast Fourier Transform) unit 58. Note that the FFT unit 58 and the subsequent configuration (multiplier 59, channel estimation unit 60, despread unit / demapping unit 61, deinterleave unit / Viterbi decoder 62) are not related here and will not be particularly described.

  Here, in the case of wireless communication, synchronization between transceivers is an important issue. In a wireless system using OFDM modulation as well as the MB-OFDM system, a known code (preamble) for acquisition of synchronization may be added prior to an OFDM symbol group (header or PSDU) for transmitting information. It is common.

  In the synchronization acquisition unit 55 of the receiver, a matched filter having the same pattern as a known preamble is prepared in advance, and synchronization is detected by detecting a peak due to the correlation characteristic of the code.

FIG. 7 shows a configuration example of the synchronization capturing unit 55.
As shown in the figure, as many matched filters 71 as the number of channels (TFC) are prepared, and received signals (outputs of the A / D converter 54) are input to the matched filters 71 (TFC 1 to TFC N), From the peak, the determination unit 72 detects the TFC and synchronization timing of the received signal.

  By the way, because the transmitter and the receiver are based on different frequency standards or due to relative movement between the transmitter and the receiver, the signal received at the receiver has a frequency deviation (error) (usually, Accompanied by several tens of ppm). In order to correct this, the frequency correction unit 57 (AFC circuit) is provided.

FIG. 8 shows a configuration example of the frequency correction unit 57 (AFC circuit).
The input signal of the frequency correction unit 57 is the output (digital signal) of the A / D converter 54 as described above, and this digital input signal is processed by the n × m sample delay circuit 81 for n times the time of m samples. After the delay, the complex conjugate calculator 82 multiplies the complex conjugate by the multiplier 83 using the complex conjugate. The output from the multiplier 83 is integrated in the interval of length m by the integrator 84, and the arc tangent calculator 85 takes the arc tangent (actan) as a phase rotation amount, which is divided by the n symbol interval. Is output to the numerically controlled oscillator (NCO 86) as a frequency correction amount. Then, a signal that cancels the frequency correction amount is generated by the numerically controlled oscillator (NCO 86), and the received signal is multiplied by the multiplier 56, whereby the frequency deviation can be corrected.

  In the case of the MB-OFDM system, n is generally 1 or 3. The A / D converter 54 operates based on a predetermined sampling clock. In this case, m samples are output per symbol, and m = ‘165’ is generally set. Therefore, the “time for m samples” means “time for one symbol”.

Regarding the MB-OFDM receiving circuit including these frequency corrections, for example, there is an invention described in Patent Document 1, but a general AFC circuit has a long delay circuit and a long length to calculate the autocorrelation. Since an integrator in the section is required, the circuit scale and power consumption for calculation increase.
JP 2007-19985 A

  An object of the present invention is to provide a wireless receiver in a direct conversion wireless system such as the MB-OFDM method, for example, by using a matched filter output used in a synchronization acquisition circuit and performing auto-correlation between the transmitter and the receiver. It is an object of the present invention to provide a radio receiver or the like that can correct the frequency offset between the transmitter and the receiver with a relatively small circuit scale.

  The first radio receiver of the present invention is a direct conversion radio receiver having a synchronization acquisition circuit having a plurality of matched filters for each channel, and the synchronization acquisition circuit is synchronized at a timing when synchronization is detected. A decision means for selecting and outputting the output of the matched filter corresponding to the channel that captured the signal, an n-symbol delay circuit for receiving the output of the decision means and delaying it by n symbols, A complex conjugate calculator that takes a complex conjugate of the output; a multiplier that inputs the output of the complex conjugate calculator and multiplies the output of the determination means; and an arctangent calculator that calculates a frequency deviation based on the output of the multiplier And have.

  In the wireless receiver having the above-described configuration, the conventional integrator is not necessary by using the matched filter output (particularly, the peak value output output at the symbol period) used in the synchronization acquisition circuit. An n-symbol delay circuit or the like for obtaining autocorrelation operates with a clock having a symbol period.

  The second wireless receiver of the present invention is a direct conversion wireless receiver having a synchronization acquisition circuit having a plurality of matched filters for each channel, and inputs the outputs of the matched filters. Switch means for selecting / outputting any one of the inputs, and the synchronization acquisition circuit causes the switch means to select / output the output of the matched filter corresponding to the channel that has acquired synchronization at the timing at which synchronization is detected An n-symbol delay circuit which has a determination unit and inputs either the output signal of the switch unit or each delay signal obtained by delaying the output signal by one sample, and delays by n symbols; and the n-symbol delay circuit A complex conjugate computing unit that takes the complex conjugate of the output of the output of the switch, and the output of the complex conjugate computing unit. Each circuit section of a multistage configuration including a multiplier that multiplies any one of the delay signals, an average value calculating means for calculating an average of outputs of each multiplier of each circuit section of the multistage configuration, and the average An arc tangent calculator for obtaining a frequency deviation based on the output of the value calculating means.

  The second radio receiver is basically based on the first radio receiver and has a configuration corresponding to a case where multiple reflections due to a radio line occur.

  According to the wireless receiver and the like of the present invention, in a wireless receiver in a direct conversion system wireless system such as the MB-OFDM system, the peak value self is obtained using the matched filter output used in the synchronization acquisition circuit. The frequency offset between the transceivers can be corrected by the correlation, and thus the frequency offset between the transceivers can be corrected with a relatively small circuit scale.

Embodiments of the present invention will be described below with reference to the drawings.
In the following description, a wireless receiver in the MB-OFDM wireless system will be described as an example, but the present invention is not limited to this example.

FIG. 1 shows a configuration example (referred to as a frequency correction device) related to frequency correction in the wireless receiver of this example.
Here, the overall configuration of the radio receiver including the frequency correction device is not particularly shown, but is basically the same as the conventional configuration shown in FIG. 6, but the input of the frequency correction circuit 20 of this example is shown in the figure. As shown, the output a of the synchronization acquisition circuit 10 is obtained. That is, after replacing the frequency correction unit 57 in FIG. 6 with the frequency correction circuit 20 and the synchronization acquisition unit 55 with the synchronization acquisition circuit 10, the input of the frequency correction circuit 20 is not the output of the A / D converter 54, but the synchronization. The output a of the capture circuit 10 is configured.

  Here, the synchronization acquisition circuit 10 of this example has a plurality of matched filters 11 for each channel (TFC) as in the conventional case, and the determination unit 12 is based on the outputs of the plurality of matched filters 11 in the related art. The synchronous detection signal is output in the same manner as described above, but the output of one of the matched filters 11 is further selected and output (this is the output signal a shown in the figure). This selects and outputs the output of the matched filter 11 corresponding to the channel (TFC) that has acquired synchronization at the timing at which synchronization is detected.

The frequency correction circuit 20 includes an n symbol delay circuit 21, a complex conjugate calculator 22, a multiplier 23, an arctangent calculator 24, and a numerically controlled oscillator (NCO) 25.
Compared with the conventional configuration of FIG. 8, the integrator 84 is not necessary, and an n symbol delay circuit 21 is provided instead of the n × m sample delay circuit. However, the delay amount does not change. That is, the n symbol delay circuit 21 delays the delay amount n times the time corresponding to one OFDM symbol, and the delay amount itself is the same in the n × m sample delay circuit 81 as described above. is there. Note that the meaning of 'n' is 1 or 3 in the MB-OFDM system as described above.

  As is well known, since the output of the matched filter 11 has a peak that appears in a symbol period (an example is shown in FIG. 3), the frequency correction circuit 20 of the present example described above has a symbol period in this way. The peak output of the matched filter 11 appearing at is used for frequency correction.

  That is, since the conventional frequency correction circuit inputs the output of the A / D converter as described above, it operates in accordance with the sampling clock (sampling period) of the A / D converter. The frequency correction circuit 20 operates with a clock signal having a symbol period. As a result, the n symbol delay circuit 21 of this example is not “n × m samples”, but a delay of n symbols (n times of a symbol period clock) as described above.

  That is, regarding the A / D conversion output, m-sample output per symbol is input to the matched filter 11 (conventionally to the delay circuit 81), but input to the delay circuit 21 of this example (conventionally of the integrator 84). Output) operates at a symbol period (one per symbol).

  Although not particularly shown, the clock signal having the symbol period is generated by, for example, multiplying the sampling clock signal by a multiplier or the like (here, 165 times in the above example).

  Further, since the conventional integrator 84 integrates in the section of “length m (for one OFDM symbol)” as described above, the frequency correction is performed only in the symbol period, and further, the integration result and the matched result are matched. Since it can be considered that the peak output of the filter 11 is substantially equivalent, the circuit configuration of this example can be considered to replace the integrator 84 with the matched filter 11 in outline.

As described above, in the frequency correction circuit 20 of this example, the conventional integrator 84 is not necessary and operates as follows.
That is, the output signal a from the synchronization acquisition circuit 10 is input to the n symbol delay circuit 21 and the multiplier 23. After delaying the output signal a by n symbols as described above by the n symbol delay circuit 21, the complex conjugate calculator 82 multiplies the output signal a by the multiplier 83 with the output signal a. Then, in the arc tangent calculator 24, the phase rotation amount φ is obtained by taking the arc tangent of the multiplication result by the multiplier 83, and further the frequency deviation is obtained by dividing the phase rotation amount φ by the delay time. By passing this frequency deviation to the numerically controlled oscillator (NCO) 25, the frequency deviation is corrected.

Here, FIGS. 2A and 2B show a standard data frame configuration in the MB-OFDM system.
The frame shown in FIG. 2A is composed of three parts: a PLCP (Physical Layer Convergence Protocol) preamble 31, a PLCP header 32, and a PSDU 33 (payload). Among these, the PLCP preamble 31 is, as shown in FIG.
It consists of a packet / frame synchronization sequence 34 and a channel estimation sequence 35. In each sequence, frequency packet / frame synchronization and estimation of a transfer function of a radio channel are performed.

The frequency correction is performed when the packet / frame synchronization sequence 34 is received.
The packet length of the MB-OFDM scheme is about several hundred microseconds at the maximum, and since it does not have a cyclic prefix as found in the conventional IEEE802.11 standard, in the OFDM symbol in the PSDU33 (payload) section, Detection and correction of frequency deviation due to autocorrelation are not performed, and correction is applied to the end of the packet with the frequency correction amount obtained in the section of the packet / frame synchronization sequence 34.

  When the packet / frame synchronization sequence 34 is received, for example, an output as shown in FIG. 3 is obtained from the corresponding matched filter 11 in the synchronization acquisition circuit 10. FIG. 3 shows the amplitude of the matched filter output, and the actual output is a complex number.

  The determination unit 12 detects synchronization based on the amplitude peak of the matched filter output. The determination unit 12 outputs the output (complex number; x) of the corresponding matched filter 11 to the delay circuit 21 and the multiplier 23 as described above at this synchronization detection timing. As shown in FIG. 3, since the matched filter 11 outputs a peak in the symbol period of the preamble signal, the signal a (x (j)) input to the multiplier 23 is set to n symbols before the signal a. Is multiplied by the complex conjugate of the signal a (x (j−n)), the output (y (j)) of the multiplier 23 is as follows:

  Here, in order to obtain the phase rotation amount φ in the arctangent calculator 24,

  Than,

Perform the operation.
The frequency offset (deviation) δf is

More obtained. Here, n differs depending on the TFC, and is assumed to be n = 3 when TFC = 1 or 2, and n = 1 otherwise. As is well known, in the MB-OFDM system, there are seven TFC patterns (TFC1 to TFC7). As shown in FIG. 4, TFC1 and TFC2 are for each symbol, and TFC3 and TFC4 are for every two symbols. This is a frequency hopping pattern. TFC5 to TFC7 are patterns that do not perform frequency hopping.

  The determination unit 72 of the conventional synchronization acquisition unit 55 detects the TFC and synchronization timing of the received signal as described above, and the determination unit 12 of this example similarly determines the TFC. Based on the above, the value of n is determined.

  As shown in FIG. 4, TFC1 and TFC2 have a pattern of 3 symbol periods for the same band, and TFC3 to TFC7 have a pattern of 1 symbol period. As described above, when TFC = 1 or 2, n = 3. Otherwise, n = 1.

FIG. 4 is a diagram showing a frequency hopping pattern for each TFC and an image of frequency correction according to the frequency hopping pattern.
Then, a signal that cancels the frequency offset (deviation) δf obtained by the above calculation formula is generated by the numerically controlled oscillator (NCO) 25 and multiplied by the received signal (conventional multiplier 56). The frequency deviation can be corrected.

  As described above, the frequency correction apparatus of this example can correct the frequency offset between the transmitter and the receiver by the autocorrelation of the peak value by using the output of the matched filter of the synchronization acquisition circuit 10, thereby comparing The frequency offset between the transmitter and the receiver can be corrected with a small circuit scale.

  By the way, when multiple reflections are caused by the radio line, the output of the corresponding matched filter 11 may not show a sharp peak as in the example shown in FIG. In such a case, the synchronization acquisition circuit normally performs synchronization detection based on the moving average of the matched filter output. In this example, for example, the configuration shown in FIG.

  FIG. 5 shows an example of the configuration of the frequency correction apparatus of this example corresponding to the case where multiple reflection occurs due to the above-described wireless line. Note that, in each configuration shown in the figure, the same reference numerals are given to configurations that are substantially the same as the configurations shown in FIG.

  First, the synchronization acquisition circuit 41 shown in the figure corresponds to each of the matched filters 11 shown in FIG. 1, inputs the output thereof, calculates the moving average, and outputs the moving average to the determination unit 43. The unit 42 is provided. Further, the output of each matched filter 11 is input to the outside of the synchronization acquisition circuit 41, and any one of the inputs from the plurality of matched filters 11 is selected according to the selection instruction signal b output from the determination unit 43. A switch 44 for selecting and outputting is provided.

  In this example, unlike the determination unit 12 in FIG. 1, since the output of each matched filter 11 is not input to the determination unit 43, the configuration is made accordingly. Therefore, as a result, any of the outputs of the matched filters 11 is input to the illustrated frequency correction circuit 40 as the output signal a as in FIG.

  Therefore, the determination unit 43 outputs the output of the matched filter 11 corresponding to the channel (TFC) that has acquired the synchronization at the timing when the synchronization is detected, based on the outputs of the plurality of moving average calculation units 42 as in the case of FIG. Is selected and output by the switch 44, the selection instruction signal b is generated and output.

The configuration of the frequency correction circuit 40 of this example that inputs the output signal a is as shown in the figure.
The configuration including the n-symbol delay circuit 21, the complex conjugate calculator 22 and the multiplier 23 is provided in a plurality of stages. As shown in the figure, the output signal a is input to the first stage. In the second and subsequent stages, a signal obtained by delaying the output signal a by each delay circuit 46 is input. For example, a signal delayed by one delay circuit 46 is input to the second stage, and a signal delayed by two delay circuits 46 is input to the third stage. Is configured to receive signals delayed by (p−1) delay circuits 46.

  Here, each delay circuit 46 delays one sample (the above sampling period). A signal delayed by d samples (d will be described later) is input to the final stage in the configuration provided with a plurality of stages.

  Then, all the outputs of the multipliers 23 at each stage are input to the averaging unit 45, the average of all the outputs of the multipliers 23 is calculated, and the output of the averaging unit 45 is input to the arctangent calculator 24. The arc tangent calculator 24 and the numerically controlled oscillator (NCO) 25 are the same as those in FIG.

  Here, it is assumed that the reflected wave is received until a time delay corresponding to d samples with respect to the direct wave in the wireless line. Normally, d << m holds in the OFDM modulation scheme. Thus, with the configuration shown in FIG. 5, the output of the matched filter corresponding to the TFC in which the preamble synchronization is captured is calculated to correlate with the n symbol delay for each incident wave (similar to the calculation of the frequency deviation). Then, for each symbol period, an average of d frequency deviations is calculated to obtain a frequency correction amount.

  As described above, in the configuration of this example, it is possible to perform frequency correction with a relatively small circuit scale in a wireless receiver in a direct conversion wireless system such as the MB-OFDM method, for example. It is also possible to cope with the case where multiple reflections occur due to the wireless line.

It is a structural example of the frequency correction apparatus of this example. (A), (b) is a figure which shows the standard data frame structure in MB-OFDM system. It is an example of the output signal waveform from a matched filter. It is a figure which shows the image of the frequency hopping pattern for every TFC, and the frequency correction according to this. It is an example of a structure of the frequency correction apparatus of this example corresponding to the case where the multiple reflection by a radio link has generate | occur | produced. 2 is a general configuration example of a direct conversion wireless receiver. It is an example of a structure of a synchronous acquisition part. It is a structural example of a frequency correction | amendment part (AFC circuit).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Synchronization acquisition circuit 11 Matched filter 12 Judgment part 20 Frequency correction circuit 21 n symbol delay circuit 22 Complex conjugate calculator 23 Multiplier 24 Inverse tangent calculator 25 Numerical control oscillator (NCO)
31 PLCP preamble 32 PLCP header 33 PSDU (payload)
34 packet / frame synchronization sequence 35 channel estimation sequence 40 frequency correction circuit 41 synchronization acquisition circuit 42 moving average calculation unit 43 determination unit 44 switch 45 adder 46 delay circuit

Claims (2)

A direct conversion wireless receiver having a synchronization acquisition circuit having a plurality of matched filters for each channel,
The synchronization acquisition circuit further includes a determination unit that selects and outputs an output of the matched filter corresponding to a channel that has acquired synchronization at a timing at which synchronization is detected;
An n-symbol delay circuit for inputting the output of the determination means and delaying it by n symbols;
A complex conjugate calculator that takes the complex conjugate of the output of the n symbol delay circuit;
A multiplier for inputting the output of the complex conjugate calculator and multiplying the output of the determination means;
An arctangent calculator for determining a frequency deviation based on the output of the multiplier;
A wireless receiver comprising: A direct conversion wireless receiver having a synchronization acquisition circuit having a plurality of matched filters for each channel,
Switch means for inputting the output of each matched filter and selecting and outputting one of the inputs;
The synchronization acquisition circuit has a determination unit that causes the switch unit to select and output the output of the matched filter corresponding to a channel that has acquired synchronization at a timing at which synchronization is detected,
An n-symbol delay circuit that inputs either the output signal of the switch means or each delayed signal obtained by delaying the output signal by one sample and delays it by n symbols, and a complex conjugate of the output of the n-symbol delay circuit. Each circuit unit of a multi-stage configuration comprising: a complex conjugate arithmetic unit that takes an output; and a multiplier that inputs the output of the complex conjugate arithmetic unit and multiplies either the output signal of the switch means or each of the delayed signals;
Average value calculating means for calculating the average of the outputs of the multipliers of the circuit sections of the multistage configuration;
An arc tangent calculator for obtaining a frequency deviation based on the output of the average value calculating means;
A wireless receiver comprising:

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