JP2006191145A - Multilayer wiring board - Google Patents

Multilayer wiring board Download PDF

Info

Publication number
JP2006191145A
JP2006191145A JP2006076654A JP2006076654A JP2006191145A JP 2006191145 A JP2006191145 A JP 2006191145A JP 2006076654 A JP2006076654 A JP 2006076654A JP 2006076654 A JP2006076654 A JP 2006076654A JP 2006191145 A JP2006191145 A JP 2006191145A
Authority
JP
Japan
Prior art keywords
liquid crystal
crystal polymer
layer
wiring board
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2006076654A
Other languages
Japanese (ja)
Inventor
Takuji Seri
拓司 世利
Katsura Hayashi
桂 林
Tadashi Nagasawa
忠 長澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2006076654A priority Critical patent/JP2006191145A/en
Publication of JP2006191145A publication Critical patent/JP2006191145A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To satisfy the densification and solder thermal resistance of wiring and both an insulation property and high-frequency transmission characteristics in a multilayer printed circuit board formed by laminating insulating layers each containing an organic material. <P>SOLUTION: In the multilayer wiring board 4 made of an organic material, which is formed by laminating a plurality of the insulating layers 1 in which a wiring conductor 2 made of a metal foil is arranged to at least one surface of upper and lower surfaces and which is connected electrically between the wiring conductors 2 located above and below the insulating layer through a penetration conductor 3 formed in the insulating layer, the insulating layer 1 is made by forming a coating layer 6 made of a polyphenylene ether organic substance on the upper and lower surfaces of a liquid crystal polymer layer 5 in which the surface is plasma-treated. Perforating processing is easy and the densification of the wiring becomes possible. Moreover, the coating layer 6 made of a polyphenylene ether organic substance exhibits high adhesive property with the liquid crystal polymer layer 5 and the wiring conductors 2, and does not lower the transmission characteristics in high-frequency by exhibiting the same dielectric constant as the liquid crystal polymer, and is excellent in the solder thermal resistance, the insulation property and the high-frequency transmission characteristics. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、各種AV機器や家電機器・通信機器・コンピュータやその周辺機器等の電子機器に使用される多層配線基板に関するものであり、特に絶縁層の一部に液晶ポリマー層を用いた多層配線基板に関するものである。   The present invention relates to a multilayer wiring board used in various AV equipment, home appliances, communication equipment, computers, and electronic equipment such as peripheral equipment thereof, and in particular, multilayer wiring using a liquid crystal polymer layer as a part of an insulating layer. It relates to a substrate.

従来、半導体素子等の能動部品や容量素子・抵抗素子等の受動部品を多数搭載して所定の電子回路を構成した混成集積回路を形成するための多層配線基板は、通常、ガラスクロスにエポキシ樹脂を含浸させて成る絶縁層にドリルによって上下に貫通孔を形成し、この貫通孔内部および絶縁層表面に複数の配線導体を形成した配線基板を、多数層積層することによって形成されている。   Conventionally, a multilayer wiring board for forming a hybrid integrated circuit in which a predetermined electronic circuit is configured by mounting a large number of active components such as semiconductor elements and passive components such as capacitance elements and resistance elements is usually an epoxy resin on a glass cloth. Through-holes are formed in an insulating layer formed by impregnating the top and bottom with a drill, and a plurality of wiring boards each having a plurality of wiring conductors formed in the through-holes and on the surface of the insulating layer are laminated.

一般に、現在の電子機器は、移動体通信機器に代表されるように小型・薄型・軽量・高性能・高機能・高品質・高信頼性が要求されており、このような電子機器に搭載される混成集積回路等の電子部品も小型・高密度化が要求されるようになってきており、このような高密度化の要求に応えるために、電子部品を構成する多層配線基板も、配線導体の微細化や絶縁層の薄層化・貫通孔の微細化が必要となってきている。このため、近年、貫通孔を微細化するために、ドリル加工より微細加工が可能なレーザ加工が用いられるようになってきた。   In general, current electronic devices are required to be small, thin, lightweight, high performance, high functionality, high quality, and high reliability, as represented by mobile communication devices. Electronic components such as hybrid integrated circuits are required to be smaller and higher in density, and in order to meet the demand for higher density, multilayer wiring boards constituting electronic components are also used as wiring conductors. Therefore, it is necessary to reduce the thickness of the insulating layer, the thickness of the insulating layer, and the size of the through hole. For this reason, in recent years, in order to miniaturize the through hole, laser processing capable of performing fine processing rather than drill processing has been used.

しかしながら、ガラスクロスにエポキシ樹脂を含浸させて成る絶縁層は、ガラスクロスをレーザにより穿設加工することが困難なために貫通孔の微細化には限界があり、また、ガラスクロスの厚みが不均一のために均一な孔径の貫通孔を形成することが困難であるという問題点を有していた。   However, an insulating layer formed by impregnating an epoxy resin into a glass cloth has a limit in miniaturizing the through-hole because it is difficult to drill the glass cloth with a laser, and the thickness of the glass cloth is not sufficient. For the sake of uniformity, there is a problem that it is difficult to form a through hole having a uniform hole diameter.

このような問題点を解決するために、アラミド樹脂繊維で製作した不織布にエポキシ樹脂を含浸させた絶縁基材や、ポリイミドフィルムにエポキシ系接着剤を塗布した絶縁基材を絶縁層に用いた多層配線基板が提案されている。   In order to solve such problems, an insulating base material in which a non-woven fabric made of aramid resin fibers is impregnated with an epoxy resin, or an insulating base material in which an epoxy adhesive is applied to a polyimide film is used as an insulating layer. A wiring board has been proposed.

しかしながら、アラミド不織布やポリイミドフィルムを用いた絶縁基材は吸湿性が高く、吸湿した状態で半田リフローを行なうと半田リフローの熱により吸湿した水分が気化してガスが発生し、絶縁層間で剥離してしまう等の問題点を有していた。   However, insulating base materials using aramid nonwoven fabric and polyimide film are highly hygroscopic, and when solder reflow is performed while moisture is absorbed, moisture absorbed by the heat of solder reflow is vaporized and gas is generated and delaminated between insulating layers. There was a problem such as.

このような問題点を解決するために、多層配線基板の絶縁層の材料として液晶ポリマーを用いることが検討されている。液晶ポリマーから成る層は、剛直な分子で構成されているとともに分子同士がある程度規則的に並んだ構成をしており分子間力が強いことから、高耐熱性・高弾性率・高寸法安定性・低吸湿性を示し、ガラスクロスのような強化材を用いる必要がなく、また、微細加工性にも優れるという特徴を有している。さらに、高周波領域においても、低誘電率・低誘電正接であり高周波特性に優れるという特徴を有している。   In order to solve such problems, it has been studied to use a liquid crystal polymer as a material for an insulating layer of a multilayer wiring board. The layer made of liquid crystal polymer is composed of rigid molecules and has a structure in which the molecules are regularly arranged to some extent and the intermolecular force is strong, so it has high heat resistance, high elastic modulus, and high dimensional stability. -It has low hygroscopicity, does not require the use of a reinforcing material such as glass cloth, and is excellent in fine workability. Furthermore, the high frequency region also has the characteristics of low dielectric constant and low dielectric loss tangent and excellent high frequency characteristics.

このような液晶ポリマーの特徴を活かし、特開平8-97565号公報には、回路層が第1の液晶ポリマーを含み、この回路層間に第1の液晶ポリマーの融点よりも低い融点を有する第2の液晶ポリマーを含む接着剤層を挿入して成る多層プリント回路基板が提案されており、また、特開2000-269616号公報には熱可塑性液晶ポリマーフィルムと金属箔とをエポキシ系接着剤を用いて接着させた高周波回路基板が提案されている。
特開平8-97565号公報 特開2000-269616号公報
Taking advantage of such characteristics of the liquid crystal polymer, Japanese Patent Application Laid-Open No. 8-97565 discloses a second circuit layer including a first liquid crystal polymer and a melting point lower than the melting point of the first liquid crystal polymer between the circuit layers. A multilayer printed circuit board in which an adhesive layer containing a liquid crystal polymer is inserted has been proposed, and JP-A-2000-269616 uses a thermoplastic liquid crystal polymer film and a metal foil with an epoxy adhesive. A high-frequency circuit board that has been bonded together has been proposed.
JP-A-8-97565 Japanese Unexamined Patent Publication No. 2000-269616

しかしながら、特開平8-97565号公報に提案された多層プリント回路基板は、回路層を間に液晶ポリマーを含む接着剤層を挿入して熱圧着により接着する際、液晶ポリマー分子が剛直で動き難いために回路層表面の微細な凹部に入ることができず、その結果、十分なアンカー効果を発揮することができず、回路層と接着剤層との密着性が悪く高温バイアス試験で絶縁不良が発生してしまうという問題点を有していた。   However, in the multilayer printed circuit board proposed in Japanese Patent Laid-Open No. 8-97565, the liquid crystal polymer molecules are rigid and difficult to move when the circuit layer is bonded by thermocompression bonding with an adhesive layer containing a liquid crystal polymer interposed therebetween. For this reason, it is not possible to enter the fine recesses on the surface of the circuit layer, and as a result, a sufficient anchor effect cannot be exhibited, and the adhesion between the circuit layer and the adhesive layer is poor, resulting in poor insulation in the high temperature bias test. It had the problem that it would occur.

また、特開2000-269616号公報に提案された高周波回路基板は、エポキシ系接着剤の誘電率が液晶ポリマーの誘電率と大きく異なることから、積層時の加圧によって生じるわずかな厚みばらつきにより、高周波領域、特に100MHz以上の周波数領域においては伝送特性が低下してしまうという問題点を有していた。   In addition, the high frequency circuit board proposed in Japanese Patent Application Laid-Open No. 2000-269616, because the dielectric constant of the epoxy adhesive is significantly different from the dielectric constant of the liquid crystal polymer, due to slight thickness variations caused by pressure during lamination, There is a problem that transmission characteristics deteriorate in a high frequency region, particularly in a frequency region of 100 MHz or higher.

本発明はかかる従来技術の問題点に鑑み案出されたものであり、その目的は、高密度な配線を有するとともに、半田耐熱性・絶縁性・高周波伝送特性に優れた多層配線基板を提供することに有る。   The present invention has been devised in view of the problems of the prior art, and an object thereof is to provide a multilayer wiring board having high-density wiring and excellent solder heat resistance, insulation, and high-frequency transmission characteristics. There is.

本発明の多層配線基板は、有機材料から成り、上下面の少なくとも1つの面に金属箔から成る配線導体が配設された複数の絶縁層を積層して成るとともに、この絶縁層を挟んで上下に位置する配線導体間を絶縁層に形成された貫通導体を介して電気的に接続した多層配線基板であって、絶縁層は、表面がプラズマ処理された液晶ポリマー層の上下面にポリフェニレンエーテル系有機物から成る被覆層を形成して成ることを特徴とするものである。   The multilayer wiring board of the present invention is formed by laminating a plurality of insulating layers made of an organic material and provided with wiring conductors made of metal foil on at least one of the upper and lower surfaces, and sandwiching the insulating layers therebetween. A multilayer wiring board in which wiring conductors located in each other are electrically connected via through conductors formed in an insulating layer, and the insulating layer is formed of a polyphenylene ether system on the upper and lower surfaces of a liquid crystal polymer layer whose surface is plasma-treated. It is characterized by forming a coating layer made of an organic substance.

本発明の多層配線基板によれば、絶縁層を表面がプラズマ処理された液晶ポリマー層の表面にポリフェニレンエーテル系有機物から成る被覆層を形成して成るものとしたことから、微細な貫通孔を穿設加工することが可能となり、その結果、高密度な配線を有する多層配線基板とすることができ、また、液晶ポリマー層とポリフェニレンエーテル系有機物から成る被覆層の誘電率の周波数挙動がほぼ等しいことから、積層の際にわずかな厚みばらつきが生じたとしても高周波領域における伝送特性の低下を生じることのない高周波伝送特性に優れた多層配線基板とすることできる。   According to the multilayer wiring board of the present invention, since the insulating layer is formed by forming a coating layer made of a polyphenylene ether organic material on the surface of the liquid crystal polymer layer whose surface has been plasma-treated, fine through holes are formed. As a result, a multilayer wiring board having high-density wiring can be obtained, and the frequency behavior of the dielectric constant of the liquid crystal polymer layer and the coating layer made of polyphenylene ether-based organic substance is almost equal. Therefore, even if slight thickness variations occur during the lamination, a multilayer wiring board having excellent high frequency transmission characteristics that does not cause deterioration of transmission characteristics in the high frequency region can be obtained.

さらに、ポリフェニレンエーテル系有機物から成る被覆層は、液晶ポリマー層と同程度の疎水性を示すことから、両者の樹脂同士の馴染みが良好で接着性に優れ、また、被覆層がランダムな分子構造で比較的熱運動しやすい分子から成ることから液晶ポリマー層表面の微細な凹部に入り込み十分なアンカー効果を発揮することができ、その結果、液晶ポリマー層と被覆層との密着性が良好となり高温バイアス試験で絶縁不良が発生することもない。さらにまた、液晶ポリマーが低吸湿性であることから、半田リフロー時に水分が気化してガスが発生することもなく、絶縁層間で剥離してしまうこともない。   Furthermore, the coating layer made of polyphenylene ether-based organic material exhibits the same level of hydrophobicity as the liquid crystal polymer layer, so that the two resins are well-familiar with each other and have excellent adhesion, and the coating layer has a random molecular structure. Because it is composed of molecules that are relatively easily moved by heat, it can penetrate into the minute recesses on the surface of the liquid crystal polymer layer and exert a sufficient anchoring effect. As a result, the adhesion between the liquid crystal polymer layer and the coating layer is improved, resulting in a high temperature bias. Insulation failure does not occur in the test. Furthermore, since the liquid crystal polymer has a low hygroscopic property, moisture is not vaporized during reflow of solder, gas is not generated, and separation between insulating layers does not occur.

次に本発明の多層配線基板を添付の図面に基づいて詳細に説明する。   Next, the multilayer wiring board of the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明の多層配線基板に半導体素子を搭載して成る混成集積回路の実施の形態の一例を示す断面図であり、また、図2は、図1に示す多層配線基板の要部断面図である。これらの図において1は絶縁層、2は配線導体、3は貫通導体で、主にこれらで本発明の多層配線基板4が構成されている。なお、本例では、絶縁層1を4層積層して成る多層配線基板4を示している。   FIG. 1 is a cross-sectional view showing an example of an embodiment of a hybrid integrated circuit in which a semiconductor element is mounted on the multilayer wiring board of the present invention, and FIG. 2 is a main part of the multilayer wiring board shown in FIG. It is sectional drawing. In these drawings, reference numeral 1 denotes an insulating layer, 2 denotes a wiring conductor, and 3 denotes a through conductor. The multilayer wiring board 4 of the present invention is mainly constituted by these. In this example, a multilayer wiring board 4 in which four insulating layers 1 are laminated is shown.

絶縁層1は、液晶ポリマー層5と、その表面に被着形成されたポリフェニレンエーテル系有機物から成る被覆層6とから構成されており、配線導体2や多層配線基板4に搭載される電子部品7の支持体としての機能を有する。   The insulating layer 1 is composed of a liquid crystal polymer layer 5 and a coating layer 6 made of a polyphenylene ether organic material deposited on the surface thereof, and an electronic component 7 mounted on the wiring conductor 2 or the multilayer wiring board 4. It has a function as a support.

なお、ここで液晶ポリマーとは、溶融時に液晶状態あるいは光学的に複屈折する性質を有するポリマーを指し、一般に溶液状態で液晶性を示すリオトロピック液晶ポリマーや溶融時に液晶性を示すサーモトロピック液晶ポリマー、あるいは、熱変形温度で分類される1型・2型・3型すべての液晶ポリマーを含むものである。また、ポリフェニレンエーテル系有機物とは、ポリフェニレンエーテル樹脂やポリフェニレンエーテルに種々の官能基が結合した樹脂、あるいはこれらの誘導体・重合体を意味するものである。   Here, the liquid crystal polymer refers to a polymer having a property of being in a liquid crystal state or optically birefringent when melted, generally a lyotropic liquid crystal polymer exhibiting liquid crystallinity in a solution state, or a thermotropic liquid crystal polymer exhibiting liquid crystallinity when melted, Alternatively, all liquid crystal polymers of type 1, type 2, and type 3 classified by the heat distortion temperature are included. The polyphenylene ether-based organic material means a polyphenylene ether resin, a resin in which various functional groups are bonded to polyphenylene ether, or a derivative / polymer thereof.

また、液晶ポリマーは、温度サイクル信頼性・半田耐熱性・加工性の観点からは200〜400℃の温度、特に250〜350℃の温度に融点を有するものが好ましく、さらに、層としての物性を損なわない範囲内で、熱安定性を改善するための酸化防止剤や耐光性を改善するための紫外線吸収剤等の光安定剤、難燃性を改善するためのハロゲン系もしくはリン酸系の難燃性剤、アンチモン系化合物やホウ酸亜鉛・メタホウ酸バリウム・酸化ジルコニウム等の難燃助剤、潤滑性を改善するための高級脂肪酸や高級脂肪酸エステル・高級脂肪酸金属塩・フルオロカーボン系界面活性剤等の滑剤、熱膨張係数を調整するため、および/または機械的強度を向上するための酸化アルミニウム・酸化珪素・酸化チタン・酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム・ゼオライト・窒化珪素・窒化アルミニウム・炭化珪素・チタン酸カリウム・チタン酸バリウム・チタン酸ストロンチウム・チタン酸カルシウム・ホウ酸アルミニウム・スズ酸バリウム・ジルコン酸バリウム・ジルコン酸ストロンチウム等の充填材を含有してもよい。   In addition, the liquid crystal polymer preferably has a melting point at a temperature of 200 to 400 ° C., particularly 250 to 350 ° C. from the viewpoint of temperature cycle reliability, solder heat resistance, and workability, and further has physical properties as a layer. Light stabilizers such as antioxidants to improve thermal stability and UV absorbers to improve light resistance, and halogen or phosphoric acid difficult to improve flame retardancy within the range that does not impair Flame retardants, flame retardant aids such as antimony compounds, zinc borate, barium metaborate, zirconium oxide, higher fatty acids, higher fatty acid esters, higher fatty acid metal salts, fluorocarbon surfactants to improve lubricity, etc. Aluminum oxide, silicon oxide, titanium oxide, barium oxide, strontium oxide, zirco for adjusting lubricant, adjusting thermal expansion coefficient and / or improving mechanical strength Filling with U.S., calcium oxide, zeolite, silicon nitride, aluminum nitride, silicon carbide, potassium titanate, barium titanate, strontium titanate, calcium titanate, aluminum borate, barium stannate, barium zirconate, strontium zirconate, etc. You may contain material.

なお、上記の充填材等の粒子形状は、略球状・針状・フレーク状等があり、充填性の観点からは略球状が好ましい。また、粒子径は、通常0.1〜15μm程度であり、液晶ポリマー層5の厚みよりも小さい。   The particle shape of the filler and the like includes a substantially spherical shape, a needle shape, and a flake shape, and a substantially spherical shape is preferable from the viewpoint of filling properties. The particle diameter is usually about 0.1 to 15 μm and is smaller than the thickness of the liquid crystal polymer layer 5.

さらに、液晶ポリマー層5は、ポリフェニレンエーテル系有機物から成る被覆層6との密着性を高めるために、その表面をプラズマ処理を用いて粗化されている。そして、その表面の中心線表面粗さRaが0.05〜5μmの値となるように粗化しておくことが好ましい。中心線表面粗さRaは、半田リフローの際に液晶ポリマー層5と被覆層6との剥離を防止するという観点からは0.05μm以上であることが好ましく、表面に被覆層6を形成する際に空気のかみ込みを防止するという観点からは5μm以下であることが好ましい。従って、液晶ポリマー層5は、その表面を中心線表面粗さRaが0.05〜5μmの粗面とすることが好ましい。   Further, the surface of the liquid crystal polymer layer 5 is roughened by using plasma treatment in order to improve the adhesion with the coating layer 6 made of a polyphenylene ether organic material. And it is preferable to roughen so that the centerline surface roughness Ra of the surface may become a value of 0.05-5 micrometers. The center line surface roughness Ra is preferably 0.05 μm or more from the viewpoint of preventing peeling between the liquid crystal polymer layer 5 and the coating layer 6 at the time of solder reflow, and when the coating layer 6 is formed on the surface. From the viewpoint of preventing air entrapment, it is preferably 5 μm or less. Therefore, the liquid crystal polymer layer 5 preferably has a rough surface with a centerline surface roughness Ra of 0.05 to 5 μm.

次に、液晶ポリマー層5の表面に形成されるポリフェニレンエーテル系有機物から成る被覆層6は、絶縁層1に配線導体2を被着形成する際の接着剤の機能を有するとともに、絶縁層1同志を積層する際の接着剤の役目を果たす。   Next, the coating layer 6 made of a polyphenylene ether-based organic material formed on the surface of the liquid crystal polymer layer 5 has a function of an adhesive when the wiring conductor 2 is formed on the insulating layer 1, and Serves as an adhesive when laminating.

被覆層6は、ポリフェニレンエーテル樹脂やその誘導体、または、これらのポリマーアロイ等のポリフェニレンエーテル系有機物を30〜90体積%含有しており、とりわけ熱サイクル信頼性や積層時の位置精度の観点からは、アリル変性ポリフェニレンエーテル等の熱硬化性ポリフェニレンエーテルを含有することが好ましい。   The coating layer 6 contains 30 to 90% by volume of a polyphenylene ether resin or a derivative thereof, or a polyphenylene ether-based organic material such as a polymer alloy thereof, and particularly from the viewpoint of thermal cycle reliability and positional accuracy during lamination. It is preferable to contain thermosetting polyphenylene ether such as allyl-modified polyphenylene ether.

なお、ポリフェニレンエーテル系有機物の含有量が30体積%未満であると、後述する充填材との混練性が低下する傾向があり、また、90体積%を超えると、液晶ポリマー層5表面に被覆層6を形成する際に、被覆層6の厚みバラツキが大きくなる傾向がある。従って、ポリフェニレンエーテル系有機物の含有量は、30〜90体積%の範囲が好ましい。   If the content of the polyphenylene ether-based organic substance is less than 30% by volume, the kneadability with the filler described later tends to be reduced. If the content exceeds 90% by volume, the surface of the liquid crystal polymer layer 5 is covered with a coating layer. When forming 6, the thickness variation of the coating layer 6 tends to increase. Therefore, the content of the polyphenylene ether organic material is preferably in the range of 30 to 90% by volume.

また、ポリフェニレンエーテル系有機物から成る被覆層6は、液晶ポリマー層5との接着性や配線導体2・貫通導体3との密着性を良好にするという観点からは、重合反応可能な官能基を2個以上有する多官能性モノマーあるいは多官能性重合体等の添加剤を含有することが好ましく、例えば、トリアリルシアヌレートやトリアリルイソシアヌレートおよびこれらの重合体等を含有することが好ましい。   The coating layer 6 made of a polyphenylene ether-based organic substance has 2 functional groups capable of polymerization reaction from the viewpoint of improving the adhesion to the liquid crystal polymer layer 5 and the adhesion to the wiring conductor 2 and the through conductor 3. It is preferable to contain additives such as polyfunctional monomers or polyfunctional polymers having at least one, for example, it is preferable to contain triallyl cyanurate, triallyl isocyanurate, and polymers thereof.

さらに、被覆層6は、弾性率を調整するためのゴム成分や熱安定性を改善するための酸化防止剤、耐光性を改善するための紫外線吸収剤等の光安定剤、難燃性を改善するためのハロゲン系もしくはリン酸系の難燃性剤、アンチモン系化合物やホウ酸亜鉛・メタホウ酸バリウム・酸化ジルコニウム等の難燃助剤、潤滑性を改善するための高級脂肪酸や高級脂肪酸エステルや高級脂肪酸金属塩・フルオロカーボン系界面活性剤等の滑剤、熱膨張係数を調整したり機械的強度を向上するための酸化アルミニウムや酸化珪素・酸化チタン・酸化バリウム・酸化ストロンチウム・酸化ジルコニウム・酸化カルシウム・ゼオライト・窒化珪素・窒化アルミニウム・炭化珪素・チタン酸カリウム・チタン酸バリウム・チタン酸ストロンチウム・チタン酸カルシウム・ホウ酸アルミニウム・スズ酸バリウム・ジルコン酸バリウム・ジルコン酸ストロンチウム等の充填材、あるいは、充填材との親和性を高めこれらの接合性向上と機械的強度を高めるためのシラン系カップリング剤やチタネート系カップリング剤等のカップリング剤を含有してもよい。   Further, the coating layer 6 is a rubber component for adjusting the elastic modulus, an antioxidant for improving the thermal stability, a light stabilizer such as an ultraviolet absorber for improving the light resistance, and improving the flame retardancy. Halogen-based or phosphoric acid-based flame retardants, antimony-based compounds, flame retardant aids such as zinc borate, barium metaborate, and zirconium oxide, higher fatty acids and higher fatty acid esters to improve lubricity, Lubricants such as higher fatty acid metal salts, fluorocarbon surfactants, aluminum oxide, silicon oxide, titanium oxide, barium oxide, strontium oxide, zirconium oxide, calcium oxide for adjusting thermal expansion coefficient and improving mechanical strength Zeolite, silicon nitride, aluminum nitride, silicon carbide, potassium titanate, barium titanate, strontium titanate, calcium titanate Silane coupling agents to improve the bondability and mechanical strength of fillers such as um, aluminum borate, barium stannate, barium zirconate, strontium zirconate, etc. Or a coupling agent such as a titanate coupling agent.

特に絶縁層1を積層しプレスする際に、被覆層6の流動性を抑制し、貫通導体3の位置ずれや被覆層6の厚みばらつきを防止するという観点からは、被覆層6は充填材として10体積%以上の無機絶縁粉末を含有することが好ましい。また、液晶ポリマー層5との接着界面および配線導体2との接着界面での半田リフロー時の剥離を防止するという観点からは、充填材の含有量を70体積%以下とすることが好ましい。従って、ポリフェニレンエーテル系有機物から成る被覆層6に、10〜70体積%の充填材を含有させておくことが好ましい。   In particular, when laminating and pressing the insulating layer 1, the covering layer 6 is used as a filler from the viewpoint of suppressing the fluidity of the covering layer 6 and preventing the displacement of the through conductor 3 and the thickness variation of the covering layer 6. It is preferable to contain 10% by volume or more of inorganic insulating powder. Further, from the viewpoint of preventing peeling at the time of solder reflow at the bonding interface with the liquid crystal polymer layer 5 and the bonding interface with the wiring conductor 2, the content of the filler is preferably 70% by volume or less. Therefore, it is preferable to contain 10 to 70% by volume of the filler in the coating layer 6 made of polyphenylene ether organic material.

なお、上記の充填材等の形状は、略球状・針状・フレーク状等があり、充填性の観点からは、略球状が好ましい。また、粒子径は、0.1〜15μm程度であり、被覆層6の厚みよりも小さい。   In addition, the shape of the filler and the like includes a substantially spherical shape, a needle shape, a flake shape, and the like, and a substantially spherical shape is preferable from the viewpoint of filling properties. The particle diameter is about 0.1 to 15 μm and is smaller than the thickness of the coating layer 6.

本発明の多層配線基板4によれば、液晶ポリマー層5とポリフェニレンエーテル系有機物から成る被覆層6の誘電率とがほぼ等しいことから、積層の際にわずかな厚みばらつきが生じても高周波領域における伝送特性の低下を生じることのない高周波伝送特性に優れた多層配線基板4とすることできる。また、被覆層6が液晶ポリマー層5と同程度の疎水性を示すことから樹脂同士の馴染みが良好であるため接着性に優れるとともに、被覆層6がランダムな分子構造で比較的熱運動しやすい分子から成ることから液晶ポリマー層5表面の微細な凹部に入り込み十分なアンカー効果を発揮することができ、その結果、液晶ポリマー層5と被覆層6との密着性が良好となり高温バイアス試験で絶縁不良が発生することのない耐熱性・絶縁性に優れた多層配線基板4とすることができる。   According to the multilayer wiring board 4 of the present invention, since the dielectric constants of the liquid crystal polymer layer 5 and the coating layer 6 made of polyphenylene ether-based organic substance are substantially equal, even in the case of slight thickness variations during lamination, The multilayer wiring board 4 having excellent high-frequency transmission characteristics without causing deterioration of transmission characteristics can be obtained. In addition, since the covering layer 6 exhibits the same degree of hydrophobicity as the liquid crystal polymer layer 5, the familiarity between the resins is good, so that the adhesiveness is excellent, and the covering layer 6 has a random molecular structure and is relatively easily moved by heat. Since it is composed of molecules, it can enter into the fine recesses on the surface of the liquid crystal polymer layer 5 and exert a sufficient anchor effect. As a result, the adhesion between the liquid crystal polymer layer 5 and the coating layer 6 is improved, and insulation is performed in a high temperature bias test. The multilayer wiring board 4 having excellent heat resistance and insulation without causing defects can be obtained.

このような絶縁層1は、例えば粒径が0.1〜15μm程度の酸化珪素等の無機絶縁粉末に、熱硬化性ポリフェニレンエーテル樹脂と溶剤・可塑剤・分散剤等を添加して得たペーストを液晶ポリマー層5の上下表面に従来周知のドクタブレード法等のシート成型法を採用して被覆層6を形成した後、あるいは上記のペースト中に液晶ポリマー層5を浸漬し垂直に引き上げることによって液晶ポリマー層5の表面に被覆層6を形成した後、これを60〜100℃の温度で5分〜3時間加熱・乾燥することにより製作される。   Such an insulating layer 1 is a liquid crystal obtained by adding a thermosetting polyphenylene ether resin and a solvent / plasticizer / dispersant to an inorganic insulating powder such as silicon oxide having a particle size of about 0.1 to 15 μm. After forming the coating layer 6 on the upper and lower surfaces of the polymer layer 5 by using a conventionally known sheet molding method such as a doctor blade method, or by immersing the liquid crystal polymer layer 5 in the above paste and pulling it up vertically, the liquid crystal polymer After the coating layer 6 is formed on the surface of the layer 5, it is manufactured by heating and drying at a temperature of 60 to 100 ° C. for 5 minutes to 3 hours.

なお、絶縁層1の厚みは絶縁信頼性を確保するという観点からは10〜200μmであることが好ましく、また、高耐熱性・低吸湿性・高寸法安定性を確保するという観点からは、液晶ポリマー層5の厚みを絶縁層1の厚みの40〜90%の範囲としておくことが好ましい。   The thickness of the insulating layer 1 is preferably 10 to 200 μm from the viewpoint of ensuring insulation reliability, and from the viewpoint of ensuring high heat resistance, low moisture absorption and high dimensional stability, liquid crystal It is preferable that the thickness of the polymer layer 5 is in the range of 40 to 90% of the thickness of the insulating layer 1.

また、絶縁層1には、上下面の少なくとも1つの面に配線導体2が被着形成されている。配線導体2は、その厚みが2〜30μm程度で銅・金等の良導電性の金属箔から成り、多層配線基板4に搭載される電子部品7を外部電気回路(図示せず)に電気的に接続する機能を有する。   In addition, a wiring conductor 2 is formed on the insulating layer 1 on at least one of the upper and lower surfaces. The wiring conductor 2 has a thickness of about 2 to 30 μm and is made of a highly conductive metal foil such as copper and gold. The electronic component 7 mounted on the multilayer wiring board 4 is electrically connected to an external electric circuit (not shown). It has a function to connect to.

このような配線導体2は、絶縁層1を複数層積層する際、配線導体2の周囲にボイドが発生するのを防止するという観点から、被覆層6に少なくとも配線導体2の表面と被覆層6の表面とが平坦となるように埋設されていることが好ましい。また、配線導体2を被覆層6に埋設する際に、被覆層6の乾燥状態での気孔率を3〜40体積%としておくと、配線導体2周囲の被覆層6の樹脂盛り上がりを生じさせず平坦化することができるとともに配線導体2と被覆層6の間に挟まれる空気の排出を容易にして気泡の巻き込みを防止することができる。なお、乾燥状態での気孔率が40体積%を超えると、複数層積層した絶縁層1を加圧・加熱硬化した後に、被覆層6内に気孔が残存し、この気孔が空気中の水分を吸着して絶縁性が低下してしまうおそれがあるので、被覆層6の乾燥状態での気孔率を3〜40体積%の範囲としておくことが好ましい。   Such a wiring conductor 2 has at least the surface of the wiring conductor 2 and the coating layer 6 in the covering layer 6 from the viewpoint of preventing voids from being generated around the wiring conductor 2 when the insulating layer 1 is laminated in a plurality of layers. It is preferably embedded so that the surface thereof is flat. Further, when the wiring conductor 2 is embedded in the coating layer 6, if the porosity of the coating layer 6 in the dry state is 3 to 40% by volume, the resin swell of the coating layer 6 around the wiring conductor 2 does not occur. In addition to being able to flatten, it is possible to easily discharge the air sandwiched between the wiring conductor 2 and the covering layer 6 and prevent entrainment of bubbles. When the porosity in the dry state exceeds 40% by volume, after the insulating layer 1 laminated in plural layers is pressurized and heat-cured, pores remain in the coating layer 6, and the pores remove moisture in the air. Since it may be adsorbed and the insulating property may be lowered, the porosity of the coating layer 6 in the dry state is preferably set in the range of 3 to 40% by volume.

このような被覆層6の乾燥状態での気孔率は、被覆層6を液晶ポリマー層5の表面上に塗布し乾燥する際に、乾燥温度や昇温速度等の乾燥条件を適宜調整することにより気孔率を所望の値とすることができる。   The porosity of the coating layer 6 in the dry state can be determined by appropriately adjusting the drying conditions such as the drying temperature and the heating rate when the coating layer 6 is applied on the surface of the liquid crystal polymer layer 5 and dried. The porosity can be set to a desired value.

また、配線導体2と液晶ポリマー層5の間に位置する被覆層6の厚みを3〜35μmの厚みとしておくことが好ましい。配線導体2と液晶ポリマー層5の間に位置する被覆層6の厚みを3〜35μmの厚みとして、配線導体2と誘電正接の低い液晶ポリマー層5とを近づけることにより、配線導体2周囲の誘電正接を低くすることができ、その結果、高周波領域、特に100MHz以上の周波数領域における伝送特性を向上させることができる。なお、被覆層6の厚みが3μm未満であると、配線導体2の熱膨張・熱収縮により発生する応力を被覆層6で有効に緩和することができず、配線導体2のコーナー部からクラックが発生してしまう傾向があり、35μmを超えると配線導体2周囲の誘電正接を低くする効果が低下してしまう傾向がある。従って、配線導体2と液晶ポリマー層5の間に位置する被覆層6の厚みを3〜35μmの範囲としておくことが好ましい。   Moreover, it is preferable to make the thickness of the coating layer 6 located between the wiring conductor 2 and the liquid crystal polymer layer 5 into a thickness of 3 to 35 μm. The thickness of the coating layer 6 positioned between the wiring conductor 2 and the liquid crystal polymer layer 5 is set to 3 to 35 μm, and the wiring conductor 2 and the liquid crystal polymer layer 5 having a low dielectric loss tangent are brought close to each other, whereby the dielectric around the wiring conductor 2 is increased. The tangent can be lowered, and as a result, transmission characteristics in a high frequency region, particularly in a frequency region of 100 MHz or higher can be improved. If the thickness of the coating layer 6 is less than 3 μm, the stress generated by the thermal expansion / contraction of the wiring conductor 2 cannot be effectively reduced by the coating layer 6, and cracks are generated from the corners of the wiring conductor 2. When the thickness exceeds 35 μm, the effect of lowering the dielectric loss tangent around the wiring conductor 2 tends to be reduced. Therefore, it is preferable to set the thickness of the coating layer 6 located between the wiring conductor 2 and the liquid crystal polymer layer 5 in the range of 3 to 35 μm.

さらに、絶縁層1に配設された配線導体2の幅方向の断面形状を、絶縁層1側の底辺の長さが対向する底辺の長さよりも短い台形状とするとともに、絶縁層1側の底辺と側辺との成す角度を95〜150°とすることが好ましい。絶縁層1に配設された配線導体2の幅方向の断面形状を、絶縁層1側の底辺の長さが対向する底辺の長さよりも短い台形状とするとともに、絶縁層1側の底辺と側辺との成す角度を95〜150°とすることにより、配線導体2を被覆層6に埋設する際に、配線導体2を被覆層6に容易に埋設することができる。なお、気泡をかみ込むことなく埋設するという観点からは、絶縁層1側の底辺と側辺との成す角度を95°以上とすることが好ましく、配線導体2を微細化するという観点からは150°以下とすることが好ましい。   Furthermore, the cross-sectional shape in the width direction of the wiring conductor 2 disposed in the insulating layer 1 is a trapezoid whose base side on the insulating layer 1 side is shorter than the opposing base side, and The angle formed between the bottom side and the side side is preferably 95 to 150 °. The cross-sectional shape in the width direction of the wiring conductor 2 disposed in the insulating layer 1 is a trapezoid in which the length of the base on the insulating layer 1 side is shorter than the length of the opposing base, and the base on the insulating layer 1 side By setting the angle formed with the side to 95 to 150 °, the wiring conductor 2 can be easily embedded in the covering layer 6 when the wiring conductor 2 is embedded in the covering layer 6. From the viewpoint of embedding without entrapment of bubbles, it is preferable that the angle formed between the bottom and the side on the insulating layer 1 side is 95 ° or more, and from the viewpoint of miniaturizing the wiring conductor 2. It is preferable to set it to 0 ° or less.

また、絶縁層1の層間において、配線導体2の長さの短い底辺と液晶ポリマー層5との間に位置する被覆層6の厚みx(μm)が、上下の液晶ポリマー層5間の距離をT(μm)、配線導体2の厚みをt(μm)としたときに、3μm≦0.5T−t≦x≦0.5T≦35μm(ただし、8μm≦T≦70μm、1μm≦t≦32μm)であることが好ましい。   In addition, the thickness x (μm) of the covering layer 6 positioned between the short base of the wiring conductor 2 and the liquid crystal polymer layer 5 between the insulating layers 1 determines the distance between the upper and lower liquid crystal polymer layers 5. When T (μm) and the thickness of the wiring conductor 2 are t (μm), 3 μm ≦ 0.5 T−t ≦ x ≦ 0.5 T ≦ 35 μm (however, 8 μm ≦ T ≦ 70 μm, 1 μm ≦ t ≦ 32 μm). It is preferable.

液晶ポリマー層6間の距離をT(μm)、配線導体2の厚みをt(μm)としたときに、配線導体2の長さの短い底辺と液晶ポリマー層5間のポリフェニレンエーテル系有機物から成る被覆層6の厚みx(μm)を3μm≦0.5T−t≦x≦0.5T≦35μmとすることにより、配線導体2の長さの短い底辺と液晶ポリマー層5間の距離および配線導体2の長さの長い底辺と隣接する液晶ポリマー層5間の距離の差をt(μm)未満と小さくでき、配線導体2周囲の誘電正接バラツキを小さなものとすることができ、その結果、伝送特性が低下することを防止できる。従って、配線導体2の台形状の上底側表面と液晶ポリマー層5の間に位置する、ポリフェニレンエーテル系有機物から成る被覆層6の厚みx(μm)を、液晶ポリマー層6間の距離をT(μm)、配線導体2の厚みをt(μm)としたときに、3μm≦0.5T−t≦x≦0.5T≦35μmの範囲とすることが好ましい。   When the distance between the liquid crystal polymer layers 6 is T (μm) and the thickness of the wiring conductor 2 is t (μm), the wiring conductor 2 is made of a polyphenylene ether organic material between the short bottom of the wiring conductor 2 and the liquid crystal polymer layer 5. By setting the thickness x (μm) of the covering layer 6 to 3 μm ≦ 0.5 T−t ≦ x ≦ 0.5 T ≦ 35 μm, the distance between the short bottom of the wiring conductor 2 and the liquid crystal polymer layer 5 and the wiring conductor 2 The difference in distance between the long base and the adjacent liquid crystal polymer layer 5 can be reduced to less than t (μm), and the dielectric tangent variation around the wiring conductor 2 can be reduced. It can be prevented from decreasing. Therefore, the thickness x (μm) of the coating layer 6 made of a polyphenylene ether-based organic material, which is located between the trapezoidal upper bottom surface of the wiring conductor 2 and the liquid crystal polymer layer 5, and the distance between the liquid crystal polymer layers 6 as T (Μm) When the thickness of the wiring conductor 2 is t (μm), the range of 3 μm ≦ 0.5 T−t ≦ x ≦ 0.5 T ≦ 35 μm is preferable.

このような配線導体2は、絶縁層1となる前駆体シートに、公知のフォトレジストを用いたサブトラクティブ法によりパターン形成した例えば銅から成る金属箔を転写法等により被着形成することにより形成される。先ず、支持体と成るフィルム上に銅から成る金属箔を接着剤を介して接着した金属箔転写用フィルムを用意し、次に、フィルム上の金属箔を公知のフォトレジストを用いたサブトラクティブ法を使用してパターン状にエッチングする。この時、パターンの表面側の側面は、フィルム側の側面に較べてエッチング液に接する時間が長いためにエッチングされやすく、パターンの幅方向の断面形状を台形状とすることができる。なお、台形の形状は、エッチング液の濃度やエッチング時間を調整することにより短い底辺と側辺とのなす角度を95〜150°の台形状とすることができる。そして、この金属箔転写用フィルムを絶縁層1と成る前駆体シートに積層し、温度が100〜200℃で圧力が0.5〜10MPaの条件で10分〜1時間ホットプレスした後、支持体と成るフィルムを剥離除去して金属箔を絶縁層1と成る前駆体シート表面に転写させることにより、台形状の上底側がポリフェニレンエーテル系有機物から成る被覆層6に埋設された配線導体2を形成することができる。   Such a wiring conductor 2 is formed by depositing, for example, a metal foil made of copper, which is patterned by a subtractive method using a known photoresist, on the precursor sheet to be the insulating layer 1 by a transfer method or the like. Is done. First, a metal foil transfer film in which a metal foil made of copper is bonded to a support film with an adhesive is prepared, and then the metal foil on the film is subtractive using a known photoresist. Is used to etch into a pattern. At this time, the side surface on the surface side of the pattern is easily etched because it takes a longer time to contact the etching solution than the side surface on the film side, and the cross-sectional shape in the width direction of the pattern can be trapezoidal. The trapezoidal shape can be a trapezoid whose angle between the short base and the side is 95 to 150 ° by adjusting the concentration of the etching solution and the etching time. And this metal foil transfer film is laminated | stacked on the precursor sheet | seat used as the insulating layer 1, and it becomes a support body after hot-pressing for 10 minutes to 1 hour on the conditions whose temperature is 100-200 degreeC and a pressure is 0.5-10 MPa. The wiring conductor 2 in which the upper base side of the trapezoidal shape is embedded in the coating layer 6 made of a polyphenylene ether-based organic material is formed by peeling and removing the film and transferring the metal foil to the surface of the precursor sheet to be the insulating layer 1 Can do.

なお、配線導体2の長さの短い底辺と対向する液晶ポリマー層5間の被覆層6の厚みx(μm)は、金属箔転写時のホットプレスの圧力を調整することにより3〜35μmの範囲とすることができる。また、配線導体2は被覆層6との密着性を高めるためにその表面にバフ研磨・ブラスト研磨・ブラシ研磨・薬品処理等の処理で表面を粗化しておくことが好ましい。   The thickness x (μm) of the coating layer 6 between the liquid crystal polymer layer 5 facing the short base of the wiring conductor 2 is in the range of 3 to 35 μm by adjusting the hot press pressure during metal foil transfer. It can be. Further, in order to improve the adhesion to the coating layer 6, the surface of the wiring conductor 2 is preferably roughened by a process such as buffing, blasting, brushing, or chemical treatment.

また、絶縁層1には、直径が20〜150μm程度の貫通導体3が形成されている。貫通導体3は、絶縁層を挟んで上下に位置する配線導体2を電気的に接続する機能を有し、絶縁層1にレーザにより穿設加工を施すことにより貫通孔を形成した後、この貫通孔に銅・銀・金・半田等から成る導電性ペーストを従来周知のスクリーン印刷法により埋め込むことにより形成される。   A through conductor 3 having a diameter of about 20 to 150 μm is formed in the insulating layer 1. The through conductor 3 has a function of electrically connecting the wiring conductors 2 positioned above and below with the insulating layer interposed therebetween. After the through hole is formed by drilling the insulating layer 1 with a laser, the through conductor 3 The hole is formed by embedding a conductive paste made of copper, silver, gold, solder, or the like by a well-known screen printing method.

本発明の多層配線基板4によれば、絶縁層1を液晶ポリマー層5の上下面にポリフェニレンエーテル系有機物から成る被覆層6を有したものとしたことから、液晶ポリマー層5が高耐熱性・高弾性率・高寸法安定性・低吸湿性であり、ガラスクロスのような強化材を用いなくとも絶縁層1を構成することが可能となり、その結果、レーザによる穿設加工が容易となり微細で均一な貫通孔を形成できる。   According to the multilayer wiring board 4 of the present invention, since the insulating layer 1 has the coating layers 6 made of polyphenylene ether organic material on the upper and lower surfaces of the liquid crystal polymer layer 5, the liquid crystal polymer layer 5 has high heat resistance, High elastic modulus, high dimensional stability, and low hygroscopicity make it possible to construct the insulating layer 1 without using a reinforcing material such as glass cloth. As a result, laser drilling is easy and fine. Uniform through holes can be formed.

このような多層配線基板4は、上述したような方法で製作した絶縁層1と成る前駆体シートの所望の位置に貫通導体3を形成した後、パターン形成した例えば銅の金属箔を、温度が100〜200℃で圧力が0.5〜10MPaの条件で10分〜1時間ホットプレスして転写し、これらを積層して最終的に温度が150〜300℃で圧力が0.5〜10MPaの条件で30分〜24時間ホットプレスして完全硬化させることにより製作される。   In such a multilayer wiring board 4, the through conductor 3 is formed at a desired position of the precursor sheet to be the insulating layer 1 manufactured by the method as described above, and then the patterned metal foil of copper, for example, is heated. It is transferred by hot pressing for 10 minutes to 1 hour at 100 to 200 ° C. under a pressure of 0.5 to 10 MPa, and these are laminated and finally 30 minutes under a temperature of 150 to 300 ° C. and a pressure of 0.5 to 10 MPa. Manufactured by hot pressing for 24 hours to complete curing.

かくして、本発明の多層配線基板4によれば、絶縁層1を液晶ポリマー層5の表面にポリフェニレンエーテル系有機物から成る被覆層6を有したものとしたことから、高周波伝送特性に優れるとともに耐湿性・半田耐熱性・絶縁性に優れた多層配線基板4とすることができる。   Thus, according to the multilayer wiring board 4 of the present invention, since the insulating layer 1 has the coating layer 6 made of polyphenylene ether-based organic material on the surface of the liquid crystal polymer layer 5, it has excellent high frequency transmission characteristics and moisture resistance. -It can be set as the multilayer wiring board 4 excellent in solder heat resistance and insulation.

なお、本発明の多層配線基板4は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では4層の絶縁層1を積層することによって多層配線基板4を製作したが、2層や3層、あるいは5層以上の絶縁層1を積層して多層配線基板4を製作してもよい。また、本発明の多層配線基板4の上下表面に、1層や2層、あるいは3層以上の有機樹脂を主成分とする絶縁層から成るビルドアップ層やソルダーレジスト層を形成してもよい。   The multilayer wiring board 4 of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, four layers are possible. The multilayer wiring board 4 is manufactured by laminating the insulating layers 1, but the multilayer wiring board 4 may be fabricated by laminating two, three, or five or more insulating layers 1. In addition, a build-up layer or a solder resist layer made of an insulating layer mainly composed of one, two, or three or more organic resins may be formed on the upper and lower surfaces of the multilayer wiring board 4 of the present invention.

次に本発明の多層配線基板を、以下のサンプルを製作して評価した。   Next, the multilayer wiring board of the present invention was evaluated by producing the following samples.

(実施例)先ず、熱硬化性ポリフェニレンエーテル樹脂に平均粒径が0.6μmの球状溶融シリカをその含有量が40体積%となるように加え、これに溶剤としてトルエン、さらに有機樹脂の硬化を促進させるための触媒を添加し、1時間混合してワニスを調整した。 (Example) First, spherical fused silica having an average particle size of 0.6 μm is added to a thermosetting polyphenylene ether resin so that the content thereof becomes 40% by volume, and toluene as a solvent is further promoted to cure organic resin. The catalyst for adding was added and mixed for 1 hour to prepare a varnish.

次に、融点が320℃の液晶ポリマー層の表面をプラズマ処理して厚さが35μmで中心線表面粗さRaが0.10μmの液晶ポリマー層を用意し、この液晶ポリマー層の上面に上記ワニスをドクターブレード法により塗布し、厚さ約20μmの乾燥状態の熱硬化性ポリフェニレンエーテル被覆層を成形した。そして、この液晶ポリマー層の下面にも同様にポリフェニレンエーテル被覆層を成形し、絶縁層となる前駆体シートを製作した。   Next, plasma treatment is performed on the surface of the liquid crystal polymer layer having a melting point of 320 ° C. to prepare a liquid crystal polymer layer having a thickness of 35 μm and a centerline surface roughness Ra of 0.10 μm. The varnish is applied to the upper surface of the liquid crystal polymer layer. It was applied by a doctor blade method to form a dried thermosetting polyphenylene ether coating layer having a thickness of about 20 μm. And the polyphenylene ether coating layer was similarly shape | molded also to the lower surface of this liquid crystal polymer layer, and the precursor sheet | seat used as an insulating layer was manufactured.

さらに、この前駆体シートに、CO2レーザにより直径65μmの貫通孔を形成し、この貫通孔に銅粉末と有機バインダを含有する導体ペーストをスクリーン印刷により埋め込むことにより貫通導体を形成した。   Further, a through-hole having a diameter of 65 μm was formed in this precursor sheet by a CO2 laser, and a through-conductor was formed by embedding a conductive paste containing copper powder and an organic binder in the through-hole by screen printing.

次に、回路状に形成した厚さ12μmの銅箔が付いた転写用支持フィルムと、貫通導体が形成された絶縁層となる前駆体シートとを位置合わせして真空積層機により3MPaの圧力で30秒加圧した後、転写用支持フィルムを剥離して配線導体を前駆体シート上に埋設した。   Next, a transfer support film with a 12 μm thick copper foil formed in a circuit shape and a precursor sheet serving as an insulating layer on which a through conductor is formed are aligned with a pressure of 3 MPa by a vacuum laminator. After pressurizing for 30 seconds, the transfer support film was peeled off, and the wiring conductor was embedded on the precursor sheet.

最後に、この配線導体が形成された前駆体シートを4枚重ね合わせ、3MPaの圧力下で200℃の温度で5時間加熱処理して完全硬化させて多層配線基板を得た。   Finally, four precursor sheets on which the wiring conductors were formed were stacked and heat-treated at a temperature of 200 ° C. for 5 hours under a pressure of 3 MPa to be completely cured to obtain a multilayer wiring board.

なお、絶縁性の評価を行うためのテスト基板は、配線幅50μm、配線間隔50μmの櫛歯状パターンの配線導体を多層配線基板内に形成し、また、伝送特性の評価を行うためのテスト基板は、ストリップライン構造の配線導体を多層配線基板内部に形成した。   In addition, the test board for evaluating insulation is a test board for forming a comb-like pattern wiring conductor with a wiring width of 50 μm and a wiring interval of 50 μm in a multilayer wiring board, and for evaluating transmission characteristics. Has formed a wiring conductor having a stripline structure inside a multilayer wiring board.

(比較例1)比較例1用として用いた多層配線基板は、まず、表面に銅箔を熱溶融により接着した融点が320℃の液晶ポリマー層にフォトレジストを用いて回路状の配線導体を形成し、次に、CO2レーザにより直径65μmの貫通孔を形成し、さらにこの貫通孔に銅粉末と有機バインダを含有する導体ペーストをスクリーン印刷により埋め込むことにより貫通導体を形成して回路基板を作成した後、これらの回路基板を融点が280℃の液晶ポリマー層を間に挟んで1MPaの圧力下で285℃の温度で5分間加熱プレスすることにより製作した。   (Comparative Example 1) The multilayer wiring board used for Comparative Example 1 was formed by first forming a circuit-like wiring conductor using a photoresist on a liquid crystal polymer layer having a melting point of 320 ° C. with a copper foil bonded to the surface by heat melting. Next, a through hole having a diameter of 65 μm was formed by a CO2 laser, and a through conductor was formed by embedding a conductive paste containing copper powder and an organic binder in the through hole by screen printing, thereby creating a circuit board. Thereafter, these circuit boards were manufactured by hot pressing at a temperature of 285 ° C. for 5 minutes under a pressure of 1 MPa with a liquid crystal polymer layer having a melting point of 280 ° C. therebetween.

(比較例2)比較例2用として用いた多層配線基板は、表面に銅箔をエポキシ樹脂製接着剤を介して接着した、融点が320℃の液晶ポリマー層を用いること以外は、比較例1用の多層配線基板と同様の方法で製作した。   (Comparative Example 2) The multilayer wiring board used for Comparative Example 2 is Comparative Example 1 except that a liquid crystal polymer layer having a melting point of 320 ° C. and having a copper foil bonded to the surface via an epoxy resin adhesive is used. It was manufactured by the same method as the multilayer wiring board.

絶縁性の評価は、試料を温度が130℃、相対湿度が85%の条件で、印加電圧5.5Vの高温バイアス試験を行い、168時間後の配線導体間の絶縁抵抗を測定し、試験前後の変化量を比較することにより評価した。また、伝送特性の評価は、ストリップ構造を有する試料を用いて、周波数が100MHz〜40GHzの範囲で伝送特性を測定することにより評価した。   The insulation was evaluated by performing a high-temperature bias test with an applied voltage of 5.5 V under the conditions of a temperature of 130 ° C. and a relative humidity of 85%, measuring the insulation resistance between the wiring conductors after 168 hours, and before and after the test. Evaluation was made by comparing the amount of change. The transmission characteristics were evaluated by measuring the transmission characteristics in a frequency range of 100 MHz to 40 GHz using a sample having a strip structure.

表1に絶縁性の評価結果を、表2に伝送特性の評価結果を示す。

Figure 2006191145
Table 1 shows the insulation evaluation results, and Table 2 shows the transmission characteristic evaluation results.
Figure 2006191145

Figure 2006191145
Figure 2006191145

表1からは、比較例1の多層配線基板が高温バイアス試験後の絶縁抵抗が3.5×106Ωと小さくなり、耐熱性に劣ることがわかった。また、表2からは、比較例2の多層配線基板が20GHz以上の高周波領域で伝送特性が-1.0dB以下と劣化し、高周波伝送特性に劣ることがわかった。 From Table 1, it was found that the multilayer wiring board of Comparative Example 1 had a low insulation resistance of 3.5 × 10 6 Ω after the high temperature bias test and was inferior in heat resistance. Further, from Table 2, it was found that the multilayer wiring board of Comparative Example 2 deteriorated to have a transmission characteristic of −1.0 dB or less in a high frequency region of 20 GHz or higher, and inferior to the high frequency transmission characteristics.

それらに対して本発明の多層配線基板は、高温バイアス試験後でも絶縁抵抗は4.3×1010Ωと大きく、また、伝送特性も40GHzの高周波領域においても‐0.51dBと小さいという優れたものであった。 In contrast, the multilayer wiring board of the present invention has an excellent insulation resistance of 4.3 × 10 10 Ω even after a high-temperature bias test, and a transmission characteristic as low as −0.51 dB even in a high frequency region of 40 GHz. It was.

本発明の多層配線基板に半導体素子を搭載して成る混成集積回路の実施の形態の一例を示す断面図である。It is sectional drawing which shows an example of embodiment of the hybrid integrated circuit formed by mounting a semiconductor element on the multilayer wiring board of this invention. 本発明の多層配線基板の要部断面図である。It is principal part sectional drawing of the multilayer wiring board of this invention.

符号の説明Explanation of symbols

1・・・・・絶縁層
2・・・・・配線導体
3・・・・・貫通導体
4・・・・・多層配線基板
5・・・・・液晶ポリマー層
6・・・・・ポリフェニレンエーテル系有機物から成る被覆層
T・・・・・液晶ポリマー層間の距離
t・・・・・配線導体の厚み
x・・・・・台形状の配線導体の上底側表面と液晶ポリマー層の間に位置する、ポリフェニレンエーテル系有機物から成る被覆層の厚み
DESCRIPTION OF SYMBOLS 1 ... Insulating layer 2 ... Wiring conductor 3 ... Through-conductor 4 ... Multilayer wiring board 5 ... Liquid crystal polymer layer 6 ... Polyphenylene ether Coating layer T made of organic organic material: distance t between liquid crystal polymer layers: thickness of wiring conductor x: between the upper bottom surface of the trapezoidal wiring conductor and the liquid crystal polymer layer The thickness of the coating layer made of polyphenylene ether organic material

Claims (7)

有機材料から成り、上下面の少なくとも1つの面に金属箔から成る配線導体が配設された複数の絶縁層を積層して成るとともに、該絶縁層を挟んで上下に位置する前記配線導体間を前記絶縁層に形成された貫通導体を介して電気的に接続した多層配線基板であって、前記絶縁層は、表面がプラズマ処理された液晶ポリマー層の上下面にポリフェニレンエーテル系有機物から成る被覆層を形成して成ることを特徴とする多層配線基板。 A plurality of insulating layers made of an organic material and laminated with wiring conductors made of metal foil on at least one of the upper and lower surfaces, and between the wiring conductors positioned above and below the insulating layer A multilayer wiring board electrically connected through a through conductor formed in the insulating layer, wherein the insulating layer is a coating layer made of a polyphenylene ether-based organic material on the upper and lower surfaces of a liquid crystal polymer layer whose surface is plasma-treated. A multilayer wiring board characterized by comprising: 前記液晶ポリマー層の上下面を中心線表面粗さRaが0.05〜5μmの粗面としたことを特徴とする請求項1記載の多層配線基板。 2. The multilayer wiring board according to claim 1, wherein the upper and lower surfaces of the liquid crystal polymer layer are rough surfaces having a center line surface roughness Ra of 0.05 to 5 [mu] m. 前記被覆層が10〜70体積%の無機絶縁粉末を含有することを特徴とする請求項1または請求項2記載の多層配線基板。 The multilayer wiring board according to claim 1, wherein the coating layer contains 10 to 70% by volume of an inorganic insulating powder. 前記ポリフェニレンエーテル系有機物が熱硬化性ポリフェニレンエーテルであることを特徴とする請求項1乃至請求項3のいずれかに記載の多層配線基板。 4. The multilayer wiring board according to claim 1, wherein the polyphenylene ether-based organic material is a thermosetting polyphenylene ether. 前記液晶ポリマー層と前記配線導体との間に位置する前記被覆層の厚みが3〜35μmであることを特徴とする請求項1乃至請求項4のいずれかに記載の多層配線基板。 The multilayer wiring board according to any one of claims 1 to 4, wherein a thickness of the coating layer located between the liquid crystal polymer layer and the wiring conductor is 3 to 35 µm. 前記絶縁層に配設された配線導体の幅方向の断面形状は、前記絶縁層側の底辺の長さが対向する底辺の長さよりも短い台形状であり、かつ、前記絶縁層側の底辺と側辺との成す角度が95〜150°であることを特徴とする請求項1乃至請求項5のいずれかに記載の多層配線基板。 The cross-sectional shape in the width direction of the wiring conductor disposed in the insulating layer is a trapezoid in which the length of the base on the insulating layer side is shorter than the length of the opposing base, and the base on the insulating layer side 6. The multilayer wiring board according to claim 1, wherein an angle formed with the side is 95 to 150 degrees. 前記絶縁層の層間において、前記配線導体の長さの短い底辺と前記液晶ポリマー層との間に位置する前記被覆層の厚みx(μm)が、上下の前記液晶ポリマー層間の距離をT(μm)、前記配線導体の厚みをt(μm)としたときに、3μm≦0.5T−t≦x≦0.5T≦35μm(ただし、8μm≦T≦70μm、1μm≦t≦32μm)であることを特徴とする請求項6記載の多層配線基板。

Between the insulating layers, the thickness x (μm) of the coating layer located between the bottom of the wiring conductor having a short length and the liquid crystal polymer layer indicates that the distance between the upper and lower liquid crystal polymer layers is T (μm). ) When the thickness of the wiring conductor is t (μm), 3 μm ≦ 0.5 T−t ≦ x ≦ 0.5 T ≦ 35 μm (however, 8 μm ≦ T ≦ 70 μm, 1 μm ≦ t ≦ 32 μm) The multilayer wiring board according to claim 6.

JP2006076654A 2006-03-20 2006-03-20 Multilayer wiring board Withdrawn JP2006191145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006076654A JP2006191145A (en) 2006-03-20 2006-03-20 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006076654A JP2006191145A (en) 2006-03-20 2006-03-20 Multilayer wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2001053834A Division JP2002261453A (en) 2001-02-28 2001-02-28 Multilayer interconnection board

Publications (1)

Publication Number Publication Date
JP2006191145A true JP2006191145A (en) 2006-07-20

Family

ID=36797893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006076654A Withdrawn JP2006191145A (en) 2006-03-20 2006-03-20 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2006191145A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014046014A1 (en) * 2012-09-20 2014-03-27 株式会社クラレ Circuit board and method for manufacturing same
JP2020013977A (en) * 2018-07-16 2020-01-23 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board
US11051398B2 (en) 2016-08-10 2021-06-29 Murata Manufacturing Co., Ltd. Ceramic electronic component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014046014A1 (en) * 2012-09-20 2014-03-27 株式会社クラレ Circuit board and method for manufacturing same
KR20150058352A (en) 2012-09-20 2015-05-28 가부시키가이샤 구라레 Circuit board and method for manufacturing same
US9439303B2 (en) 2012-09-20 2016-09-06 Kuraray Co., Ltd. Circuit board and method for manufacturing same
US11051398B2 (en) 2016-08-10 2021-06-29 Murata Manufacturing Co., Ltd. Ceramic electronic component
JP2020013977A (en) * 2018-07-16 2020-01-23 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board

Similar Documents

Publication Publication Date Title
JP2005072328A (en) Multilayer wiring board
JP2006191145A (en) Multilayer wiring board
JP4462872B2 (en) Wiring board and manufacturing method thereof
JP2002261453A (en) Multilayer interconnection board
JP4025695B2 (en) Insulating layer with protective film and method for producing wiring board
JP4959066B2 (en) Insulating film and multilayer wiring board using the same
JP2006191146A (en) Method of manufacturing multilayer wiring board
JP3694673B2 (en) Insulating film and multilayer wiring board using the same
JP3872360B2 (en) Multilayer wiring board
JP2003069237A (en) Insulation film and multilayer interconnection board using the same
JP3878832B2 (en) Multilayer wiring board
JP2004179011A (en) Insulating film and multilayer wiring board using this
JP2003174264A (en) Insulation film and multilayer wiring substrate employing the same
JP2002290055A (en) Multilayer wiring board
JP2005050877A (en) Wiring board
JP2003062942A (en) Insulating film and multilayered wiring board using the same
JP2004322482A (en) Insulating film and multi-layer wiring board using the film
JP2002324978A (en) Multilayer wiring board
JP2003039602A (en) Insulating film and multilayered wiring board
JP2003347454A (en) Multilayer wiring board
JP4508472B2 (en) Multilayer wiring board
JP2004082554A (en) Insulating film and multilayer printed circuit board using the same
JP2003159768A (en) Insulation film and multilayer wiring board using the same
JP2003046259A (en) Multilayer interconnection board
JP4508498B2 (en) Multilayer wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061117

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20090327