JP2006190739A - Solid state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make electrical characteristics of a source contact uniform. <P>SOLUTION: The solid state imaging device including a photoelectric conversion element and a transistor formed contiguously thereto comprises a substrate, first diffusion layers 21 and 21' formed on the substrate in a region for forming the photoelectric conversion element and the transistor, a second diffusion layer 4 formed on the first diffusion layer in a region for forming the photoelectric conversion element, a third diffusion layer 5 formed on the first diffusion layer in a region for forming the transistor continuously to the second diffusion layer, an annular gate electrode 6 formed on the substrate above the third diffusion layer and having an opening, a source region 7 formed on the substrate below the opening, a contact layer 9 formed of a conductive material on the surface of the substrate in the source region, an insulating film 41 formed on the substrate including the gate electrode and the contact layer, and a conductive material 43 formed in a contact hole opened in the insulating film above the contact layer in contact therewith. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device having excellent electrical characteristics and a method for manufacturing the same.

  As a solid-state imaging device mounted on a cellular phone or the like, there are a CCD (charge coupled device) type image sensor and a CMOS type image sensor. A CCD type image sensor has excellent image quality, and a CMOS type image sensor has low power consumption and low process cost. In recent years, a MOS type solid-state imaging device of a threshold voltage modulation method that has both high image quality and low power consumption has been proposed. A threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Patent Document 1.

  The image sensor obtains an image output by arranging sensor cells in a matrix and repeating three states of initialization, accumulation, and readout. In the image sensor disclosed in Patent Document 1, each unit pixel includes a light receiving diode for performing accumulation and a transistor for performing readout.

  FIG. 11 is a schematic cross-sectional view showing the image sensor disclosed in Patent Document 1. As shown in FIG.

  In the image sensor of FIG. 11, a light receiving diode 111 and an insulated gate field effect transistor 112 are arranged adjacent to each other on a substrate 100 for each unit pixel. The gate electrode 113 of the transistor 112 is formed in a ring shape, and a source region 114 is formed in the central opening of the gate electrode 113. A drain region 115 is formed around the gate electrode 113.

  Charges (photogenerated charges) generated by light incident from the opening region of the light receiving diode 111 are transferred to the P-type well region 116 below the gate electrode 113 and accumulated in the carrier pocket 117 formed in this portion. . The threshold voltage of the transistor 112 is changed by the photo-generated charges accumulated in the carrier pocket 117. Accordingly, a signal (pixel signal) corresponding to incident light can be extracted from the source region 114 of the transistor 112.

An interlayer insulating film (not shown) is formed on the substrate including the ring-shaped gate electrode 113, and a wiring layer or the like is formed on the interlayer insulating film. The wiring layer and the source region 114 are electrically connected through a contact hole provided in the interlayer insulating film. In general, for example, in a contact hole, a film having a two-layer structure of titanium and titanium nitride is first formed. The contact hole on the titanium nitride is filled with tungsten. A wiring layer of aluminum or the like is formed in contact with these titanium nitride and tungsten. The source region 114 at the center of the ring-shaped gate electrode 113 is in contact with titanium in a contact hole on the substrate surface, and is connected to the wiring layer through titanium, titanium nitride, and tungsten.
JP 2001-177085 A

  By the way, the ring gate is formed by a photolithography process using a gate mask. Then, using the gate as a mask, a source region is formed in a self-aligned manner in the central opening of the ring gate, and then an interlayer insulating film is formed. The contact hole formed in the interlayer insulating film is formed by a lithography process using a source contact mask. In this case, the alignment is performed so that the contact hole is positioned substantially at the center of the center opening of the ring gate.

  However, misalignment occurs in contact hole alignment due to manufacturing variations. If the contact hole is not located at the center of the center opening of the ring gate, the distance between the conductive material in the contact hole and the ring gate will vary depending on the position, and the amount of current flowing from the drain region to the source region Variation occurs.

  As described above, there is a problem that the sensor characteristics vary due to the manufacturing variation of the position of the source contact.

  The present invention has been made in view of such a problem, and provides a solid-state imaging device capable of improving characteristics by allowing a contact portion to a source to be formed in a self-aligned manner and a method for manufacturing the same. The purpose is to provide.

  The solid-state imaging device according to the present invention is a solid-state imaging device including a photoelectric conversion element and a transistor formed adjacent to the photoelectric conversion element. The solid-state imaging device is formed on the substrate in a formation region of the substrate and the photoelectric conversion element and the transistor. The first diffusion layer formed, the second diffusion layer formed on the first diffusion layer in the photoelectric conversion element formation region, and the first diffusion layer in the transistor formation region, A third diffusion layer formed continuously with the second diffusion layer; a gate electrode having an opening formed on the substrate above the third diffusion layer; and formed on the substrate below the opening. A source contact region, a contact contact layer formed of a first conductive material on the substrate of the source region, an insulating film formed over the substrate including the gate electrode and the contact contact layer, and the contact contact Characterized by comprising a conductive material formed in contact with the contact holes formed in the insulating film layer above the contact contacting layer.

  According to such a configuration, photogenerated charges generated in the photoelectric conversion element formation region are transferred from the second diffusion layer to the third diffusion layer. The threshold voltage of the channel of the transistor is controlled by the photogenerated charge held in the third diffusion layer, and a pixel signal corresponding to the photogenerated charge is output from the transistor. A contact contact layer formed of a conductive material is provided on the substrate surface of the source region. In the insulating film formed above the substrate, a contact hole is formed above the contact contact layer. In this contact hole, a conductive material is formed in contact with the contact contact layer. That is, the source region is electrically connected to the conductive material in the contact hole via the contact contact layer. Therefore, if the contact hole is formed above the contact contact layer, uniform electrical characteristics can be obtained even when the position is not located at the center of the opening of the gate electrode.

  Further, the gate electrode has a sidewall on the side surface on the opening side.

  According to such a configuration, the contact contact layer and the gate electrode are prevented from being short-circuited by the sidewall.

  The contact contact layer may be formed on the substrate surface and the sidewall surface in the opening.

  According to such a configuration, even when the position of the contact hole is relatively large, electrical conduction between the conductive material in the contact hole and the source region can be ensured.

  The contact contact layer is made of polysilicon or silicon material.

  According to such a configuration, the contact contact layer can have an appropriate resistance value, and, as will be described later, the hydrogen occlusion property can be sufficiently lowered to suppress the generation of dangling bonds on the substrate surface. it can.

  The solid-state imaging device manufacturing method according to the present invention is a method for manufacturing a solid-state imaging device including a photoelectric conversion element and a transistor formed adjacent to the photoelectric conversion element. Forming a reverse conductivity type first diffusion layer on the one conductivity type substrate; forming a one conductivity type second diffusion layer on the first diffusion layer in the photoelectric conversion element formation region; Forming a third diffusion layer of one conductivity type on the first diffusion layer in the transistor formation region so as to be continuous with the second diffusion layer; and above the substrate above the third diffusion layer Forming a gate electrode having an opening in the substrate, forming a sidewall on a side surface of the gate electrode on the opening side, and forming a source region on the substrate surface side on the third diffusion layer And the source region Forming a contact contact layer on the substrate with a first conductive material; forming an insulating film on the substrate including the gate electrode and the contact contact layer; and opening the insulating film above the contact contact layer. Forming a conductive material in contact with the contact contact layer in the contact hole formed.

  According to such a configuration, the first diffusion layer is formed on the substrate, and the second and third diffusion layers are formed on the first diffusion layer. The second diffusion layer is formed in the photoelectric conversion element formation region and generates photogenerated charges. The third diffusion layer is formed in the transistor formation region, and photogenerated charges from the second diffusion layer are transferred to control the threshold voltage of the transistor channel. A contact contact layer formed of a conductive material is provided on the substrate surface of the source region. In the insulating film formed above the substrate, a contact hole is formed above the contact contact layer. In this contact hole, a conductive material is formed in contact with the contact contact layer. That is, the source region is electrically connected to the conductive material in the contact hole via the contact contact layer. Therefore, if the contact hole is formed above the contact contact layer, uniform electrical characteristics can be obtained even when the position is not located at the center of the opening of the gate electrode.

  The contact contact layer is made of polysilicon or silicon material.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view showing a cross-sectional shape of one sensor cell of the solid-state imaging device according to the present embodiment, and FIG. 2 is an explanatory diagram showing a planar shape of one sensor cell of the solid-state imaging device according to the present embodiment. . 1 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a circuit block diagram showing the entire structure of the element by an equivalent circuit. 4 to 7 are process diagrams for explaining a method of manufacturing an element. 8 to 10 are plan views for explaining a method for manufacturing the element. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

<Structure of sensor cell>
The solid-state imaging device according to the present embodiment has a sensor cell array in which sensor cells that are unit pixels are arranged in a matrix. Each sensor cell collects and accumulates photogenerated charges generated according to incident light, and outputs a pixel signal at a level based on the accumulated photogenerated charges. An image signal of one screen can be obtained by arranging the sensor cells in a matrix.

  First, the structure of each sensor cell will be described with reference to FIGS. FIG. 2 shows one sensor cell. This embodiment shows an example in which holes are used as photogenerated charges. Even in the case where electrons are used as the photo-generated charges, the same configuration is possible. FIG. 1 shows a cross-sectional structure of the cell cut along the line A-A ′ of FIG. 2.

  As shown in the plan view of FIG. 2, a photodiode PD and a modulation transistor TM are provided adjacent to each other in a sensor cell 3 that is a unit pixel. As the modulation transistor TM, for example, an N-channel depletion MOS transistor is used.

  In the photodiode PD formation region, which is a photoelectric conversion element formation region, an opening region that transmits light is formed in the step of forming a wiring layer on the surface of the substrate 1. A P-type well in a region wider than the opening region is formed at a relatively shallow position on the surface of the substrate 1, and a collection well 4 as a second diffusion layer for collecting photogenerated charges generated by the photoelectric conversion element is formed. Yes. An N-type diffusion layer 32 as a pinning layer is formed on the surface of the substrate 1 on the collection well 4.

  A P-type well is formed in the modulation transistor TM formation region at a position substantially the same substrate depth as that of the collection well 4, and the photo-generated charges collected in the collection well 4 are transferred to control the modulation transistor TM. A modulation well 5 as a three diffusion layer is formed. In the example of FIG. 1, the collection well 4 and the modulation well 5 are configured by the respective parts of the P well 24 formed integrally, but may be formed separately.

An annular gate (ring gate) 6 is formed on the surface of the substrate 1 on the modulation well 5, and a region near the surface of the substrate 1 in the opening 6a at the center of the ring gate 6 is a high-concentration N-type region. A source region 7 is formed. In FIG. 2, the ring gate 6 and carrier pockets to be described later are shown in a circular shape, but may be in an elliptical shape or an arbitrary polygonal shape (for example, an octagonal shape). An N-type drain region 8 is formed around the ring gate 6. An N ⁺ drain contact region (not shown) is formed near the surface of the substrate 1 at a predetermined position of the drain region 8.

  The modulation well 5 controls the threshold voltage of the channel of the modulation transistor TM. A carrier pocket 10 which is a P-type high concentration region is formed in the modulation well 5 below the ring gate 6. The modulation transistor TM is constituted by the modulation well 5, the ring gate 6, the source region 7 and the drain region 8, and the threshold voltage of the channel changes according to the electric charge accumulated in the modulation well 5 (carrier pocket 10). It is like that.

  The drain region 8, the diffusion layer 22, the diffusion layer 21, the diffusion layer 21 ′, and the diffusion layer 32 are biased to a positive potential by the application of the drain voltage, so that the diffusion layer 32 and A depletion layer extends from the boundary surface with the collection well 4 and from the boundary surface between the diffusion layer 21 and the collection well 4 to the entire collection well 4 and its periphery. In the depletion region, photogenerated charges due to light incident through the opening region are generated. As described above, the generated photo-generated charges are collected in the collection well 4.

  The charges collected in the collection well 4 are transferred to the modulation well 5 and held in the carrier pocket 10. As a result, the source potential of the modulation transistor TM is in accordance with the amount of charge transferred to the modulation well 5, that is, the incident light to the photodiode PD.

<Sensor cell cross section>
Furthermore, the cross-sectional structure of the sensor cell 3 will be described in detail with reference to FIG.

  An isolation region 22 is provided between the photodiode PD formation region (PD) and the modulation transistor TM formation region (TM) of adjacent cells. N-type wells 21 and 21 ′ as first diffusion layers are formed in the entire region of the P-type substrate 1 at a relatively deep position of the substrate 1. A P-type collection well 4 is formed on the N-type well 21 in the photodiode formation region. An N-type diffusion layer 32 which is a pinning layer is formed on the substrate surface side above the collection well 4. The N-type well 21 is formed up to a relatively deep position on the substrate.

  On the other hand, a P-type buried layer 23 is formed on the substrate 1 in the modulation transistor TM formation region. The P-type buried layer 23 limits the N-type well 21 'to a relatively shallow position on the substrate. A P-type modulation well 5 is formed on the N-type well 21 ′ on the P-type buried layer 23. A carrier pocket 10 is formed in the modulation well 5.

The carrier pocket 10 is formed in a ring shape below the ring gate 6 in plan view. The carrier pocket 10 is a sufficiently high concentration diffusion layer by P ⁺ diffusion.

In the modulation transistor TM formation region, the ring gate 6 is formed on the substrate surface via the gate oxide film 31, and the N-type diffusion layer 27 constituting the channel is formed on the substrate surface below the ring gate 6. The ring gate 6 has a two-phase structure of a lower layer 6a and an insulating layer 6b made of a conductive material. A side wall 6 c is formed on the side surface of the ring gate 6. In the central opening 6d portion of the ring gate 6, an N ⁺ diffusion layer is formed on the substrate surface to constitute the source region 7.

  The source region 7 is formed in a self-aligned manner in the central opening 6d of the ring gate 6 using the ring gate 6 including the sidewall 6c as a mask.

  Further, an N-type diffusion layer is formed on the substrate surface around the ring gate 6 to constitute the drain region 8. The N type diffusion layer 27 constituting the channel is electrically connected to the source region 7 and the drain region 8. The isolation region 22 is electrically connected to the N-type wells 21, 21 ′ and the drain region 8.

  In the present embodiment, a contact contact layer 9 made of, for example, polysilicon or silicon material is formed on the substrate surface side on the source region 7, that is, on the substrate surface in the central opening 6d of the ring gate 6 and the surface of the sidewall 6c. Is formed.

  For example, the contact contact layer 9 is made of a material having a sufficiently low hydrogen storage property such as aluminum, polysilicon, epitaxially grown silicon, tungsten, tungsten silicide, tungsten nitride or the like.

  The contact contact layer 9 extends to the upper surface (insulating layer 6b) of the ring gate 6. That is, it is provided in the entire area within the circle indicated by reference numeral 9 in FIG. The contact contact layer 9 is preferably formed in a somewhat wide area, but does not necessarily extend to the upper surface of the ring gate 6 and may be formed in a range corresponding to the alignment accuracy of the source contact.

  The contact contact layer 9 is obtained, for example, by etching a conductive material formed on the entire surface of the substrate. In this case, a mask that covers a portion other than the ring gate 6 and the outer peripheral edge of the ring gate 6 is used, and etching is performed using the ring gate 6 including the sidewall 6c as a mask. Thereby, the contact contact layer 9 is formed in a self-aligned manner in the central opening 6d of the ring gate 6.

  An interlayer insulating film 41 is formed over the entire surface of the substrate including the ring gate 6 partially covered with the contact contact layer 9. A contact hole 42 is formed in the interlayer insulating film 41 on the source region 7, and a conductive material 43 is embedded in the contact hole 42. For example, a two-layer structure film of titanium and titanium nitride is employed as the conductive material 43. Furthermore, the contact hole 42 surrounded by the conductive material 43 is filled with, for example, tungsten (not shown) so that these conductive materials are connected to a wiring layer (not shown) formed on the interlayer insulating film 41. It has become.

<Circuit configuration of the entire device>
Next, a circuit configuration of the entire solid-state imaging device according to the present embodiment will be described with reference to FIG.

  The solid-state imaging device 61 includes a sensor cell array 62 including the sensor cells 3 of FIG. 2 and circuits 63 to 65 for driving the sensor cells 3 in the sensor cell array 62. The sensor cell array 62 is configured by arranging the cells 3 in a matrix. The sensor cell array 62 includes, for example, a 640 × 480 cell 3 and an optical black (OB) region (OB region). When the OB region is included, the sensor cell array 62 is composed of, for example, 712 × 500 cells 3.

  Each sensor cell 3 includes a photodiode PD that performs photoelectric conversion and a modulation transistor TM for detecting and reading out an optical signal. The photodiode PD generates a charge (photogenerated charge) corresponding to the incident light, and the generated charge is collected in the collection well 4 (corresponding to the connection point PDW in FIG. 3). The photo-generated charges collected in the collection well 4 are transferred to and held in the carrier pocket 10 in the modulation well 5 (corresponding to the connection point TMW in FIG. 3) for threshold modulation of the modulation transistor TM.

  The modulation transistor TM is equivalent to a change in the back gate bias due to the photogenerated charge held in the carrier pocket 10, and the channel threshold voltage changes according to the amount of charge in the carrier pocket 10. As a result, the source voltage of the modulation transistor TM corresponds to the charge in the carrier pocket 10, that is, corresponds to the brightness of the incident light of the photodiode PD.

  In this manner, each cell 3 exhibits operations such as accumulation, transfer, readout, and discharge by applying drive signals to the ring gate 6, the source region 7, and the drain region 8 of the modulation transistor TM. A signal is output from the source region 7 to a wiring (not shown) on the interlayer insulating film 41 via the contact contact layer 9 and the conductive material 43 in the contact hole 42.

  Signals are supplied to each part of the cell 3 (not shown) from a vertical drive scanning circuit 63, a drain drive circuit 64, and a horizontal drive scanning circuit 65, as shown in FIG. The vertical drive scanning circuit 63 supplies a scanning signal to the gate line 67 in each row, and the drain drive circuit 64 applies a drain voltage to the drain region 8 in each column. The horizontal drive scanning circuit 65 supplies a drive signal to the switch 68 connected to each source line 66.

  Each cell 3 is provided corresponding to the intersection of a plurality of source lines 66 arranged in the horizontal direction in the sensor cell array 62 and a plurality of gate lines 67 arranged in the vertical direction. In each cell 3 of each line arranged in the horizontal direction, the ring gate 6 of the modulation transistor TM is connected to a common gate line 67, and each cell 3 in each column arranged in the vertical direction is the source of the modulation transistor TM. Are connected to a common source line 66.

  By supplying an ON signal (selection gate voltage) to one of the plurality of gate lines 67, the cells commonly connected to the gate line 67 to which the ON signal is supplied are simultaneously selected, and these selected cells are selected. A pixel signal is output from each source via each source line 66. The vertical drive scanning circuit 63 supplies an ON signal to the gate line 67 while sequentially shifting it in one frame period. Pixel signals from each cell of the line to which the ON signal is supplied are simultaneously read from each source line 66 for one line and supplied to each switch 68. The pixel signals for one line are sequentially output (line output) for each pixel from the switch 68 by the horizontal drive scanning circuit 65.

  The switch 68 connected to each source line 66 is connected to the video signal output terminal 70 via a common constant current source (load circuit) 69. The source of the modulation transistor TM of each sensor cell 3 is connected to the constant current source 69, and the source follower circuit of the sensor cell 3 is configured.

  It should be noted that hydrogen sintering is performed at any timing from the side wall 6c forming step in the manufacturing step described later to the step of forming the conductive material 43. For example, hydrogen sintering is performed by heating to about 400 ° C. in a hydrogen atmosphere.

  By the way, when the source contact is formed, variations occur, and the contact hole 42 does not always come to the approximate center of the source region. Depending on the alignment accuracy of the contact hole 42, the position of the contact hole 42 may be relatively largely shifted from the center of the central opening 6d. 1 and 2 shows an example in which the contact hole 42 is formed so as to be shifted to the left side in FIG. 1 with respect to the central opening 6d.

  However, in the present embodiment, the contact contact layer 9 is formed on the substrate surface of the source region 7 and the surface of the sidewall 6c of the ring gate 6. The conductive material 43 formed in the contact hole 42 is connected to the source region 7 through the contact contact layer 9 to achieve a source contact. That is, if the contact hole 42 is formed on the contact contact layer 9, even if the formation position of the contact hole 42 is shifted, there is no change in the electrical characteristics.

  The contact contact layer 9 is made of a material having a relatively low hydrogen storage property such as polysilicon. A conductive material 43 having a two-layer structure of titanium and titanium nitride is formed on the contact contact layer 9 as a buried layer of the contact hole. That is, a contact contact layer 9 having a sufficiently low hydrogen storage property is formed between the substrate surface above the source region 7 and the titanium material constituting the conductive material 43. Thereby, removal of hydrogen from the substrate surface can be prevented, and dangling bonds can be reduced by hydrogen sintering. Thereby, a solid-state imaging device having excellent electrical characteristics can be obtained.

  Further, since the substrate is not directly damaged during contact etching, there is an advantage that generation of dark current can be suppressed.

  In the present embodiment, a side wall 6c made of an insulating material is also formed on the side surface of the ring gate 6 on the center opening 6d side, and the contact contact layer 9 and the layer 6a of the ring gate 6 are short-circuited. Can be prevented.

  By the way, when the source region 7 and the buried layer of the contact hole 42 are directly connected as in the prior art, since the contact resistance is large, it is necessary to form the source region 7 with a high concentration. In this case, the source region 7 is also formed to a deep position, so that a leak path from the N-type well 21 'via the source region 7 is easily formed, and there is a disadvantage that black smear occurs.

  On the other hand, in the present embodiment, the source region 7 is connected to the contact contact layer 9 made of a polysilicon material or the like, so that the contact resistance is small. As a result, the concentration of the source region 7 can be reduced. As a result, the depth of the source region 7 is also reduced, and it is difficult to form a leak path from the N-type well 21 ′ via the source region 7, and there is an advantage that black smear can be reduced.

<Process>
Next, a method for manufacturing the element will be described with reference to process diagrams of FIGS. 4 to 7 and plan views of FIGS. 8 to 10. 6 to 8 show cross sections taken along the line AA ′ in FIGS. 9 to 10. 4 to 7, arrows on the substrate indicate that ion implantation is performed.

  As shown in FIG. 4A, for example, boron (B) ions are implanted into the entire surface of the prepared P substrate 1 to form a P-type well 24 on the surface side of the substrate 1. The P-type well 24 constitutes the collection well 4 in the photodiode formation region and the modulation well 5 in the modulation transistor formation region.

  Next, a resist mask 91 is formed in a portion other than the photodiode formation region, and, for example, phosphorus (phosphorus (P)) ions are implanted to form the N-type well 21 (FIG. 8A). This ion implantation is performed up to a relatively deep position in the photodiode formation region (FIG. 4B).

  Next, phosphorus ions are implanted into the substrate 1 to form an N-type well below the P-type well 24. Thus, an N-type well 21 is formed in the photodiode formation region, and an N-type well 21 'is formed in the modulation transistor formation region (FIG. 4C).

  Next, as shown in FIG. 4D, a P-type buried layer 23 is formed by deep ion implantation of P-type impurities in the modulation transistor formation region using the resist mask 92 (FIG. 8B). )). Further, an N-type diffusion layer 27 for obtaining a channel of the modulation transistor TM is formed in the vicinity of the surface of the substrate 1 using the same resist mask 92.

  Next, as shown in FIG. 5A, a resist mask 93 is formed to form an isolation region 22 for element isolation (FIG. 8C). Next, as shown in FIG. 5B, a gate oxide film 31 is formed on the surface of the substrate 1 by thermal oxidation.

Next, as shown in FIG. 5C, a carrier pocket 10 made of a dense P ⁺ diffusion layer is formed in the modulation well 5 below the ring gate 6 using a resist mask 94 (FIG. 9A). To do. The planar shape of the ring gate 6 is annular as shown in FIG. Next, as shown in FIG. 5D, the ring gate 6 of the modulation transistor TM is formed on the gate oxide film 31 (FIG. 9B). The ring gate 6 has a two-layer structure of a lower layer 6a and an insulating layer 6b made of a conductive material.

  Next, as shown in FIG. 6A, N-type impurities are ionized using the resist mask 96 and the ring gate 6 (FIG. 9C) formed so as to close the central opening 6d of the ring gate 6 as masks. By implanting, an N-type diffusion layer 32 as a pinning layer is formed on the surface of the substrate 1.

  Next, as shown in FIG. 6B, an oxide film 51 is deposited in order to form the sidewall 6 c on the ring gate 6. Next, as shown in FIG. 6C, sidewalls 6c are formed by anisotropic etching. Next, the outside of the ring gate 6 is covered with a resist mask (not shown), and ion implantation is performed using the ring gate 6 including the resist mask and the sidewall 6c as a mask to form the source region 7 in a self-aligned manner (FIG. 6). (C)).

  Further, in this embodiment, hydrogen sintering is performed by placing the substrate of FIG. 6C in a hydrogen atmosphere and heating at 400 ° C. Thereby, dangling bonds in the vicinity of the substrate surface of the source region 7 are removed.

  Next, as shown in FIG. 6D, in order to form the contact contact layer 9, a material having a sufficiently low hydrogen storage property, for example, a polysilicon material 52 is formed on the substrate surface. Since the polysilicon material 52 constituting the contact contact layer 9 has a sufficiently low hydrogen storage property, hydrogen bonded to the substrate surface of the source region 7 is hardly taken into the contact contact layer 9. That is, an increase in dangling bonds due to the contact contact layer 9 can be suppressed.

  Next, as shown in FIG. 7A, etching is performed using a resist mask 97 (FIG. 10A) reaching the upper surface of the ring gate 6 from the center opening 6d of the ring gate 6, and FIG. The contact contact layer 9 shown in FIG. The planar size of the contact contact layer 9 may be determined according to the alignment accuracy in the source contact formation process.

  Next, using the resist mask 98 and the ring gate 6 (FIG. 10B) covering the ring gate opening and the photodiode formation region as masks, N-type impurities are ion-implanted to form the drain region 8 (FIG. 7C). )).

  Next, after forming an interlayer insulating film 41 on the surface of the substrate 1, a contact hole 42 reaching the center of the opening of the ring gate 6 is formed (FIG. 7D). Since the contact contact layer 9 is formed on the surface of the substrate above the source region 7 and the surface of the sidewall 6c of the ring gate 6 around the source region 7, the contact hole 42 is always formed on the contact contact layer 9.

  Since the contact contact layer 9 is formed, it is possible to prevent the substrate surface from being damaged by the etching during the etching for forming the contact hole 42. As a result, the generation of dark current can be suppressed.

  Thereafter, a conductive material having a two-layer structure of titanium and titanium nitride is formed in the contact hole 42, and a buried layer of, for example, tungsten is formed in the contact hole 42 surrounded by the conductive material 43.

  As a result, the conductive material 43 is connected to the source region 7 through the contact contact layer 9. Since the contact contact layer 9 is formed over the entire substrate surface of the source region 7, if the contact hole 42 is formed on the contact contact layer 9, the electrical characteristics of the source contact are uniform regardless of the position. Can be.

  That is, since the contact contact layer 9 having a sufficiently low hydrogen storage property is provided between the conductive material 43 made of titanium having a high hydrogen storage property and the source region 7, the generation of dangling bonds is suppressed. The electrical characteristics can also be improved.

FIG. 3 is a schematic cross-sectional view showing a cross-sectional shape of one sensor cell of the solid-state imaging device according to the present embodiment. Explanatory drawing which shows the planar shape of 1 sensor cell of the solid-state imaging device which concerns on this Embodiment. The circuit block diagram which shows the whole structure of an element with an equivalent circuit. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. Process drawing for demonstrating the manufacturing method of an element. The top view for demonstrating the manufacturing method of an element. The top view for demonstrating the manufacturing method of an element. The top view for demonstrating the manufacturing method of an element. FIG. 6 is a schematic cross-sectional view showing an image sensor disclosed in Patent Document 1.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Collection well, 5 ... Modulation well, 6 ... Ring gate, 7 ... Source region, 8 ... Drain region, 9 ... Contact contact layer, 10 ... Carrier pocket, PD ... Photodiode, TM ... Modulation transistor .

Claims (6)

In a solid-state imaging device including a photoelectric conversion element and a transistor formed next to the photoelectric conversion element,
A substrate,
A first diffusion layer formed on the substrate in a formation region of the photoelectric conversion element and the transistor;
A second diffusion layer formed on the first diffusion layer in the formation region of the photoelectric conversion element;
A third diffusion layer formed on the first diffusion layer in the transistor formation region and formed continuously with the second diffusion layer;
A gate electrode having an opening formed on the substrate above the third diffusion layer;
A source region formed in the substrate below the opening;
A contact contact layer formed of a first conductive material on the substrate of the source region;
An insulating film formed over the substrate including the gate electrode and the contact contact layer;
A contact hole formed in the insulating film above the contact contact layer;
And a second conductive material formed in the contact hole.   The solid-state imaging device according to claim 1, wherein the gate electrode has a sidewall on a side surface on the opening side.   The solid-state imaging device according to claim 2, wherein the contact contact layer is formed on the substrate surface and the sidewall surface in the opening.   The solid-state imaging device according to claim 1, wherein the contact contact layer is made of polysilicon or a silicon material. In a method for manufacturing a solid-state imaging device including a photoelectric conversion element and a transistor formed next to the photoelectric conversion element,
Forming a first diffusion layer of reverse conductivity type on a substrate of one conductivity type in the formation region of the photoelectric conversion element and the transistor;
Forming a second diffusion layer of one conductivity type on the first diffusion layer in the formation region of the photoelectric conversion element;
Forming a third diffusion layer of one conductivity type on the first diffusion layer in the transistor formation region so as to be continuous with the second diffusion layer;
Forming a gate electrode having an opening above the substrate above the third diffusion layer;
Forming a sidewall on a side surface of the gate electrode on the opening side;
Forming a source region on the surface of the substrate on the third diffusion layer;
Forming a contact contact layer with a first conductive material on the substrate in the source region;
Forming an insulating film over the substrate including the gate electrode and the contact contact layer;
Forming a contact hole in the insulating film above the contact contact layer;
And a step of forming a second conductive material in the contact hole.   6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the contact contact layer is made of polysilicon or a silicon material.

Images