JP2006186802A - Downsampling fir filter apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform filtering processing of I and Qch data at right angles to each other only with a single product-sum operation means. <P>SOLUTION: A first delay part 101 delays Ich input data just by the number of taps, an addition delay part 102 makes the Qch input data more delayed than I channel data so that product-sum operation timings of the Q channel data and I channel data do not match, and a second delay part 103 delays the Qch input data from the addition delay part 102 just by the number of taps. A data selection part 104 selects one of the delayed Ich input data and Qch input data with time division, multiplies filter coefficients corresponding to Ich input data and Qch input data delayed by a product-sum operation part 106 to perform accumulation addition, and a data holding part 107 holds the Ich input data and Qch input data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a down-sampling FIR (Down Sampling FIR) filter device that accumulates and accumulates filter coefficients corresponding to respective delay amounts with respect to mutually orthogonal I channel data and Q channel data, and outputs the result.

  The downsampling FIR filter device is used when directly transferring signals between devices having different sampling frequencies, or when reducing the sampling rate such as changing a signal sequence encoded by delta modulation to a PCM code. The target signals are so-called I channel and Q channel data signals orthogonal to each other.

  FIG. 7 is a block diagram showing a configuration example of a conventional downsampling FIR filter device. FIG. 7 shows a case in which, for example, an FIR digital filter disclosed in Patent Document 1 is used.

  The conventional downsampling FIR filter apparatus 700 shown in FIG. 7 includes a first delay unit 701, a product-sum operation unit 702, a data holding unit 703, and a Q channel (Qch) that perform processing on I channel (Ich) data. A second delay unit 704 that performs processing on data, a product-sum operation unit 705, a data holding unit 706, a filter coefficient storage unit 707, and a control unit 708 that controls them are provided.

  The operation will be described. The I channel and Q channel data having orthogonality are input to the first delay unit 701 and the second delay unit 704 in the communication apparatus, respectively. The first delay unit 701 and the second delay unit 704 each perform a delay process on the input data under the control of the control unit 708, and provide the delayed data to the corresponding product-sum operation units 702 and 705.

  The product-sum operation units 702 and 705 include multipliers 702a and 705a and adders 702b and 705b, respectively. Each delay data output from the first delay unit 701 and the second delay unit 704 becomes one input of the multipliers 702a and 705a. The control unit 708 reads out the filter coefficient corresponding to the delay amount of each delay data output from the first delay unit 701 and the second delay unit 704 from the filter coefficient storage unit 707, and inputs the other of the multipliers 702a and 705a. Give to the end.

  The multiplication results of the multipliers 702a and 705a are added to the data held in the data holding units 703 and 706 in the adders 702b and 705b, and the addition result is held in the data holding units 703 and 706. Under the control of the control unit 708, the data holding units 703 and 706 repeat the operation of giving the held data to the adders 702b and 705b and capturing and holding the addition result within a certain period.

As a result, the product-sum operation result of the I channel data and the filter coefficient is cumulatively added and held in the data holding unit 703. Also, the product-sum operation result of the Q channel data and the filter coefficient is cumulatively added and held in the data holding unit 706. The control unit 708 causes the data holding units 703 and 706 to output I channel data and Q channel data, respectively, after a predetermined time has elapsed.
JP-A-3-78310

  However, in the conventional downsampling FIR filter device, a product-sum operation unit is provided for each of the I-channel input data and the Q-channel input data that are orthogonal to each other. There is a problem that it is not possible to reduce the size of the apparatus.

  Even when the filter coefficient is a symmetric coefficient value with respect to the center of the impulse response length, the number of calculations is required as many as the number of filter coefficients. There is also a problem that cannot be achieved.

  The present invention has been made in view of the above points, and it is possible to use only one product-sum operation unit that performs filtering processing of two channel data orthogonal to each other. In particular, the filter coefficient is at the center of the impulse response length. On the other hand, an object of the present invention is to provide a downsampling FIR filter device capable of increasing the calculation speed in the case of symmetrical coefficient values.

  In order to solve the above problems, a downsampling FIR filter apparatus according to the present invention integrates and accumulates filter coefficients corresponding to respective delay amounts with respect to mutually orthogonal I channel data and Q channel data and outputs the result. A FIR filter device comprising: first delay means for delaying the I channel data; additional delay means for delaying the Q channel data from the I channel data; and Q channel data delayed by the additional delay means. Delay means read out from the first delay means and delay data read out from the second delay means to select and output the filter coefficient, Stored filter coefficient storage means and the I channel data output from the selection means or the previous For each Q channel data, the filter coefficient corresponding to the delay amount in the first delay means or the delay amount in the second delay means is read out from the filter coefficient storage means and multiplied, and the multiplication results are cumulatively added. And product-sum operation means for outputting.

  In the down-sampling FIR filter device, the filter coefficient is a coefficient value symmetrical with respect to the center of the impulse response length, and the product-sum operation means includes the I-channel data output from the selection means. Adding two data multiplied by the same filter coefficient, adding two data multiplied by the same filter coefficient among the Q channel data, and for each of the two added data, The same filter coefficient corresponding to the delay amount in the first delay means or the delay amount in the second delay means is read from the filter coefficient storage means and multiplied, and the multiplication results are accumulated and output.

  Further, in the downsampling FIR filter device, the second delay means sequentially writes the Q channel data in the order of the tap numbers, and the additional delay means has the second delay means in the order of the tap numbers. When all the Q channel data is written, the Q channel data is sequentially written in the order of the tap numbers.

  In the downsampling FIR filter device, the second delay means and the additional delay means sequentially write the Q channel data in the order of their tap numbers.

  Further, in the downsampling FIR filter device, the additional delay means includes delay means for the number of the Q channel data input during the product-sum operation of the I channel data by the product-sum operation means. .

  In the downsampling FIR filter device, the first delay means reads the delayed I channel data by the number of I channel input data from the read start tap number at the previous I channel calculation. Start with a shifted tap number.

  Further, in the downsampling FIR filter device, the additional delay means and the second delay means read the delayed Q channel data, and use the tap numbers that are consecutive for the second delay means and the additional delay means. It has a tap number that is shifted by the number of the Q channel input data from the read start tap number in the previous Q channel calculation.

  According to the present invention, the additional delay unit delays the Q channel data from the I channel data so that the product-sum operation timing of the Q channel data and the I channel data is shifted. Filtering processing of two orthogonal channel data can be processed by one common product-sum operation unit, and the circuit scale can be reduced. In particular, when the filter coefficient is a symmetric coefficient value with respect to the center of the impulse response length, a product-sum operation is performed using two data multiplied by the same filter coefficient, so that calculation can be performed without using a high-speed element or the like. Can be speeded up.

  In the embodiment of the present invention, for example, in the filtering of two channel data orthogonal to each other, only one common product-sum operation unit is required, and the filter coefficient is symmetrical with respect to the center of the impulse response length. In the case of numerical values, it is to be able to speed up the calculation without using a high-speed element or the like.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a downsampling FIR filter device according to Embodiment 1 of the present invention. In FIG. 1, a downsampling FIR filter apparatus 100 according to the first embodiment includes a first delay unit 101, an additional delay unit 102, a second delay unit 103, a data selection unit 104, a filter coefficient storage unit 105, a product. A sum calculation unit 106, a data holding unit 107, and a control unit 108 for controlling them are provided.

  Next, the operation will be described with reference to FIGS. First, in FIG. 1, Ich (I channel) input data and Qch (Q channel) input data are signal components orthogonal to each other. The Ich input data is input to the first delay unit 101. The Qch input data is input to the additional delay unit 102. As will be described later, of course, it may be input to the additional delay unit 102 or the second delay unit 103.

  The first delay unit 101 takes in the Ich input data under the control of the control unit 108, delays it by the tap of the filter, and applies it to one input terminal of the data selection unit 104.

  The additional delay unit 102 includes delay devices (not shown) for the number of Qch input data input during the product-sum operation of the Ich input data, and is input under the control of the control unit 108. And is delayed by an arbitrary timing from the Ich input data.

  Under the control of the control unit 108, the second delay unit 103 takes in the Qch input data and delays it by the tap of the filter. The delay data of the Qch input data applied to the other input terminal of the data selection unit 104 is output from the additional delay unit 102 and the second delay unit 103. Thereby, each product-sum operation timing of Ich input data and Qch input data is shifted.

  The data selection unit 104 is read from the first delay unit 101 under the control of the control unit 108, for example, read from the n−1 delay Ich input data and the additional delay unit 102 or the second delay unit 103. The n−1 pieces of delayed Qch input data are switched so that the product-sum operation timings of the delayed Ich input data and the delayed Qch input data are shifted, and are output to the product-sum operation unit 106.

  The product-sum operation unit 106 includes a multiplier 106a and an adder 106b. The multiplier 106 a obtains n−1 delay data from the data selection unit 104 and n filter coefficients corresponding to the output delay data of the data selection unit 104 that the control unit 108 reads from the filter coefficient storage unit 105. Multiply and give to adder 106b.

  The adder 106b adds the data held by the data holding unit 107 to the multiplication result of the multiplier 106a, and outputs the data to the data holding unit 107 for holding. Under the control of the control unit 108, the data holding unit 107 repeats the operation of supplying the held data from one output end to the adder 106b and taking in and holding the addition result within a certain period.

  As a result, the product-sum operation results with the corresponding filter coefficients of the Ich input data and the Qch input data are cumulatively added and held in the data holding unit 107 in a time division manner. The control unit 108 causes the Ich input data and the Qch input data to be output in time series in this order from the other output terminal of the data holding unit 107 after a predetermined time has elapsed.

  FIG. 2 is a diagram for explaining a delay data generation operation according to the first embodiment.

  FIG. 2 shows Ich input data write control to the first delay unit 101, Ich input data read control from the first delay unit 101, and filter coefficient read control from the filter coefficient storage unit 105. Has been.

  In FIG. 2, when the delay amount in the first delay unit 101, that is, the number of Ich input data to the first delay unit 101 is, for example, “3”, that is, three data are input during one calculation. An example of the order of writing and the order of reading in this case is shown.

  That is, as shown at the left end of FIG. 2, the Ich input data is written in order from the top in accordance with the tap numbers (tap1 to tapn) in the first delay unit 101.

  Reading from the first delay unit 101 is the number of Ich input data from the read start tap number at the time of the previous I channel calculation, that is, in this example, “3” which is the delay amount of the Ich input data. Start with tap numbers that are just staggered.

  That is, in FIG. 2, at the first calculation, the read start position is the same as the first tap number tap1 as the write start position, and the data is sequentially read up to the final tap number tapn.

  In the second calculation, the fifth tap number tap5 shifted by “3” that is the delay amount of the Ich input data from the first reading start tap number tap1 of the previous calculation is the reading start position, and the final Are sequentially read up to the tap number tapn, returning to the first tap number tap1, and sequentially read up to the fourth tap number tap4.

  Similarly, in the third calculation, the ninth tap number tap9, which is shifted from the read start tap number tap5 of the second previous calculation by an amount of “3” that is the delay amount of the Ich input data, is the read start position. Thus, the data is sequentially read up to the final tap number tapn, returned to the first tap number tap1, and read in order up to the eighth tap number tap8.

  In the filter coefficient reading control from the filter coefficient storage unit 105, the filter coefficients are similarly read from the corresponding tap numbers in the same order.

  Note that the delay data generation operation in the second delay unit 103 for the Qch input data is performed in the same manner as the delay operation in the first delay unit 101 for the Ich input data.

  However, in the first embodiment, since the additional delay unit 102 and the second delay unit 103 function as one delay unit, writing of Qch input data to the additional delay unit 102 and the second delay unit 103 is not performed. First, writing to the second delay unit 103 in the order of the tap numbers, and when writing is completed for all, the method of sequentially writing the tap numbers of the additional delay unit 102, the tap number of the additional delay unit 102 and the second delay unit 103 Any one of the methods of writing in the same order to the tap numbers may be used. In short, by writing Qch input data to the additional delay unit 102 and the second delay unit 103 and reading as described later, the Q channel data is delayed from the I channel data, and the Q channel data and the I channel data are What is necessary is just to make the product-sum operation timing deviate.

  In the first embodiment, when reading from the additional delay unit 102 and the second delay unit 103, the additional delay unit 102 and the second delay unit 103 are treated as delay devices having consecutive tap numbers, and the additional delay is performed. Unit 102 delays Q channel data from I channel data so as to shift the product-sum operation timing of Q channel data and I channel data, and outputs the result to second delay unit 103. Therefore, like the first delay unit 101, the second delay unit 103 starts from a tap number that is shifted by the number of Qch input data from the read start tap number at the time of the previous Q channel calculation.

  FIG. 3 is a time chart for explaining the switching operation between Ich input data and Qch input data according to the first embodiment.

3, D _i0 , D _i1 ,..., D _in−1 , D _in indicate Ich input data. Further, D _q0 , D _q1 ,..., D _qn−1 , D _qn indicate Qch input data, and h ₀ , h ₁ ,..., H _n−1 , h _n are Ich input data, respectively. The filter coefficient corresponding to the delay amount is shown.

In the first embodiment, first, as shown in FIG. 3, within the Ich product-sum operation time 301, the product-sum operation with the filter coefficient for the Ich input data, that is, D _i0 × h ₀ , D _i0 × h ₀ + D _i1 × h ₁ ,..., ΣD _in−1 × h _n−1 and ΣD _in × h _n are performed.

In the subsequent Qch product-sum operation time 302, similarly, the product-sum operation with the filter coefficient for the Qch input data, that is, D _q0 × h ₀ , D _q0 × h ₀ + D _q1 × h _{1 ,.} , ΣD _qn−1 × h _n−1 and ΣD _qn × h _n are performed.

  Therefore, the sum of the data length obtained during the Ich product-sum operation time 301 and the data length obtained during the Qch product-sum operation time 302 becomes the data length 303 after downsampling.

  Since the I channel output data and the Q channel output data may be output simultaneously with the end of the product-sum operation, the switching timing between the Ich product-sum operation time 301 and the Qch product-sum operation time 302 is arbitrary.

  As described above, according to the first embodiment, the additional delay unit 102 that delays the Qch input data from the Ich input data is provided, and the additional delay unit 102 delays the Q channel data from the I channel data so as to delay the Q channel data. The product-sum operation timing of the I-channel data and the I-channel data is shifted, and the product-sum operation of the delay data of each of the I channel and the Q channel and the filter coefficient is used in a time-sharing manner. Therefore, it is possible to perform the filtering process for each data of the I channel and the Q channel, which are originally desired to be processed in parallel, without impairing the downsampling function. Therefore, the product-sum operation unit 106 having one multiplier 106a and adder 106b can be shared, so that the circuit scale can be reduced.

Embodiment 2. FIG.
Next, a downsampling FIR filter device according to Embodiment 2 of the present invention will be described. In the second embodiment, it is assumed that the filter coefficient is a coefficient value that is symmetrical with respect to the center of the impulse response length. In this case, the calculation speed is increased.

  FIG. 4 is a block diagram showing a configuration of a downsampling FIR filter device according to Embodiment 2 of the present invention. In FIG. 4, components that are the same as or equivalent to the components of the first embodiment shown in FIG. Here, the description will be focused on the portion related to the second embodiment.

  As shown in FIG. 4, the downsampling FIR filter device 400 according to the second embodiment includes a product-sum operation unit 401 in place of the product-sum operation unit 106 in the configuration of the first embodiment shown in FIG. 1. A control unit 402 is provided instead of the control unit 108.

  The product-sum operation unit 401 according to the second embodiment includes data selectors 401a, 401c, and 401d, a multiplier 401b, and an adder 401e. The data selectors 401 a, 401 c, and 401 d perform a selection operation under the control of the control unit 402.

  Here, the output terminal of the data selection unit 104 is connected to one input terminal of each of the data selectors 401a and 401c. The other input terminal of the data selector 401a is connected to one output terminal of the data holding unit 107 together with one input terminal of the data selector 401d. The multiplier 401b multiplies the output of the data selector 401a and the filter coefficient from the filter coefficient storage unit 105, and gives the multiplication result to the other input terminal of the data selector 401c. The adder 401e adds the output of the data selector 401c and the output of the data selector 401d, and gives the addition result to the data holding unit 107. The other input terminal of the data selector 401d is connected to the ground (ground).

  In addition, the control unit 402 according to the second embodiment reads two data multiplied by the same filter coefficient by the method shown in FIG. 5 from the first delay unit 101 and the additional delay unit 102 or the second delay unit 103, The data selection unit 104 is caused to perform a selection operation by the method shown in FIG. Then, the following control is applied to the product-sum operation unit 401.

  That is, under the control of the control unit 402, each of the data selectors 401c and 401d selects one input terminal, and the adder 401e gives the output data of the data selection unit 104 and the stored data of the data holding unit 107 for addition. . The addition result is held in the data holding unit 107.

  Next, under the control of the control unit 402, the data selector 401 a selects the other input terminal and gives the addition result to the multiplier 401 b, and the same value corresponding to the two data added from the filter coefficient storage unit 105. The filter coefficient is read and supplied to the multiplier 401b. Then, the data selector 401c selects the other input terminal, the multiplication result of the multiplier 401b is given to the adder 401e via the data selector 401c, and the multiplication result of the multiplier 401b and the data selector 401d are input. The data held by the data holding unit 107 to be added is added. The addition result is held in the data holding unit 107.

  Thus, when the filter coefficient is a symmetric coefficient value with respect to the center of the impulse response length, two data multiplied by the same filter coefficient are added by the adder 401e and then multiplied by the filter coefficient by the multiplier 401b. Then, the addition of the cumulative addition value is repeated.

  Under the control of the control unit 402, the data holding unit 107 gives the held data to the adder 401e via the data selector 401d, and repeats the operation of fetching and holding the addition result within a certain period.

  As a result, the multiplication result of the added two data and the corresponding filter coefficient is cumulatively added by the adder 401e for a certain period of time and is held in the data holding unit 107. Alternatively, Q-channel output data can be obtained.

  FIG. 5 is a diagram for explaining a delay data generation operation according to the second embodiment.

  FIG. 5 shows Ich input data write control to the first delay unit 101, Ich input data read control from the first delay unit 101, and filter coefficient read control from the filter coefficient storage unit 105. Has been.

  Here, in FIG. 5, as in the case of FIG. 2 of the first embodiment, the delay amount in the first delay unit 101, that is, the number of Ich input data to the first delay unit 101 is, for example, “3”. As shown at the left end of FIG. 5, the Ich input data is written in order from the top in accordance with the tap numbers (tap1 to tapn) in the first delay unit 101.

  That is, in the case of the second embodiment, reading from the first delay unit 101 starts from a tap number that is shifted by the number of Ich input data from the reading start tap number at the time of the previous I channel calculation. Then, (start tap number) -1st data is read. As a result, the binary value of the data of the start tap number and (start tap number) -1st data is added, multiplied by the filter coefficient, and cumulative addition is performed. Thereafter, the product-sum operation described above is repeated by repeatedly reading the two data of (start tap number) +1 and (start tap number) -2.

  That is, in FIG. 5, in the first calculation, the read start position is two of the first tap number tap1 and the final tap number tapn. One data is sequentially read from the top tap number tap1 to the center tap number tap (n / 2) -1. The other data is sequentially read from the final tap number tapn to the center tap number tap (n / 2).

  In the second calculation, the fifth and fourth taps are shifted from the read start tap numbers tap1 and tapn of the previous calculation by a distance of “3” that is the delay amount in the first delay unit 101. The numbers tap5 and tap4 are read start positions. Therefore, as shown in FIG. 5, one data is sequentially read from the tap number tap5 to the center tap number tap (n / 2) -1. As shown in FIG. 5, the other data is sequentially read from the fourth tap number tap4 to the first tap number tap1, and sequentially read from the final tap number tapn to the center tap number tap (n / 2).

  Further, in the third calculation, the ninth and eighth shifts are shifted from the read start tap numbers tap5 and tap4 of the previous calculation by a distance of “3” as the delay amount in the first delay unit 101, respectively. The tap numbers tap9 and tap8 are read start positions. Therefore, as shown in FIG. 5, one data is sequentially read from the tap number tap9 to the center tap number tap (n / 2) -1. As shown in FIG. 5, the other data is sequentially read from the eighth tap number tap8 to the first tap number tap1 and sequentially read from the final tap number tapn to the center tap number tap (n / 2).

  In the filter coefficient reading control from the filter coefficient storage unit 105, the filter coefficients are similarly read from the corresponding tap numbers in the same order.

  Note that the delay data generation operation in the second delay unit 103 for the Qch input data is performed in the same manner as the delay operation in the first delay unit 101 for the Ich input data. The relationship at the time of reading of the additional delay unit 102 and the second delay unit 103 is the same as in the first embodiment.

  FIG. 6 is a time chart for explaining the switching operation between Ich input data and Qch input data according to the second embodiment.

As in FIG. 3 of the first embodiment, D _i0 , D _i1 ,..., D _in−1 , D _in indicate Ich input data. Further, D _q0 , D _q1 ,..., D _qn−1 , D _qn indicate Qch input data, and h ₀ , h ₁ ,..., H _n−1 , h _n are Ich input data, respectively. The filter coefficient corresponding to the delay amount is shown.

  In the case of the second embodiment, as shown in FIG. 6, first, the product-sum operation is performed on the Ich input data within the Ich product-sum operation time 601, and then the Qch input data within the subsequent Qch product-sum operation time 602. Since the product-sum operation is performed for, the sum of the data length obtained within the Ich product-sum operation time 601 and the data length obtained within the Qch product-sum operation time 602 becomes the data length 603 after downsampling. .

That is, in the second embodiment, first, as shown in FIG. 6, the product-sum operation with the same filter coefficient is performed on two data that integrate the same filter coefficient in the Ich input data within the Ich product-sum operation time 601. Operation, ie, (D _i0 + D _in ) × h ₀ , (D _i0 + D _in ) × h ₀ + (D _i1 + D _{i (n−1)} ) × h ₁ ,..., Σ (D _ia + D _{in− a)} × _{h a} (however, a = 0~ (n / 2 ) -1), Σ (D ia + D in-a) × h a ( however, a = 0~ (n / 2 )) is performed.

In the subsequent Qch product-sum operation time 602, similarly, the product-sum operation with the same filter coefficient for two data that integrate the same filter coefficient in the Qch input data, that is, (D _q0 + D _qn ) × h ₀ , (D _q0 + D _qn ) × h ₀ + (D _q1 + D _{q (n−1)} ) × h ₁ ,..., Σ (D _qa + D _qn−a ) × h _a (where a = 0 ~ (n / 2) -1) , Σ (D qa + D qn-a) × h a ( however, a = 0~ (n / 2 )) is performed.

  Therefore, also in the second embodiment, the sum of the data length obtained in the Ich product-sum operation time 601 and the data length obtained in the Qch product-sum operation time 602 is the same as in the first embodiment. Is the data length 603 after downsampling.

  As in the case of the first embodiment, the I channel output data and the Q channel output data may be output simultaneously with the end of the product-sum operation, so that the Ich product-sum operation time 601 and the Qch product-sum operation time 602 are output. The switching timing is arbitrary.

  Thus, according to the second embodiment, as in the first embodiment, the additional delay unit 102 that delays the Qch input data from the Ich input data is provided, and the product-sum operation timing of the Q channel data and the I channel data is provided. Since the product-sum operation of each delay data of I channel and Q channel and the filter coefficient is performed by using one multiplier 106a and one adder 106b in a time-sharing manner, Filtering can be performed on each of the I channel and Q channel data, which is originally desired to be processed in parallel without impairing the sampling function, and the product-sum operation unit having one multiplier and adder can be shared. Can be achieved.

  In particular, in the second embodiment, when the filter coefficient is folded at the center of the impulse response length, two data multiplied by the same filter coefficient are added by an adder, then multiplied by the filter coefficient, and then cumulative addition is performed. Thus, the number of multiplications with the filter coefficient can be reduced, and the calculation speed can be increased without using a high-speed element or the like.

  In the first and second embodiments, the additional delay unit 102 and the second delay unit 103 are separately provided. However, the present invention is not limited to this, and the additional delay unit 102 and the second delay unit 103 are provided. Of course, the delay unit 103 is constituted by one delay unit, and as one delay unit, the Qch input data is delayed from the Ich data, and the Qch data is delayed by the number of taps of the second delay unit 103. good. In this case, in reading from the additional delay unit 102 and the second delay unit 103, the additional delay unit 102 and the second delay unit 103 are treated as delay units having consecutive tap numbers, and one delay unit is used. This starts from a tap number shifted by the number of Qch input data from the read start tap number at the time of the previous Q channel calculation. For this reason, in this case, the Qch input data is read from the additional delay unit 102 or the second delay unit 103, but the present invention is substantially included in one delay unit. Additional delay means for delaying the Qch input data from the I channel data and second delay means for delaying the Qch input data delayed by the additional delay means are the same.

  The downsampling FIR filter apparatus according to the present invention requires only one product-sum operation unit that performs filtering processing of two channel data orthogonal to each other, and in particular, the filter coefficient is symmetrical with respect to the center of the impulse response length. In the case of the coefficient value, there is an effect that the operation speed can be increased, and it is useful as an FIR type digital filter used for an A / D converter or the like.

The block diagram which shows the structure of the downsampling FIR filter apparatus which concerns on Embodiment 1 of this invention. The figure explaining the production | generation operation | movement of the delay data based on this Embodiment 1. Time chart for explaining the switching operation of Ich input data and Qch input data according to the first embodiment The block diagram which shows the structure of the downsampling FIR filter apparatus which concerns on Embodiment 2 of this invention. The figure explaining the production | generation operation | movement of the delay data based on this Embodiment 2. Time chart for explaining the switching operation of Ich input data and Qch input data according to the second embodiment Block diagram showing a configuration example of a conventional downsampling FIR filter device

Explanation of symbols

100, 400 Downsampling FIR filter device 101 First delay unit 102 Additional delay unit 103 Second delay unit 104 Data selection unit 105 Filter coefficient storage unit 106, 401 Product-sum operation unit 106a, 401b Multiplier 106b, 401e Adder 107 Data holding unit 108, 402 Control unit 401a, 401c, 401d Data selector

Claims (7)

A down-sampling FIR filter device that integrates, accumulates and outputs filter coefficients corresponding to respective delay amounts with respect to mutually orthogonal I channel data and Q channel data,
First delay means for delaying the I channel data;
Additional delay means for delaying the Q channel data from the I channel data;
Second delay means for delaying the Q channel data delayed by the additional delay means;
Selecting means for selecting and outputting the delay data read from the first delay means and the delay data read from the second delay means;
Filter coefficient storage means for storing the filter coefficient;
For each of the I channel data or the Q channel data output from the selection unit, the filter coefficient corresponding to the delay amount in the first delay unit or the delay amount in the second delay unit is stored in the filter coefficient. Product-sum operation means for reading and multiplying from the means, and accumulating and outputting each multiplication result; and
A downsampling FIR filter device. The downsampling FIR filter device according to claim 1.
The filter coefficient is a coefficient value symmetrical with respect to the center of the impulse response length;
The product-sum operation means adds two data to be multiplied by the same filter coefficient in the I channel data output from the selection means, and multiplies the same filter coefficient in the Q channel data. Two data are added, and the same filter coefficient corresponding to the delay amount in the first delay means or the delay amount in the second delay means is stored in the filter coefficient for each of the two added data A down-sampling FIR filter device that performs multiplication by reading from the means, cumulatively adding the respective multiplication results, and outputting the result. The downsampling FIR filter device according to claim 1 or 2,
The second delay means sequentially writes the Q channel data in the order of the tap numbers,
The downsampling FIR filter device, wherein the additional delay means sequentially writes the Q channel data in the order of the tap numbers when the second delay means has written all the Q channel data in the order of the tap numbers. The downsampling FIR filter device according to claim 1 or 2,
The down-sampling FIR filter device, wherein the second delay means and the additional delay means sequentially write the Q channel data in the order of their tap numbers. In the downsampling FIR filter device according to any one of claims 1 to 4,
The additional delay means includes
A downsampling FIR filter device comprising delay means for the number of Q channel data input during the product-sum operation of the I channel data by the product-sum operation means. In the downsampling FIR filter device according to any one of claims 1 to 5,
The first delay means starts the readout of the delayed I channel data from a tap number shifted by the number of the I channel input data from the read start tap number at the time of the previous I channel calculation. FIR filter device. In the downsampling FIR filter device according to any one of claims 1 to 5,
The additional delay means and the second delay means read the delayed Q channel data, assuming that the second delay means and the additional delay means have consecutive tap numbers, and the previous Q channel A downsampling FIR filter device that starts from a tap number that is shifted by the number of Q channel input data from a read start tap number at the time of calculation.

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