JP2006186547A - Timing generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a timing generating circuit which can control precisely a delay amount which makes it generate in a minute delay. <P>SOLUTION: The timing generating circuit includes a coarse delay and the minute delay connected in series, a first DLL for supplying a power supply voltage to the minute delay, and a second DLL for supplying the power supply voltage to the minute delay. The delay used as a monitor circuit in the first DLL is formed in the same circuit type as the coarse delay. Moreover, the delay used as the monitor circuit in the second DLL is formed in the same type circuit type as the minute delay. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a timing generation circuit that generates a signal having an arbitrary delay amount by using a variable delay circuit for an input signal.

  As a circuit for controlling the edge timing of a signal waveform and controlling the operation timing of an LSI or the like, there is a timing generation circuit (see, for example, Patent Document 1 or 2). This is a circuit that generates a signal having an arbitrary delay amount with respect to an input signal by using a variable delay circuit. By using this timing generation circuit, the operation timing can be accurately controlled.

  However, the variable delay circuit used in this timing generation circuit causes a delay in the delay amount due to variations in temperature, power supply voltage, and the like. A DLL (De1ay Locked Loop) circuit is used to correct this shift and to keep the delay amount constant.

  A timing generation circuit using a DLL is roughly divided into a variable delay circuit portion that controls timing in the order of ps and a DLL portion that functions to keep the delay amount output from the variable delay circuit portion constant. Normally, one DLL portion exists in the LSI or in the timing generation circuit.

  FIG. 2 shows an example of a timing generation circuit using a conventional DLL. A delay circuit (hereinafter referred to as a monitor circuit), a phase comparator, a charge pump, and a filter are provided in the DLL. The monitor circuit is a circuit that delays the basic clock from the outside serving as a reference by one cycle using a delay element similar to the variable delay circuit.

  The phase comparator compares the phases of the basic clock and the basic clock delayed by one cycle by the monitor circuit. The charge pump and the filter convert the phase difference detected by the phase comparator into a voltage, and control the power supply voltage so that the phase difference becomes zero.

  Usually, the variable delay circuit delays an input signal by a set time and outputs it. When this variable delay circuit is composed of a CMOS inverter that is a voltage-controlled delay element as shown in FIG. 3, the temperature of the element rises due to the operation, and the delay amount changes. At this time, the delay amount also changes in the monitor circuit similarly composed of the CMOS inverter, and as a result, the phase of the two signals input to the phase comparator is shifted. Then, the charge pump and the filter generate a power supply voltage that brings this phase difference close to 0 and supplies it to the variable delay circuit and the monitor circuit. In general, the relationship between the power supply voltage and the delay amount in a CMOS inverter is as shown in FIG.

  Since the variable delay circuit and the monitor circuit operate with the power supply voltage, the DLL can keep the delay generated by the variable delay circuit and the variable delay circuit constant by controlling the power supply voltage VDD.

  Conventionally, a circuit constituting a variable delay circuit generates delay by connecting CMOS inverters in multiple stages, and maintains delay accuracy by using a power supply voltage VDD adjusted by a DLL. Currently, there are demands for variable delay circuits: (1) high resolution of 100 ps or less, (2) large delay amount, and (3) small offset delay. The offset delay is a delay generated in a portion other than the delay element even when the delay amount is set to zero.

  As a delay unit for obtaining a high resolution of 100 ps or less, there is a multi-stage connection of an inverter, an additional capacitor and a switch (hereinafter referred to as a fine delay unit) as shown in FIG. When the switch is set to 0ff, the delay time per stage is Δt0f, whereas when the switch is turned on, the delay time per stage is Δt0f +100 ps. A desired delay amount can be realized by the difference in delay time. As described above, since the minute delay unit adjusts the delay amount by the capacity, a resolution of several tens of ps can be easily obtained by using an appropriate capacity.

  On the other hand, as a delay unit for obtaining a large delay amount, as shown in FIG. 6, a circuit that switches a gate delay of a CMOS inverter in multiple stages and a path without a gate delay are switched by a selector (hereinafter, coarse). (Coarse) is called a delay unit). A delay amount can be set for each selector. For example, Δt0c and Δt0c + 1ns are switched by the selector S1, and Δt0c and Δt0c + 2ns are switched by the selector S2. Although this coarse delay unit can obtain a large amount of delay, the resolution is low.

  When a variable delay circuit having a large delay amount is configured only by a minute delay unit having a high resolution, a delay element having an enormous number of stages is required. FIG. 7 shows the basic clock and the output clock of the variable delay circuit in this case. As can be seen from FIGS. 7A and 7B, even if the delay amount of the variable delay circuit is set to 0, the delay of the variable delay circuit is caused by a delay (offset delay) generated in a portion other than the delay element. The amount is not zero. Therefore, the delay amount cannot be accurately controlled.

  In order to realize the above conflicting requirements, a variable delay circuit in which a minute delay unit and a coarse delay unit are connected in series has been proposed. In order to generate a delay of, for example, 11 ns by these two delay units, a delay of 1 ns is generated by the minute delay unit, and a delay of 10 ns is generated by the coarse delay unit.

  In this case, a circuit in which 10 stages of circuits generating a delay amount of 100 ps are connected as shown in FIG. 5 is used as the minute delay unit. Thus, by setting the switch to 0 N / OFF, a delay of 0 ns to 1 ns can be generated with a resolution of 1 OOps.

  As the coarse delay unit, as shown in FIG. 6, a circuit that switches between a path that generates a delay by a delay element and a path that does not generate a delay is used. The delay amount is set in advance according to the path selected by the selector. When 0 is input to the control terminal S of the selector, a path that does not generate a delay is selected, and when 1 is input, a path that generates a delay is selected. For example, as shown in FIG. 6, if a delay of 1 ns for the selector Sl, 2 ns for the S2, 3 ns for the S3, and 4 ns for the S4 is generated, the signal input to the control terminal of the selector is changed to 0 ns with a resolution of 1 ns. A delay of ~ 10ns can be generated.

  By the above method, a delay of up to 1 ns is generated in the minute delay unit, a delay of up to 10 ns is generated in the coarse delay unit, and by combining these two, a delay of up to 11 ns can be generated in units of 100 ps. A variable delay circuit was realized.

  In addition, since the monitor circuit in the conventional DLL needs to generate a delay of one cycle of the basic clock, the selector switches between the path passing through the delay element part and the path not passing through like the coarse delay part. A delay amount was generated.

  For example, when the period of the basic clock is 10 ns, it is necessary to delay one period (10 ns) of the basic clock by the monitor circuit. However, since an offset delay occurs in a portion other than the delay element, the delay by the monitor circuit becomes larger than one cycle of the basic clock (FIG. 7 (c)).

  For this reason, even if the basic clock (a) and the clock (c) with a delay of one synchronization are input to the phase comparator, the phase difference becomes large, and the power supply voltage cannot be controlled accurately. was there.

  Therefore, as shown in FIG. 8, in addition to the first delay unit in which the delay amount is set so as to delay the basic clock by one cycle, a second delay unit in which the delay amount is set to 0 is provided. Then, the phase difference between the clocks output from the first delay unit and the second delay unit is input to the phase comparator, and the power supply voltage is controlled so that the two phase differences are zero in the charge pump and the filter. . Here, since the offset delays of the first delay unit and the second delay unit are the same, the power supply voltage can be accurately controlled without being affected by the offset delay.

USPatent No.5,684,421 Japanese Patent Laid-Open No. 2001-290555

  In the conventional timing generation circuit, the monitor circuit in the DLL has the same circuit format as the coarse delay unit of the variable delay circuit. Therefore, a large delay amount can be controlled by the power supply voltage VDD from the DLL having the monitor circuit.

  However, the minute delay portion of the variable delay circuit is also controlled using the same power supply voltage VDD. That is, the power supply voltage of the minute delay unit that must be controlled more precisely is controlled using the power supply voltage for obtaining a large delay amount. In the above example, a control voltage for controlling the monitor circuit in units of 1 ns is used to control the minute delay unit in the variable delay circuit having a resolution of 100 ps. In addition, when the power supply voltage VDD input to the variable delay circuit from the DLL is changed, the delay amount generated by the minute delay unit and the delay amount generated by the coarse delay unit may not be continuous. . Therefore, there is a problem that the amount of delay generated in the minute delay unit cannot be precisely controlled.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a timing generation circuit capable of precisely controlling a delay amount generated by a minute delay unit.

  The timing generation circuit according to the present invention includes a coarse delay unit and a micro delay unit connected in series, a first DLL that supplies a power supply voltage to the coarse delay unit, and a second DLL that supplies a power supply voltage to the micro delay unit. Have The delay unit used as the monitor circuit in the first DLL has the same circuit format as the coarse delay unit. Further, the delay unit used as the monitor circuit in the second DLL has the same circuit format as the minute delay unit. Other features of the present invention will become apparent below.

  According to the present invention, the amount of delay generated in the minute delay unit can be precisely controlled.

  FIG. 1 is a block diagram showing a timing generation circuit according to an embodiment of the present invention. This timing generation circuit generates a signal having an arbitrary delay amount with respect to a signal input using the variable delay circuit 11. The variable delay circuit 11 includes a coarse delay unit 12 and a minute delay unit 13 connected in series.

  Further, a first DLL 14 is provided to supply the power supply voltage to the coarse delay unit 12, and a second DLL 15 is provided to supply the power supply voltage to the minute delay unit 13.

  The first DLL 14 includes a first monitor circuit 21, a first phase comparator 22, a first charge pump 23, and a first filter 24. The first monitor circuit 21 includes a first delay unit 25 and a second delay unit 26.

  The first delay unit 25 has the same circuit format as the coarse delay unit 12, and the delay amount is set so as to delay the basic clock by one period (10 ns). Specifically, the first delay unit 25 uses the circuit format shown in FIG. 6 and switches the path through which the basic clock passes through the selector so that the lOns delay amount can be obtained.

  The second delay unit 26 has the same circuit format as that of the coarse delay unit 12, and the delay amount is set so as not to delay the basic clock. Specifically, the second delay unit 26 has the same circuit configuration as the first delay unit 25, and the amount of delay is set to 0 ns by switching the path through which the basic clock passes by the selector.

  The first phase comparator 22 compares the phase of the signal generated by the first delay unit 25 with the phase of the signal generated by the second delay unit 26. At this time, since the same amount of offset delay occurs in the first delay unit 25 and the second delay unit 26, the first phase comparator 22 compares the phase difference without considering the offset delay. Can do.

  Then, the first charge pump 23 and the first filter 24 generate the power supply voltage VDD1 so that the phase difference detected by the first phase comparator 22 becomes 0, and the coarse delay unit 12, the first delay To the unit 25 and the second delay unit 26.

  Similarly, the second DLL 15 includes a second monitor circuit 31, a second phase comparator 32, a second charge pump 33 and a second filter 34. The second monitor circuit 31 includes a third delay unit 35 and a fourth delay unit 36.

  The third delay unit 35 has the same circuit format as the minute delay unit 13 and has a delay amount set so as to delay the basic clock by one period (10 ns). Specifically, the third delay unit 35 uses the circuit format shown in FIG. 5 and is connected in 100 stages in order to generate a delay of 1 Ons when the delay amount is 1 OOps per stage. Then, all the switches are set to 0N in order to generate a delay.

  The fourth delay unit 36 has the same circuit format as that of the minute delay unit 13, and the delay amount is set so as not to delay the basic clock. Specifically, the fourth delay unit 36 has the same circuit configuration as the third delay unit 35, and all the switches are set to 0FF.

  The second phase comparator 32 compares the phase of the signal generated by the third delay unit 35 with the phase of the signal generated by the fourth delay unit 36. At this time, since the same amount of offset delay occurs in the third delay unit 35 and the fourth delay unit 36, the second phase comparator 32 compares the phase difference without considering the offset delay. Can do.

  Then, the second charge pump 33 and the second filter 34 generate the power supply voltage VDD2 so that the phase difference detected by the second phase comparator 32 becomes 0, and the minute delay unit 13 and the third delay are generated. To the unit 35 and the fourth delay unit 36.

  As described above, in the timing generation circuit according to the embodiment of the present invention, the delay unit used as the monitor circuit in the first DLL has the same circuit format as the coarse delay unit, and is used as the monitor circuit in the second DLL. The delay unit to be used has the same circuit format as the minute delay unit. Thereby, the amount of delay generated in the minute delay unit can be precisely controlled.

It is a block diagram which shows the timing generation circuit which concerns on embodiment of this invention. It is a block diagram which shows the conventional timing generation circuit. It is a figure which shows an example of a voltage control type delay element. It is a figure which shows the relationship between the power supply voltage and delay amount in a CMOS inverter. It is a block diagram which shows a micro delay part. It is a block diagram which shows a coarse delay part. It is a timing chart of the basic clock and the output clock of the delay circuit. It is a block diagram which shows the conventional timing generation circuit.

Explanation of symbols

11 Variable Delay Circuit 12 Coarse Delay Unit 13 Micro Delay Unit 14 First DLL
15 Second DLL
21 1st monitor circuit 22 1st phase comparator 23 1st charge pump 24 1st filter 25 1st delay part 26 2nd delay part 31 2nd monitor circuit 32 2nd phase comparator 33 Second charge pump 34 Second filter 35 Third delay unit 36 Fourth delay unit

Claims (1)

A coarse delay section and a micro delay section connected in series;
A first DLL for supplying a power supply voltage to the coarse delay unit;
A second DLL for supplying a power supply voltage to the minute delay unit,
The first DLL is:
A first delay unit having the same circuit format as the coarse delay unit, the delay amount being set to delay the basic clock by one cycle;
A second delay unit having the same circuit format as the coarse delay unit, and a delay amount set so as not to delay the basic clock;
A first phase comparator that compares the phase of the signal generated in the first delay unit with the phase of the signal generated in the second delay unit;
A first charge pump that generates a power supply voltage such that a phase difference detected by the first phase comparator becomes 0 and supplies the power supply voltage to the coarse delay unit, the first delay unit, and the second delay unit And a first filter,
The second DLL is:
A third delay unit having the same circuit format as the minute delay unit, and a delay amount set so as to delay the basic clock by one cycle;
A fourth delay unit having the same circuit format as the minute delay unit and having a delay amount set so as not to delay the basic clock;
A second phase comparator that compares the phase of the signal generated by the third delay unit with the phase of the signal generated by the fourth delay unit;
A second charge pump that generates a power supply voltage such that a phase difference detected by the second phase comparator becomes zero and supplies the power supply voltage to the minute delay unit, the third delay unit, and the fourth delay unit And a second filter.

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