JP2006186379A - Field effect transistor and its application device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photo-relay in which a MOSFET capable of satisfying both of a low on-state resistance and a high withstand voltage as well as achieving a small output capacitance (C(gd), etc.) is used. <P>SOLUTION: This MOSFET comprises a light emitting element to which a switching controlled input signal is supplied, a photovoltaic element which receives light emitted from the light emitting element and generates direct electric power, a drain electrode, and a source electrode, and a gate electrode to which an output voltage generated by the photovoltaic element is supplied. In a photo-relay using the MOSFET, the output voltage of the photovoltaic element supplied to the gate electrode of the MOSFET is made to be equal to or higher than a withstand voltage between the source and drain electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor having a low on-resistance and a small output capacity, and an application device thereof.

  1 to 3 show a structure of a multi-resurf MOSFET, which is a conventional low on-resistance lateral field effect transistor (hereinafter referred to as a MOSFET), or a MOSFET called a super junction structure. 1 is a three-dimensional perspective view thereof, FIG. 2 is a plan view thereof, and FIGS. 3A, 3B, and 3C are line segments AA ′ and BB ′ of FIG. FIG. 5 is a cross-sectional view of the device taken along the line CC ′.

  As shown in these drawings, a p-type base layer 204 is selectively formed on the surface of a p-type semiconductor substrate 201, and a high-concentration n-type source is formed on the surface of the p-type base layer 204. A layer 205 and a high-concentration p-type contact layer 206 are selectively formed. An n-type drain layer 209 is formed on the surface of the p-type semiconductor substrate 201 so as to be separated from the p-type base layer 204. A source electrode 210 is formed on the n-type source layer 205 and the p-type contact layer 206, and a drain electrode 211 is formed on the n-type drain layer 209. A substrate electrode 212 is provided on the lower surface of the p-type semiconductor substrate 201 and is set to the same potential as the source electrode 210.

  Between the p-type base layer 204 and the n-type drain layer 209, stripe-shaped n-type semiconductor layers 202 and p-type semiconductor layers 203 are alternately arranged in the direction connecting them as drift layers. . That is, the n-type semiconductor layer 202 and the p-type semiconductor layer 203 are alternately arranged in a direction substantially perpendicular to the direction connecting the p-type base layer 204 and the n-type drain layer 209. A gate electrode 208 is formed on the surface of the p-type base layer 204 between the n-type source layer 205 and the n-type semiconductor layer 202 and the p-type semiconductor layer 203 via a gate oxide film 207.

  As described above, this type of MOSFET is characterized in that the n-type semiconductor layer 202 and the P-type semiconductor layer 203 are formed in a stripe shape as drift layers and are alternately arranged (multi-resurf structure, super junction structure). .) For this reason, since the drift layer is easily depleted and the concentration of the dose amount of the drift layer can be increased, the on-resistance can be reduced.

  However, in the configuration of the conventional low on-resistance MOSFET described above, electrons flow in the drift layer n-type semiconductor layer 202 but do not flow in the p-type semiconductor layer 203. Therefore, the effective area ratio of the n-type semiconductor layer 202 However, even if the concentration of the n-type semiconductor layer 202 is increased by increasing the concentration of the n-type semiconductor layer 202 to compensate for the reduced amount, there is a drawback that a sufficient effect cannot be expected to reduce the on-resistance of the entire device.

  In addition to the lateral MOSFET described above, a MOSFET in which the above-described multi-resurf structure (super junction structure) is applied to a vertical MOSFET is also known. However, even in such a structure, the design with a device withstand voltage of several hundred volts or less has the same drawback as the above-mentioned lateral device. Therefore, the conventional multi-resurf structure or the super junction structure can be used to improve the characteristics of a relatively low withstand voltage MOSFET. The effect of was not expected very much.

  Therefore, the present invention has been made in view of the above circumstances, and is a field effect type that can achieve low on-resistance and realize low output capacity even in the design of an element withstand voltage of relatively low withstand voltage (several tens to 100 V). An object of the present invention is to provide a transistor and an application device thereof.

  A field effect transistor according to an embodiment of the present invention includes a first conductivity type base layer provided on a substrate surface and a second conductivity type source selectively formed on the surface of the first conductivity type base layer. And a second conductivity type drain layer formed on the substrate apart from the first conductivity type base layer, and the first conductivity type base layer and the second conductivity type drain layer. A drift layer having a higher resistance than the first conductivity type base layer, and a gate electrode formed on a surface of the first conductivity type base layer via a gate insulating film. Is.

  The field effect transistor according to the embodiment of the present invention includes a first conductivity type base layer provided on the substrate surface and a second conductivity selectively formed on the surface of the first conductivity type base layer. A source layer, a second conductivity type drain layer formed on the substrate apart from the first conductivity type base layer, and a first conductivity type base layer and a second conductivity type drain layer. It has a sandwiched drift region and at least a gate layer provided so as to face the first conductivity type base layer, and realizes a high device breakdown voltage in the drift region and is added to the on state of the device A sufficient voltage is accumulated in the drift region by the gate voltage to realize a low on-resistance of the element.

  In addition, for example, the source electrode potential, the drain electrode potential, and the gate electrode are all in a heat parallel state of 0 V, and the drift layer is depleted, thereby reducing the low output capacitance (Cout) of the device. Realized simultaneously with resistance (Ron) and high breakdown voltage (Vdss).

  Furthermore, the field effect transistor according to the embodiment of the present invention includes a first conductivity type base layer provided on the surface of the substrate and a second conductivity selectively formed on the surface of the first conductivity type base layer. A source layer, a second conductivity type drain layer formed on the substrate apart from the first conductivity type base layer, and the first conductivity type base layer and the second conductivity type drain layer. And a first conductivity type drift semiconductor layer extending from the first conductivity type base layer toward the second conductivity type drain layer in the buried region, and is formed side by side with the first conductivity type drift semiconductor layer A gate electrode formed through a gate insulating film is provided to face the drift semiconductor layer of the second conductivity type.

  As described above, according to the present invention, it is possible to provide a MOSFET having a structure with low on-resistance and low output capacitance without sacrificing device breakdown voltage.

  Further, by using the MOSFET of the present invention as a photorelay, a photorelay capable of reliably turning on / off a high frequency signal can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
4 to 7 are diagrams showing the structure of a lateral field effect transistor (hereinafter, field effect transistor is abbreviated as MOSFET) according to the first embodiment of the present invention. 4 and 5 are three-dimensional perspective views, FIG. 6 is a plan view thereof, and FIGS. 7A to 7D are line segments AA ′, BB ′, CC ′ and D in FIG. It is sectional drawing which cut | disconnects and shows an element along -D '. 4 is a perspective view in which a part of the apparatus of FIG. 5 is removed. This lateral MOSFET is a type of MOSFET called a so-called multi-resurf MOSFET or super junction MOSFET.

  As shown in the figure, the substrate 1 is composed of a p-type (or n-type) silicon semiconductor 2 and a buried oxide film 3 formed on the surface thereof. A p-type base layer 4 is selectively formed on the upper surface of the buried oxide film 3. A high-concentration n-type source layer 5 and a high-concentration p-type contact layer 6 are selectively formed on the surface of the p-type base layer 4. An n-type drain layer 7 is formed on the surface of the buried oxide film 3 of the semiconductor substrate 1 so as to be separated from the p-type base layer 4. A source electrode 8 is formed on the n-type source layer 5 and the p-type contact layer 6. A drain electrode 10 is formed on the n-type drain layer 7 via a contact layer 9. A substrate electrode 11 is provided on the bottom surface of the p-type semiconductor substrate 1 and is set to the same potential as the source electrode 8.

Between the p-type base layer 4 and the n-type drain layer 7, a striped n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are formed in the direction connecting them. The n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are alternately formed in a direction perpendicular to the direction connecting the p-type base layer 4 and the n-type drain layer 7. Here, the dose amount of the p-type drift semiconductor layer 13 is in the range of 1.0 × 10 ^{11 to} 6.0 × 10 ¹³ cm ⁻² . In addition, the repetition pitch of the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 is between 0.01 μm and 5 μm. When the impurity dose of the n-type drift semiconductor layer 12 or the p-type drift semiconductor layer 13 is Φ and the stripe width is W,
Φ × W ≦ 1 × 10 ⁸ (cm ⁻¹ )
Have the relationship

  Next, as shown in FIG. 4, the surface of the active layer composed of the n-type source layer 4, the n-type drift semiconductor layer 12, the p-type drift semiconductor layer 13 and the n-type drain layer 7 is interposed via a gate oxide film 14. A gate electrode 15 is formed. The gate oxide film 14 is the surface of the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13, and has a film thickness of 16 at the end of the n-type drain layer 7 side and the surface of the n-type drain layer 7. Is getting bigger. The gate electrode 15 covers this stepped portion.

  A characteristic part of the lateral MOSFET of the present embodiment is that the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are formed at positions in contact with the gate oxide film, or the gate oxide film is on the drift layer. It covers at least half or more, or covers the entire drift layer and part of the drain layer. The n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are designed so as to improve the elongation of the depletion layer when turned off. At the same time, it is designed to reduce the capacitance between the gate and the drain in a thermal equilibrium state when the gate voltage is 0V.

  For example, by setting the thickness of the buried oxide film 3 to 3 μm and the thickness of the active layer formed on the oxide film to 1 μm or less (for example, 0.1 μmm), the output power is high and the on-resistance is small. It is possible to realize a device breakdown voltage. Here, the active layer includes a p-type base layer 4, an n-type drain layer 7, an n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 formed therebetween. Further, by designing the drain-side gate oxide film to be 2 to 10 times thicker, it is possible to realize a device having a higher breakdown voltage.

  As described above, the lateral MOSFET according to the present embodiment is characterized in that the stripe n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are alternately arranged in parallel as the drift layer. It is also possible to optimize the elongation of the depletion layer at the gate portion. Therefore, it is possible to increase the breakdown voltage of the element and reduce the capacitance between the gate and drain layers.

  8 to 14 are a perspective view and a side sectional view showing a modification of the lateral MOSFET of the present invention shown in FIGS. In these drawings, the same parts as those in the structure of the lateral MOSFET of the present invention shown in FIGS. 4 to 7 are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described. In the lateral MOSFET shown in FIG. 8, the n-type source layer 5 and the high-concentration p-type contact layer 6 are directly formed on the buried oxide film 3 without interposing a p-type base layer. The n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are each formed in a comb shape.

  In the lateral MOSFET shown in FIG. 9, the structure of the n-type source layer 5, the high-concentration p-type contact layer 6, the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 is the same as that of the lateral MOSFET shown in FIG. is there. However, the difference is that the gate electrodes 15 and 15 ′ are provided above and below the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13.

  FIG. 10 is a perspective view showing a modification of the lateral MOSFET shown in FIG. The difference from the lateral MOSFET shown in FIG. 9 is that gate electrodes 15 and 15 ′ are provided above and below the p-type base layer 4, which provide an offset to the n-type drain layer 7, thereby A high resistance drift semiconductor layer is formed between the p-type base layer 4 and the n-type drain layer 7. The high-resistance drift semiconductor layer may be p-type, n-type, or SJ type.

  In the lateral MOSFET shown in FIG. 11, the n-type drift semiconductor layer 12 ′ and the p-type drift semiconductor layer 13 ′ are not stripes but trapezoids. Thus, the impurity concentration of the p-type drift semiconductor layer is set to be substantially higher on the source side than on the drain side. The impurity concentration of the n-type drift semiconductor layer is set to be substantially higher on the drain side than on the source side.

In the lateral MOSFET shown in FIG. 12, a P / P ⁻ / N junction is formed instead of the super junction structure including the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 as shown in FIG.

  FIG. 13 is a sectional view showing a chip structure of a lateral MOSFET. In the figure, the thickness of the buried oxide film 3 is about 3 μm, and the super junction layer or the high resistance P-type semiconductor layer 4 composed of the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 formed thereon is formed. The thickness is about 0.1 μm. A gate electrode 15 is formed on the super junction layer via an oxide film 14 having a thickness of about 0.1 μm. By forming a gate oxide film substantially the same as or thicker than the thickness of the SiSOI layer, a high breakdown voltage and a low output capacity can be realized simultaneously.

  FIG. 14 is a diagram conceptually showing the structure of the lateral MOSFET of the present invention described above.

(Second Embodiment)
15 to 18 are views showing the structure of a lateral MOSFET according to the second embodiment of the present invention. FIG. 15 is a three-dimensional perspective view, FIG. 16 is a plan view thereof, and FIGS. 17 and 18 are cross-sectional views taken along lines AA ′ and BB ′ of FIG.

  In this embodiment, an active layer comprising a p-type base layer 4, an n-type drain layer 7, an n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 formed therebetween is formed on the SOI insulating substrate 1 with pillars. It is formed in a shape. Then, both sides of the pillar-like active layer are sandwiched between the gate electrodes 15. The n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 having a super junction structure are alternately stacked in the active layer sandwiched between the gate electrodes 15. In these drawings, the same portions as those in FIGS. 4 to 6 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 19 is a cross-sectional view showing a modification of the second embodiment. This sectional view corresponds to FIG. Although the gate oxide film 14 of the vertical MOSFET shown in FIG. 17 has a constant film thickness between the source electrode 8 and the drain electrode 10, the gate oxide film 14 of the vertical MOSFET shown in FIG. As in the case of, the difference is that the thickness is increased in the vicinity of the drain electrode 10. In the figure, the same parts as those in FIG. 17 are denoted by the same reference numerals, and detailed description thereof is omitted.

(Third embodiment)
20 to 23 are three-dimensional perspective views showing the structure of the vertical trench gate MOSFET according to the third embodiment of the present invention.

  FIG. 21 is a perspective view showing a half of the vertical MOSFET shown in FIG. 20 cut in the vertical direction. As is apparent from these drawings, in this embodiment, the gate electrode has a trench structure and the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are different from the vertical MOSFET shown in FIG. The difference is that it extends in the vertical direction and is arranged in the horizontal direction.

  FIG. 22 is a view showing a modification of FIG. As shown in the figure, the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are extended in the vertical direction, but they alternately alternate from one of the two gate electrodes 15 and 15 'to the other. It differs in that it is laminated.

  Further, the vertical MOSFET shown in FIG. 23 is a view showing a modification of the vertical trench gate MOSFET shown in FIG. 20, and a part of the gate oxide film 14 has a large film thickness as in FIG. ing.

  In these drawings, the same parts as those in FIGS. 15 to 18 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  24 to 28 are modifications of the vertical trench gate MOSFET shown in FIGS.

  In the vertical trench gate MOSFET shown in FIG. 24, the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are larger than the widths of the two gate electrodes 15 and 15 ′ with respect to the FET shown in FIG. , Extending downward from the region between the electrodes. With this structure, the capacitance between the electrodes can be reduced.

     In the vertical trench gate MOSFET shown in FIG. 25, the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are extended in the vertical direction, as shown in a perspective view in which a half of the vertical trench gate MOSFET is cut in the vertical direction. Has been. However, they are different from the vertical trench gate MOSFET of FIG. 24 in that they are alternately stacked in the longitudinal direction of the two gate electrodes 15 and 15 ′. In this structure, the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 are stacked so that their longitudinal directions are orthogonal to the longitudinal direction of the trench gate electrodes 15 and 15 ′. However, the direction is not necessarily perpendicular, and may be an arbitrary angle, for example, 60 degrees. As a result, as in the case of the FET shown in FIG. 24, alignment is not required when the trench gate electrode is manufactured, so that the manufacture is facilitated.

  FIG. 27 is a perspective view showing a half of the vertical trench gate MOSFET cut in the vertical direction, similarly to FIG. In this structure, the super junction structure is not employed, but the p-type high resistance semiconductor layer 13 ′ extends deeply below the region in the depth direction of the trench gate 15.

  FIG. 28 is a perspective view showing a half of a vertical trench gate MOSFET cut in the vertical direction, similarly to FIG. This structure is different from the FET of FIG. 25 in that the upper end of the trench gate 15 in the depth direction is lower than the n-type source region 4. With this structure, the capacitance between the source and gate electrodes can be reduced, and the contact property of the source electrodes can be improved.

(Fourth embodiment)
FIG. 29 to FIG. 37 are diagrams for explaining the fourth embodiment of the present invention.

  The lateral MOSFET according to the fourth embodiment of the present invention includes two lateral MOSFETs 21 and 22 connected in series to each other on the same substrate, as shown in the plan view of FIG. Since these MOSFETs 21 and 22 are symmetric with respect to the center line BB ′, the corresponding portions are indicated by corresponding numbers with “′”. Drain electrodes 10, 10 ′ composed of substantially square aluminum pads are formed on both sides of the center line BB ′ at approximately the center of the surface of the semiconductor substrate 2. On the upper surface of the semiconductor substrate 2, source electrodes 8 and 8 ′ made of substantially square aluminum pads are formed on both sides of the center line BB ′. Between the source electrodes 8 and 8 ', a gate electrode 23 made of a substantially square or circular aluminum pad is formed.

  FIG. 30 is a plan view showing the configuration of the surface region of the semiconductor substrate 2 constituting the lateral MOSFET shown in FIG. In the surface region of the semiconductor substrate 2, drain regions 7 and 7 'are formed in a substantially rectangular region including the drain electrodes 10 and 10' shown in FIG. A source region 5 is formed around the drain regions 7 and 7 '. The source region 5 is not formed in the gate electrode 15 portion on the semiconductor substrate 2 shown in FIG. Polysilicon gate electrode pad portions 15-1 and 15-1 ′ separated from each other are formed on the surface portion of the semiconductor substrate 2 on which the gate electrode 15 is formed. The separation between the polysilicon gate electrode pad portions 15-1 and 15-1 'is performed by interposing a P ++ high concentration impurity layer or an insulating layer, for example. The reason why the polysilicon gate electrode pad portions 15-1 and 15-1 ′ are separated from each other is that the two lateral MOSFETs 21 and 22 connected in series as shown in the plan view of FIG. This is to prevent conduction in a state where no bias voltage is applied. The reason for this will be further described later.

  The boundary regions 24 and 24 'between the source region 5 and the drain regions 7 and 7' formed in the surface region of the semiconductor substrate 2 are formed in stripes as shown in FIG. These boundary regions 24 and 24 ′ meander in the upper and lower portions of the drain electrodes 10 and 10 ′ shown in FIG. 29 in order to increase the length of the boundary regions 24 and 24 ′. Further, as shown in FIG. 31, stripe-like polysilicon gate electrodes 15 having a narrower width than the source / drain boundary regions 24 and 24 ′ are wired on the surfaces of the boundary regions 24 and 24 ′. Yes. The gate electrodes 15 and 15 ′ on the boundary regions 24 and 24 ′ are connected to the common gate electrodes 15-2 and 15-2 ′ at each vertex of the meandering portion. These common gate electrodes 15-2 and 15-2 'are connected to polysilicon gate electrode pad portions 15-1 and 15-1' formed separately from each other.

  32 is a plan view showing an aluminum wiring pattern formed on the surface of each semiconductor surface region shown in FIG. On the surface of the source region 5 shown in FIG. 30, a source electrode wiring 25 extending along the peripheral portion and the center line of the semiconductor substrate 2 is formed of an aluminum layer. As shown in FIG. 30, source electrode pads 8 and 8 ′ are formed at the upper end of the source electrode wiring 25. Drain electrode pads 10 and 10 'are formed at substantially the center of the drain regions 7 and 7' shown in FIG. 30 are formed on the surfaces of the polysilicon gate electrode pad portions 15-1 and 15-1 'separated from each other as shown in FIG.

  FIGS. 33A and 33B are diagrams showing the structure of a straight line AA ′ portion that crosses the boundary region 24 of the lateral MOSFET shown in FIG. 29, where FIG. 33A is a cross-sectional view taken along the line AA ′, and FIG. FIG. As shown in FIG. 2A, in this lateral MOSFET, an oxide film 3 made of silicon oxide is formed on a silicon semiconductor substrate 2. A source region 5 and a drain region 7 are formed on the left and right sides on the oxide film 3. A p-type base layer 4 and a super junction drift layer (hereinafter referred to as SJ-type drift layer) 16 are formed between the source region 5 and the drain region 7 on the oxide film 3.

  A gate oxide film 14 is formed on the source region 5, the p-type base layer 4, the SJ-type drift layer 16 and the drain region 7. The gate oxide film 14 is formed so as to overlap a part of the source region 5 and the drain region 7. A drain electrode pad 10 and a source electrode wiring 25 are formed in portions of the source region 5 and the drain region 7 that are not covered with the gate oxide film 14.

  A polysilicon gate electrode 15 is formed on the surface portion of the gate oxide film 14. The polysilicon gate electrode 15 has a width narrower than that of the gate oxide film 14, and is shifted to the source region 5 side so as to form an offset with respect to the drain region 7. Here, the width of the offset substantially matches the width of the SJ type drift layer 16.

  FIG. 33B is a plan view showing the gate oxide film 14 and the polysilicon gate electrode 15 of FIG. As shown in this figure, the source region 5 has P + contact layers 6 disposed on both sides thereof. That is, the source regions 5 and the P + contact layers 6 are alternately arranged along the longitudinal direction of the boundary region 24. Further, the SJ type drift layer 16 is composed of an n type drift layer 12 and a p type drift layer 13 as shown in the plan view of FIG. That is, the n-type drift layer 12 and the p-type drift layer 13 are alternately arranged along the longitudinal direction of the boundary region 24.

  Examples of dimensions of each part in the lateral MOSFET having such a structure are as follows. The thickness Tsi of the SOI layer made of the source region 5, the p-type base layer 4, the SJ-type drift layer 16 and the drain region 7 formed on the oxide film 3 is 0.1 μm, and the thickness Tgate of the gate oxide film 14 is 0.14 to 0.21 μm, the thickness Tbox of the oxide film 3 formed on the silicon semiconductor substrate 2 is 3.0 μm, the width of the gate polysilicon pattern is 1.1 to 1.3 μm, and the offset length is 0.6 to 2.5 μm. The structural characteristics of this lateral MOSFET are that, firstly, the thickness Tsi of the SOI layer is an ultrathin film, and secondly, the thickness Tgate of the gate oxide film 14 is smaller than the thickness Tsi of the SOI layer. In other words, the oxide film 3 is sufficiently thick, and thirdly, the thickness Tbox of the oxide film 3 is sufficiently thick. The first feature is that even if the bias voltage of the drain region 7 is 0 V, the SJ drift layer 16 is depleted by the built-in potential in the thermal equilibrium state. Further, due to the second feature, this MOSFET is driven with a higher gate voltage. For example, when the source / drain voltage (Vdss) is 20-40V, the gate voltage (Vg) is driven at 30-60V, which is higher than the source / drain voltage (Vdss). Further, the third feature makes it possible to reduce the substrate capacity of the drain or source region.

  In the lateral MOSFET having such a structure, the output capacitance (Cout) is reduced by the effect of the depleted SJ type drift layer 16, as in the MOSFETs of the other embodiments described above, and the source region 5 and the drain region 7. The on-resistance (Ron) can be reduced. In the lateral MOSFET of this embodiment, the gate / drain capacitance (Cgd) is reduced and the source / drain breakdown voltage (Vdss) is further increased by the offset between the polysilicon gate electrode 15 and the drain region 7. Can be bigger. Since the MOSFET of this embodiment is further driven with a high gate voltage, there is an effect of mitigating an increase in on-resistance due to the offset structure. That is, in general, in an MOSFET having an offset structure, in the ON state, the channel layer formed by the gate voltage does not connect to the drain electrode due to the presence of the offset, so that the ON resistance (Ron) tends to increase. However, in the MOSFET of this embodiment, when a high gate voltage is applied, an inversion layer (or accumulation layer) is also formed in the SJ type drift layer 16 and electrons are accumulated. It was confirmed that a low on-resistance (Ron) equal to that obtained when the regions 7 were connected by the channel layer was obtained. Such an effect (the degree of improvement of Vdss and Ron when Cout is the same) increases as the thickness Tgate of the gate oxide film 14 increases and the gate voltage (Vg) increases. Was confirmed. This point will be further described later.

  34 is a plan view showing a modification of the lateral MOSFET shown in FIG. 33. FIG. 34A is a cross-sectional view taken along line AA ′ of FIG. 29, and FIG. 34B is a plan view of the vicinity thereof. In this lateral MOSFET, a P− type or N− type drift layer 18 is used instead of the SJ type drift layer 16 shown in FIG. 33. Since other structures are the same as those of the lateral MOSFET shown in FIG. 34, the same portions are denoted by the same reference numerals, and detailed description thereof is omitted.

Table 1 shows an example of dimensions of each part in the lateral MOSFET having such a structure.

  That is, the thickness Tsi of the SOI layer formed on the oxide film 3 composed of the source region 5, the p-type base layer 4, the high resistance drift layer 16 and the drain region 7 is 0.1 μm, and the thickness of the gate oxide film 14. Tgate is 0.14 to 0.21 μm, the thickness Tbox of the oxide film 3 formed on the silicon semiconductor substrate 2 is 3.0 μm, the width of the gate electrode is 1.1 to 1.3 μm, and the offset length is 0.6 to 2.5 μm. The structural characteristics of this lateral MOSFET are that, firstly, the thickness Tsi of the SOI layer is an ultrathin film, and secondly, the thickness Tgate of the gate oxide film 14 is smaller than the thickness Tsi of the SOI layer. In other words, the oxide film 3 is sufficiently thick, and thirdly, the thickness Tbox of the oxide film 3 is sufficiently thick. According to the first feature, even when the bias voltage of the drain region 7 is 0 V, the high resistance drift layer 16 is depleted by the built-in potential in the thermal equilibrium state. Further, due to the second feature, this MOSFET is driven with a higher gate voltage. For example, when the source / drain voltage (Vdss) is 20-40V, the gate voltage (Vg) is driven at 30-60V, which is higher than the source / drain voltage (Vdss). Further, the third feature makes it possible to reduce the substrate capacity of the drain or source region.

  In the lateral MOSFET having such a structure, the output capacitance (Cout) is reduced by the effect of the depleted high resistance drift layer 16 as in the MOSFETs of the other embodiments described above, and the source region 5 and the drain region 7 are reduced. The on-resistance (Ron) can be reduced. In the lateral MOSFET of this embodiment, the gate / drain capacitance (Cgd) is reduced and the source / drain breakdown voltage (Vdss) is further increased by the offset between the polysilicon gate electrode 15 and the drain region 7. Can be bigger. Since the MOSFET of this embodiment is further driven with a high gate voltage, there is an effect of mitigating an increase in on-resistance due to the offset structure. That is, in general, in an MOSFET having an offset structure, in the ON state, the channel layer formed by the gate voltage does not connect to the drain electrode due to the presence of the offset, so that the ON resistance (Ron) tends to increase. However, in the MOSFET of this embodiment, by applying a high gate voltage, an inversion layer (or accumulation layer) is formed in the high resistance drift layer 16 and electrons are accumulated. It was confirmed that a low on-resistance (Ron) equivalent to that obtained when the drain regions 7 are connected by a channel layer can be obtained. Such an effect (an improvement effect of Vdss and Ron when Cout is made the same) may become larger as the thickness Tgate of the gate oxide film 14 becomes thicker and the gate voltage (Vg) becomes higher. confirmed.

  Next, the reason why the polysilicon gate electrode pad portions 15-1 and 15-1 ′ are separated from each other at least at one location will be described. This is because, as described above, the two lateral MOSFETs 21 and 22 (FIG. 28) connected in series with each other are prevented from conducting in a state where no bias voltage is applied to the gate electrode 23. That is, in manufacturing the lateral MOSFET having the above-described SOI layer thickness Tsi which is an ultrathin film, the diffusion layer of the SOI element is generally introduced by impurity implantation or the like after the polysilicon wiring is formed. Therefore, the portion of the SOI layer facing the polysilicon wiring remains with the substrate concentration. In the case of an ultra-thin film device, it is difficult to fill the SOI portion left with this substrate concentration by lateral diffusion. When two MOSFETs as shown in FIG. 29 are used by applying a voltage to the drain and drain with a common source and gate, the Si substrate generated in the SOI layer facing the gate polysilicon wiring from the drain of one MOSFET A circuit that is electrically connected to the drain of the other MOSFET through the channel is opened. The resistance of this circuit depends on the resistance of the substrate to be used, but in the blocked state of the element, even if a small amount of current flows there is a problem in reliability. Therefore, a structure for closing the circuit generated in the SOI layer facing the gate polysilicon wiring is necessary.

  In order to provide a P + layer and an insulating groove in the SOI layer facing the gate polysilicon wiring, it is necessary to once cut the gate polysilicon wiring at that portion. Alternatively, there is a method of forming a high-concentration P + layer or an insulating groove for element isolation before forming the gate polysilicon wiring at a place where the gate polysilicon wiring is formed. The former has an advantage that it can be easily handled by a conventional process. The latter method is also possible although the number of manufacturing process steps is increased.

  FIG. 35 is a circuit diagram showing a configuration of a photorelay circuit which is an applied device of the lateral MOSFET shown in FIG. This photorelay circuit includes an LED light-emitting element 31, a photodiode array 32 that receives light from the LED light-emitting element 31 and generates a voltage, a MOSFET circuit 33 and a MOSFET circuit driven by the output voltage of the photodiode array 32 The MOS gate discharge circuit 34 is connected between 33 gate electrodes / source electrodes.

  The LED light emitting element 31 emits light by a switching input voltage of several volts applied between its input terminals 31-1 and 31-2. In the photodiode array 32, several tens of photodiodes each generating an electromotive force of 0.5 to 0.6V are connected in series, and a DC voltage of 30 to 60V is generated between both ends thereof. Two MOSFETs 35-1 and 35-2 are connected to the input terminals 31-1 and 31-2. The MOSFET circuit 33 is the lateral MOSFET shown in FIG. The MOS gate discharge circuit 34 connected between the gate electrode / source electrode of the MOSFET circuit 33 quickly discharges the electric charge charged between the gate electrode / source electrode when the MOSFET circuit 33 is switched from the on state to the off state. It is a circuit for doing. The output terminals 33-1 and 33-2 of the MOSFET circuit 33 are switching terminals of the photorelay circuit.

  Next, the operation of this photorelay circuit will be described. When a switching input voltage is applied between the input terminals 31-1 and 31-2 of the LED light emitting element 31, the LED light emitting element 31 emits light. This light is received by the photodiode array 32, and a high DC voltage is generated between both terminals of the photodiode array 32. This DC voltage is applied between the gate electrodes / source electrodes of the two MOSFETs 35-1 and 35-2 included in the MOSFET circuit 33. As a result, the two MOSFETs 35-1 and 35-2 connected in series are switched from the off state to the on state. As a result, the output terminals 33-1 and 33-2 of the MOSFET circuit 33 become conductive.

  When the switching input voltage applied between the input terminals 31-1 and 31-2 of the LED light emitting element 31 becomes zero, the LED light emitting element 31 stops emitting light. As a result, the DC voltage generated between both terminals of the photodiode array 32 also disappears. Therefore, the two MOSFETs 35-1 and 35-2 are switched from the on state to the off state. At this time, the electrification charged between the gate electrodes / source electrodes of the two MOSFETs 35-1 and 35-2 is discharged by the MOS gate discharge circuit 34. In this state, the output terminals 33-1 and 33-2 of the MOSFET circuit 33 are nonconductive.

  The lateral MOSFET for switching used in such a photorelay circuit can simultaneously realize a low output capacitance (Cout) and a low on-resistance (Ron). That is, the figure of merit (FOM) representing the high-frequency transmission characteristics of the photorelay circuit is represented by the product of the output capacitance (Cout) and the on-resistance (Ron). An FOM of 1.87 pF.OMEGA. Was achieved when the voltage / drain voltage (Vds) was 26.5 V, and 4 pF.OMEGA. The FOM of a conventional photorelay circuit used for practical use has a Vds of 40 V and a maximum of 10 pFΩ.

Table 2 shows data indicating the operating characteristics of the switching lateral MOSFET used in the photorelay circuit.

  In this table, samples A and B are 20V elements, and sample C is a 40V element. Sample Conventional is a conventional product. In the table, Voff, Ioff, and Coff are the drain-source voltage, current, and capacitance in the off state of the lateral MOSFET, respectively. Ion and Ron are the drain-source current and resistance in the on state of the lateral MOSFET, respectively. Vds and Vg are a voltage and a gate voltage applied between the drain and source of the lateral MOSFET, respectively.

  In this photorelay circuit, a high voltage is used as a gate voltage for driving the two MOSFETs 35-1 and 35-2 included in the MOSFET circuit 33, and this gate voltage is the photodiode array 32. It is not necessary to supply from the outside of the photorelay circuit. That is, since the photodiode array 32 and the MOS gate discharge circuit 34 can be housed in one package as a one-chip IC, the input voltage from the outside to the photorelay circuit may be a switching input voltage of several volts. It can be used as a low voltage IC circuit.

  FIG. 36 is a graph for explaining the relationship between the gate drive voltage of the lateral MOSFET (20 V system) shown in FIG. 29 and the element characteristics.

In FIG. 36, the on-state gate drive voltage proportional to the gate oxide film thickness (for example, the gate oxide film can be driven at a gate voltage of 30 V per 0.1 μm) is plotted on the horizontal axis, and Ron is the element breakdown voltage (Vdss ) Divided by (Vdss / Ron). Each plot NO. 90, NO. 91 and NO92 are comparisons of three MOSFET samples having different gate oxide film thicknesses and other element parameters being the same. From the figure, if Cout is the same, Vdss / Ron is better, so it can be seen that the device characteristics can be improved by increasing the gate oxide film and increasing the drive gate voltage. . Table 3 shows data of each sample shown in FIG. As can be seen from this figure, the device characteristics can be improved by designing the gate drive voltage (V) to be higher than the device breakdown voltage (Vdss). The degree of improvement becomes higher as the device breakdown voltage becomes 1, 5, 2, 4 times.

  One of the features of this lateral MOSFET is that, as described above, the SJ type drift layer 16 is depleted by the built-in potential. The condition for this is expressed by the following equation.

W <{2εS · Vbi · (Np + Nn) / qNpNn} ^0.5
W = Lp + Ln
here,
W: SJ pattern pitch Ln: n-type drift layer 12 (FIG. 32B)
Lp: width of the p-type drift layer 13 (FIG. 32B)
εS: Dielectric constant of Si semiconductor Vbi: Built-in potential between super junction and PN junction q: Element charge In the fourth embodiment described above, the two lateral MOSFETs 21 and 22 are arranged at the gate electrode 23 portion. The polysilicon gate electrodes 15-1 and 15-1 ′ to be connected are separated. However, the separation between the two lateral MOSFETs 21 and 22 is not limited to the portion of the gate electrode 23 but, for example, by surrounding each of the two lateral MOSFETs 21 and 22 with a P ++ high concentration impurity layer or an insulating layer. It may be separated.

  In the various embodiments described above, the p-type semiconductor layer is used as the SOI layer, but this semiconductor layer may be an n-type or non-doped semiconductor layer. Further, although the SOI substrate is used as the substrate, it is needless to say that a p-type semiconductor substrate may be used. In the case of an SOI substrate, since the drain and source (substrate) capacitance can be reduced, the capacitance can be further reduced as compared with the case where the SOI structure is not adopted.

  Furthermore, the p-type and n-type conductivity types may be interchanged, and in various other semiconductor elements having MOS gates such as IGBT, planar gate type, and trench gate type elements, the capacitance inside the element between the electrodes is increased. The present invention is effective in effectively reducing the electric field at the electric field concentration portion while reducing the electric field.

  In addition, it is desirable that the structure included in the present invention, such as the gate oxide film thickness, the optimum design between the gate drive voltage and the device breakdown voltage, and the SOI structure, the ultra-thin SOI structure, etc., be optimized in consideration of all However, even if not all of the structures are satisfied, the characteristics of the element can be improved by adopting each structure.

It is a three-dimensional perspective view which shows the structure of the conventional super junction MOSFET. It is a top view of the element shown in FIG. FIG. 3 is a cross-sectional view showing a cross-sectional structure of the element along line segments AA ′, BB ′, and CC ′ in FIG. 2. It is the three-dimensional perspective view which removes and partially shows the structure of MOSFET concerning the 1st Embodiment of this invention. It is a three-dimensional perspective view which similarly shows the structure of MOSFET concerning the 1st Embodiment of this invention. It is a top view which similarly shows the structure of MOSFET concerning the 1st Embodiment of this invention. It is sectional drawing which shows the cross-section of the element along AA ', BB', CC ', DD' of FIG. It is a perspective view which shows the modification of horizontal type | mold MOSFET concerning the 1st Embodiment of this invention. It is a perspective view which shows the modification of horizontal type | mold MOSFET concerning the 1st Embodiment of this invention. FIG. 10 is a perspective view showing a modification of the lateral MOSFET shown in FIG. 9. It is a perspective view which shows the modification of horizontal type | mold MOSFET concerning the 1st Embodiment of this invention. It is a perspective view which shows the modification of horizontal type | mold MOSFET concerning the 1st Embodiment of this invention. 1 is a cross-sectional view showing a chip structure of a lateral MOSFET according to a first embodiment of the present invention. 1 is a diagram conceptually showing the structure of a lateral MOSFET according to a first embodiment of the present invention. It is a three-dimensional perspective view which shows the structure of MOSFET concerning the 2nd Embodiment of this invention. It is a top view which similarly shows the structure of MOSFET concerning the 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view showing a cross-sectional structure of the element along AA ′ in FIG. 16. It is sectional drawing which similarly shows the cross-section of the element along BB 'of FIG. It is sectional drawing of MOSFET which shows the modification of the 2nd Embodiment of this invention. It is a three-dimensional perspective view which shows the structure of the element concerning the 3rd Embodiment of this invention. It is a cross-sectional three-dimensional perspective view of MOSFET which shows the modification with respect to the 3rd Embodiment of this invention. It is a cross-sectional three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a three-dimensional perspective view of MOSFET which shows the further another modification with respect to the 3rd Embodiment of this invention. It is a top view which shows the structure of the horizontal MOSFET concerning the 4th Embodiment of this invention. FIG. 30 is a plan view showing a configuration of a surface region of a semiconductor substrate 2 constituting the lateral MOSFET shown in FIG. FIG. 30 is a plan view showing a part of the lateral MOSFET shown in FIG. 29 in an enlarged manner. FIG. 30 is a plan view showing an aluminum wiring pattern formed on the surface of the lateral MOSFET shown in FIG. 29. It is AA 'sectional drawing of FIG. It is a top view which shows the modification of FIG. It is a circuit diagram which shows the structure of the photorelay circuit which is an application apparatus of horizontal type | mold MOSFET shown in FIG. FIG. 30 is a graph for explaining the relationship between the gate drive voltage and the element characteristics of the lateral MOSFET shown in FIG. 29. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... N-type silicon semiconductor 3 ... Embedded oxide film 4 ... p-type base layer 5 ... n-type source layer 6 ... p-type contact layer 7 ... n-type drain layer 8, 8 '... source electrode 9 ... contact layer DESCRIPTION OF SYMBOLS 10, 10 '... Drain electrode 11 ... Substrate electrode 12 ... N-type drift semiconductor layer 13 ... P-type drift semiconductor layer 13' ... P-type high resistance semiconductor layer 14 ... Gate oxide film 15 ... Gate electrodes 15-1, 15-1 '... Polysilicon gate electrode pad portion 16 ... Super junction drift layer 18 ... N-type drift layer 21, 22 ... Horizontal MOSFET
DESCRIPTION OF SYMBOLS 23 ... Gate electrode 24, 24 '... Boundary area | region 25 ... Source electrode wiring 31 ... LED light emitting element 31-1, 31-2 ... Input terminal 32 ... Photodiode array 33-1, 33-2 ... Output terminal 34 ... MOS gate Discharge circuit 35-1, 35-2 ... MOSFET

Claims (1)

A light emitting element to which a switching control input signal is applied;
A photovoltaic element that receives light emitted by the light emitting element and generates a DC voltage;
A field effect transistor comprising a drain electrode, a source electrode, and a gate electrode to which an output voltage of the photovoltaic element is supplied;
The photorelay characterized in that the output voltage of the photovoltaic device applied to the gate electrode of the field effect transistor is equal to or greater than the source-drain breakdown voltage of the field effect transistor.

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