JP2006186232A - Package, microwave integrated circuit, and its manufacturing method - Google Patents

Package, microwave integrated circuit, and its manufacturing method Download PDF

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JP2006186232A
JP2006186232A JP2004380464A JP2004380464A JP2006186232A JP 2006186232 A JP2006186232 A JP 2006186232A JP 2004380464 A JP2004380464 A JP 2004380464A JP 2004380464 A JP2004380464 A JP 2004380464A JP 2006186232 A JP2006186232 A JP 2006186232A
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package
component
semiconductor
manufacturing
plating
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Yasushi Wada
靖 和田
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • H01L2224/29019Shape in side view comprising protrusions or indentations at the bonding interface of the layer connector, i.e. on the surface of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301Disposition
    • H01L2224/3012Layout
    • H01L2224/3013Square or rectangular array
    • H01L2224/30131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Abstract

<P>PROBLEM TO BE SOLVED: To reduce occurrence of cracks of a semiconductor or the like by relaxing stress generated by the mismatch of a thermal expansion coefficient between the semiconductor or the like and a package. <P>SOLUTION: The package 1 is composed by providing a large number of protrusions 2 made of a metallic material having a small rigidity modulus like gold to a mounting face for a component such as the semiconductor of the package 1. When the stress due to the mismatch of the thermal expansion coefficient in between the package 1 is generated in the semiconductor 3, it is possible to reduce the occurrence of cracks of the component such as the semiconductor by relaxing the stress by the composition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体等の部品を搭載するパッケージに関し、特に、マイクロ波集積回路等に適用可能なパッケージ及びその製造方法に関する。   The present invention relates to a package on which a component such as a semiconductor is mounted, and more particularly to a package applicable to a microwave integrated circuit or the like and a manufacturing method thereof.

図9はRFモジュールの構成を示す図である。マイクロ波、ミリ波帯におけるRFモジュールは、金属パッケージ1にベアチップ構造の半導体6とマイクロ波伝送線路基板7をマルチチップ実装し、ボンディングワイヤ8により周囲の端子部9と接続することで、マイクロ波集積回路としての所望の特性を実現させている。   FIG. 9 is a diagram showing the configuration of the RF module. An RF module in the microwave and millimeter wave bands is obtained by mounting a semiconductor 6 having a bare chip structure and a microwave transmission line substrate 7 on a metal package 1 in a multichip, and connecting to a peripheral terminal portion 9 by a bonding wire 8. Desired characteristics as an integrated circuit are realized.

ところで、近年、このような高周波帯の半導体等は回路の高集積化、高電力化の要望が高まり、そのために面積は大きくなり、かつ厚みが薄くなってきている。
従って、このような構造では半導体等とパッケージとの熱膨張係数の不整合により半導体等の実装部品に応力が作用した際、当該部品にクラックの発生が起こりやすく、RFモジュールの長期信頼性、および生産の歩留まりを低下させる大きな要因となっている。
By the way, in recent years, there is an increasing demand for higher integration of circuits and higher power in such high-frequency band semiconductors and the like, so that the area is increased and the thickness is reduced.
Therefore, in such a structure, when a stress is applied to a mounted component such as a semiconductor due to mismatch of thermal expansion coefficients between the semiconductor and the package, the component is likely to crack, and the long-term reliability of the RF module, and This is a major factor that reduces the production yield.

図10は従来のパッケージに部品を搭載したRFモジュールのクラックの様子を示す図である。一例として、パッケージ5の材料の熱膨張係数が半導体6の熱膨張係数より大きい場合を考えると、RFモジュールに温度上昇が生じると、パッケージ5と半導体6の接合面には熱膨張係数の不整合に依存する応力が発生し、この応力がある限界値に達すると半導体6にクラック11が発生する。   FIG. 10 is a view showing a crack state of an RF module in which components are mounted on a conventional package. As an example, considering the case where the thermal expansion coefficient of the material of the package 5 is larger than the thermal expansion coefficient of the semiconductor 6, when the temperature rises in the RF module, the mismatch between the thermal expansion coefficients of the joint surfaces of the package 5 and the semiconductor 6 occurs. Depending on the stress, a crack 11 is generated in the semiconductor 6 when the stress reaches a certain limit value.

前述のように半導体等の実装部品への応力は、搭載用パッケージとの熱膨張係数の不整合が原因となるため、従来、金属パッケージ等の材料として搭載する半導体の熱膨張係数に近い材料を用いることでクラック対策を行っている。しかし、半導体等の熱膨張係数と同程度の金属材料は特殊金属であるため、RFモジュールのコスト面で大きな障害となる。   As mentioned above, stress on mounting components such as semiconductors is caused by mismatch in thermal expansion coefficient with the mounting package, so conventionally, a material close to the thermal expansion coefficient of the semiconductor mounted as a material such as a metal package has been used. It is used to take measures against cracks. However, since a metal material having the same thermal expansion coefficient as a semiconductor is a special metal, it becomes a major obstacle in terms of the cost of the RF module.

従って、低価格かつ加工性に優れた金属材料を用いたときでも、半導体等とパッケージの熱膨張係数の整合性に依存されず、半導体等のクラックの発生を低減させることが可能なパッケージの構造が要求される。   Therefore, even when a metal material with low cost and excellent workability is used, the structure of the package that can reduce the occurrence of cracks in the semiconductor, etc., without depending on the consistency of the thermal expansion coefficient of the semiconductor, etc. with the package Is required.

本発明の目的は、以上の課題を解決するものであり、熱膨張係数の不整合が要因となる応力が生じてもその応力を緩和させ、半導体等のクラックの発生を低減させることにある。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and is to reduce the occurrence of a crack in a semiconductor or the like by relaxing the stress even if a stress caused by a mismatch of thermal expansion coefficients occurs.

本発明は、パッケージと半導体等の搭載部品の間の熱膨張係数の不整合が要因となる応力が生じた際に、その応力を緩和させ半導体等の部品のクラックの発生を低減させる効果を有するパッケージの構造、該パッケージを使用したマイクロ波集積回路及びそれらの製造方法に係るものである。   The present invention has an effect of reducing the occurrence of cracks in a component such as a semiconductor when the stress caused by the mismatch of thermal expansion coefficients between the package and a mounted component such as a semiconductor occurs. The present invention relates to a package structure, a microwave integrated circuit using the package, and a manufacturing method thereof.

本発明のパッケージは、部品を搭載するパッケージであって、前記部品の搭載面側に、頂部に部品を搭載、固定することが可能であり、当該部品の固定面より十分小さく、前記部品の熱膨脹係数との差により発生する応力を緩和する複数の突起が設けられていることを特徴とし、前記突起は、前記部品の搭載面側に形成した凹凸と、前記凹凸を覆うパッケージ材料より剛性率の低い材料により形成し、前記凹凸は、前記部品の搭載面側の複数の溝の形成によるものであることを特徴とし、パッケージ材料に金属材料を使用し、前記凹凸を覆う前記金属材料より剛性率の低い材料は金属メッキにより形成されていることを特徴とする。更に、以上のパッケージを使用して高周波用の部品を搭載することによりマイクロ波集積回路を構成することを特徴とする。   The package of the present invention is a package on which a component is mounted. The component can be mounted and fixed on the top on the component mounting surface side, and is sufficiently smaller than the fixing surface of the component. A plurality of protrusions that relieve stress generated due to a difference from the coefficient, and the protrusions have an unevenness formed on the mounting surface side of the component and a rigidity higher than that of the package material that covers the unevenness. It is formed of a low material, and the unevenness is formed by forming a plurality of grooves on the mounting surface side of the component. A metal material is used as a package material, and the rigidity is higher than that of the metal material covering the unevenness. The low material is formed by metal plating. Furthermore, a microwave integrated circuit is configured by mounting high frequency components using the above package.

本発明のパッケージの製造方法は、部品を搭載するパッケージの製造方法であって、前記パッケージの部品の搭載面側に複数の微小な凹凸を形成する凹凸形成工程と、前記凹凸をパッケージ材料より剛性率の低い金属材料によりメッキするメッキ工程と、を含み、更に前記メッキ工程は、金の電界メッキを行う工程を含むことを特徴とする。   The method for manufacturing a package of the present invention is a method for manufacturing a package on which a component is mounted, and includes a step of forming a plurality of minute unevenness on the mounting surface side of the component of the package, and the unevenness is more rigid than the package material. A plating step of plating with a metal material having a low rate, and the plating step further includes a step of performing electroplating of gold.

本発明のマイクロ波集積回路の製造方法は、パッケージに部品を搭載したマイクロ波集積回路の製造方法であって、前記パッケージの部品の実装面側に複数の微小な凹凸を形成する凹凸形成工程と、前記凹凸をパッケージ材料より剛性率の低い金属材料によりメッキして突起を形成するメッキ工程と、前記突起の頂部に高周波用の部品を搭載し熱圧着により固定する実装工程と、を含み、更に前記メッキ工程は、金の電界メッキを行う工程を含むことを特徴とする。   A method for manufacturing a microwave integrated circuit according to the present invention is a method for manufacturing a microwave integrated circuit in which a component is mounted on a package, and includes a step of forming a plurality of minute unevenness on the mounting surface side of the component of the package, A plating step of plating the unevenness with a metal material having a lower rigidity than a package material to form a projection, and a mounting step of mounting a high-frequency component on the top of the projection and fixing by thermocompression bonding, and The plating step includes a step of performing gold electroplating.

本発明によれば、パッケージの半導体等の部品の搭載面側に、頂部に部品を搭載でき且つ前記部品の搭載、固定面より十分小さく、パッケージ材料と前記部品との熱膨脹係数との差により発生する応力を緩和する複数の突起が設けられていることから、搭載する部品とパッケージの熱膨張係数の不整合により生じるストレスを緩和することが可能であり、半導体等の部品のクラック等を防止することができる。   According to the present invention, a component can be mounted on the top side of a package on the mounting surface side of a component such as a semiconductor, and is sufficiently smaller than the mounting and fixing surface of the component, and is generated due to a difference in thermal expansion coefficient between the package material and the component. Since a plurality of protrusions that relieve stress is provided, it is possible to relieve stress caused by mismatch of thermal expansion coefficients between the mounted component and the package, and prevent cracks in components such as semiconductors. be able to.

また、パッケージと部品の熱膨張係数を一致させる必要はなくなるから、同一パッケージ内に異種材料の半導体デバイス等の部品を搭載しても信頼性を充分向上させることが可能である。   Further, since it is not necessary to make the thermal expansion coefficients of the package and the parts coincide, it is possible to sufficiently improve the reliability even if parts such as semiconductor devices of different materials are mounted in the same package.

また、パッケージ材料の熱膨張係数に関する制約が緩和されるので、パッケージ材料の選択の幅が広がり低コスト化が可能となる。   In addition, since restrictions on the thermal expansion coefficient of the package material are relaxed, the selection range of the package material is widened, and the cost can be reduced.

また、半導体等の部品搭載時のクラックの問題が解決することで、半導体等の部品全体の面積も大きくすることが出来、更なる高集積化が可能となる。   Further, by solving the problem of cracks when mounting a component such as a semiconductor, the area of the entire component such as a semiconductor can be increased, and higher integration can be achieved.

更に、本発明の突起を有するパッケージ及び該パッケージを使用したマイクロ波集積回路は、凹凸を形成したパッケージの部品搭載面に電解メッキ等でメッキする工程を経て製作することにより、凹凸の凸部の位置の突起を厚く(高く)形成することができるから、ストレスの緩和に好適な複数の突起の形成が可能であり、更に、金等の突起を有するパッケージとしても低価格で製作することが可能である。   Furthermore, the package having the projection of the present invention and the microwave integrated circuit using the package are manufactured through a process of plating the component mounting surface of the package having the projections and depressions by electrolytic plating or the like. Since the protrusions at the position can be formed thicker (higher), it is possible to form a plurality of protrusions suitable for stress relaxation, and it is also possible to manufacture a package having protrusions such as gold at a low cost. It is.

以上により本発明は搭載する半導体等の部品のみならずマイクロ波集積回路等の高周波用の部品のクラック対策においても極めて有効である。   As described above, the present invention is extremely effective in preventing cracks in not only components such as semiconductors to be mounted but also high frequency components such as microwave integrated circuits.

(構成の説明)
図1は本発明の一実施の形態のパッケージの構成を示す図である。本実施の形態では電子部品として半導体の搭載例を示すものである。図1において、1は金属材料等で構成された板状又は基板状のパッケージであり、搭載面側の周囲には図示しないカバーを係合する段差を有し、半導体等の搭載面側に該半導体等と配線可能に下部から貫通するリード電極とを有する。2はパッケージ1の半導体等の搭載面に形成され、その頂部に搭載する半導体等(部品)の下面のサイズより小さな多数の突起である。
(Description of configuration)
FIG. 1 is a diagram showing a configuration of a package according to an embodiment of the present invention. In this embodiment, an example of mounting a semiconductor as an electronic component is shown. In FIG. 1, reference numeral 1 denotes a plate-like or substrate-like package made of a metal material or the like, and has a step for engaging a cover (not shown) around the mounting surface side. It has a semiconductor etc. and a lead electrode which penetrates from the lower part so that wiring is possible. Reference numeral 2 denotes a large number of protrusions which are formed on the mounting surface of the semiconductor or the like of the package 1 and are smaller than the size of the lower surface of the semiconductor or the like (component) mounted on the top.

図2はパッケージと半導体との接合面に着目した模式図である。本実施の形態においては、突起2はパッケージ1の半導体3の搭載面に金のようにパッケージ材料より剛性率の小さな金属材料により形成され、この突起2の頂部(凸部)にベア構造等の半導体3が搭載、接合され、パッケージ1と半導体3の下面との間には僅かに間隙を有する構造でなる。   FIG. 2 is a schematic diagram focusing on the bonding surface between the package and the semiconductor. In the present embodiment, the projection 2 is formed on the mounting surface of the semiconductor 3 of the package 1 by a metal material having a lower rigidity than the package material, such as gold, and the top (projection) of the projection 2 has a bare structure or the like. The semiconductor 3 is mounted and bonded, and has a structure having a slight gap between the package 1 and the lower surface of the semiconductor 3.

この構造により半導体3とパッケージ1との熱膨張係数の不整合による応力が生じた際、その応力が緩和され半導体3のクラックの発生を低減させることが可能となる。   With this structure, when a stress is generated due to mismatch of thermal expansion coefficients between the semiconductor 3 and the package 1, the stress is relieved and the occurrence of cracks in the semiconductor 3 can be reduced.

図3は本発明のパッケージの構造、マイクロ波集積回路の製作方法を示す図である。
(1)パッケージ1の半導体搭載面の凹凸を形成する工程(凹凸形成工程)
パッケージ1の半導体搭載面に該半導体の面積に対して十分小さくかつ多数の凹凸21を形成する。例えば、パッケージの表面処理における切削加工又は押し型のプレス加工により半導体の搭載面に図3(a)に示すように凹凸21を規則的又は不規則に形成する。凹凸の形状は、例えば三角錐、三角柱、釣り鐘型、断面が台形、矩形等の形状とすることが可能である。
FIG. 3 is a view showing a package structure of the present invention and a method for manufacturing a microwave integrated circuit.
(1) Step of forming irregularities on the semiconductor mounting surface of the package 1 (irregularity forming step)
A large number of irregularities 21 that are sufficiently small with respect to the area of the semiconductor are formed on the semiconductor mounting surface of the package 1. For example, as shown in FIG. 3A, irregularities 21 are regularly or irregularly formed on the semiconductor mounting surface by cutting in the surface treatment of the package or pressing with a pressing die. The uneven shape may be, for example, a triangular pyramid, a triangular prism, a bell shape, a trapezoidal shape, a rectangular shape, or the like in cross section.

(2)パッケージ1の半導体搭載面の突起を形成する工程(メッキ工程)
次に、前記凹凸21が形成されたパッケージ1の表面に金メッキ処理を施し、図3(b)に示すように凹凸21の箇所に膜厚の厚い金の突起2を形成する。
(2) A process of forming protrusions on the semiconductor mounting surface of the package 1 (plating process)
Next, a gold plating process is performed on the surface of the package 1 on which the unevenness 21 is formed, and a thick gold protrusion 2 is formed on the unevenness 21 as shown in FIG.

凹凸21を有するパッケージ1は、電解メッキ等により金属メッキを行うと凹凸21の凸部には他の部分と比較し多くの金属が厚膜に形成される。これは電解メッキにより凹凸の凸部に電解が集中しメッキが厚く付くという現象に基づくものであり、本実施の形態では、この現象を積極的に利用して金による突起2を形成する。金の突起2は搭載される半導体等の搭載面積に対して十分小さく、かつ多数形成して半導体搭載時に直流的にも交流的にもグランド状態を害さないようにする。
(3)パッケージ1の突起の頂部に半導体を搭載し固着する工程(実装工程)
更に、図3(c)に示すように、パッケージ1の半導体搭載面の突起2の上に半導体やマイクロ波伝送線路の基板等をマルチチップ実装し熱圧着により固着する。続いて、半導体等、実装部品と周囲の電極(接続端子)とをワイヤボンディングにより電気的に接続することにより所望のマイクロ波集積回路等が構成される。
When the package 1 having the projections and depressions 21 is subjected to metal plating by electrolytic plating or the like, more metal is formed on the projections of the projections and depressions 21 than in other portions in a thick film. This is based on the phenomenon that electrolysis concentrates on the convex and concave portions of the unevenness and the plating becomes thick, and in the present embodiment, this phenomenon is actively used to form the gold protrusion 2. The gold protrusions 2 are sufficiently small with respect to the mounting area of a semiconductor or the like to be mounted, and are formed in large numbers so as not to harm the ground state in both direct and alternating currents when the semiconductor is mounted.
(3) A process of mounting and fixing a semiconductor on the top of the protrusion of the package 1 (mounting process)
Further, as shown in FIG. 3C, a semiconductor, a substrate of a microwave transmission line, or the like is mounted on the projection 2 on the semiconductor mounting surface of the package 1 and fixed by thermocompression bonding. Subsequently, a desired microwave integrated circuit or the like is configured by electrically connecting a mounting component such as a semiconductor and surrounding electrodes (connection terminals) by wire bonding.

(動作の説明)
次に、本実施の形態のパッケージ1と半導体3の熱膨張係数の不整合に対する機能に関し、例としてパッケージ1が半導体3より膨脹係数が大きい場合の半導体へ加わる応力の緩和動作について説明する。
図4は金のような剛性率の小さな金属の突起2を形成したパッケージ1に半導体3を熱圧着により搭載した状態を示す図であり、また、図5は温度上昇によるパッケージ1の膨脹した状態の動作を示す図であり、図6は温度低下によるパッケージ1の収縮した状態の動作を示す図である。
(Description of operation)
Next, with respect to the function for mismatching the thermal expansion coefficients of the package 1 and the semiconductor 3 according to the present embodiment, a stress relaxation operation applied to the semiconductor when the package 1 has a larger expansion coefficient than the semiconductor 3 will be described as an example.
FIG. 4 is a view showing a state in which a semiconductor 3 is mounted on a package 1 on which a metal protrusion 2 having a small rigidity such as gold is formed by thermocompression bonding, and FIG. 5 is an expanded state of the package 1 due to a temperature rise. FIG. 6 is a diagram showing an operation in a contracted state of the package 1 due to a temperature drop.

まず、パッケージ1に温度上昇が生じた場合、図4に示す状態から図5に示すようにパッケージ1が膨脹し、半導体3の接合面に矢印Aの方向の応力が作用する。この場合、パッケージ1と半導体3との接合面では、剛性率の小さな金属の突起2が相対的に膨脹量が少ない半導体3とがその頂部で固着されているため、図5で示すように頂部側は外側への移動が少なく引きつられて変形することにより、パッケージ1と半導体3の接合面における半導体3に加わる応力が緩和される。   First, when the temperature rises in the package 1, the package 1 expands from the state shown in FIG. 4 as shown in FIG. 5, and stress in the direction of arrow A acts on the bonding surface of the semiconductor 3. In this case, since the metal projection 2 having a small rigidity is fixed to the semiconductor 3 with a relatively small expansion amount at the top of the joint surface between the package 1 and the semiconductor 3, as shown in FIG. Since the side is pulled and deformed with little movement to the outside, the stress applied to the semiconductor 3 at the joint surface between the package 1 and the semiconductor 3 is relaxed.

次に、パッケージ1の温度が低下した場合、図4又は図5に示す状態から図6に示すようにパッケージ1が収縮し、半導体3の接合面に矢印Bの方向の応力が作用する。この場合、パッケージ1と半導体3との接合面では、剛性率の小さな金属の突起2が相対的に収縮量が少ない半導体3とがその頂部で固着されているため、図6で示すように頂部側は内側への移動が少なく引き連られて変形することにより、パッケージ1と半導体3の接合面における半導体3に加わる応力が緩和される。   Next, when the temperature of the package 1 decreases, the package 1 contracts as shown in FIG. 6 from the state shown in FIG. 4 or 5, and stress in the direction of arrow B acts on the bonding surface of the semiconductor 3. In this case, since the metal protrusion 2 having a small rigidity is fixed to the semiconductor 3 having a relatively small amount of contraction at the top of the joint surface between the package 1 and the semiconductor 3, as shown in FIG. The side is deformed by being pulled inward with little movement inward, so that the stress applied to the semiconductor 3 at the bonding surface between the package 1 and the semiconductor 3 is relaxed.

以上のように、半導体3に何れの方向の応力が作用するときでも、剛性率の小さい金属の突起4が変形することによりパッケージ1と半導体3の接合面の応力が緩和される。   As described above, when the stress in any direction acts on the semiconductor 3, the stress on the joint surface between the package 1 and the semiconductor 3 is relieved by the deformation of the metal protrusion 4 having a small rigidity.

従って、剛性率の小さな金属の突起2が熱膨張係数の不整合により生じるパッケージ1と半導体3の接合面での応力が緩和され、半導体のクラックの発生が抑制される。   Therefore, the stress at the joint surface between the package 1 and the semiconductor 3 caused by the mismatch of the thermal expansion coefficients of the metal protrusions 2 having a small rigidity is alleviated, and the occurrence of cracks in the semiconductor is suppressed.

(発明の他の実施の形態)
以上の実施の形態ではパッケージ1の半導体搭載面に半導体の接合面と比較して小さい多数の凹凸に基づく多数の突起を形成した例を説明したが、このような突起としては他の形状を採用することが可能である。
(Another embodiment of the invention)
In the above embodiment, the example in which a large number of projections based on a large number of projections and depressions smaller than the bonding surface of the semiconductor are formed on the semiconductor mounting surface of the package 1, but other shapes are adopted as such projections. Is possible.

図7は本発明の他の実施の形態のパッケージを示す図である。本実施の形態ではパッケージの半導体等の搭載面側に隣接する山脈状の複数の突起4を形成したものである。パッケージへ搭載する半導体等のサイズの縦横比が大きくなり、長辺方向(長手方向)等の一方向への応力緩和が必要なときに適しており、当該方向に対して直角な方向の溝による凹凸をパッケージ1上に形成することにより、その方向の熱膨張係数による応力を緩和するように構成することが可能である。   FIG. 7 is a view showing a package according to another embodiment of the present invention. In the present embodiment, a plurality of mountain-shaped projections 4 adjacent to the mounting surface side of the package, such as a semiconductor, are formed. This is suitable when the aspect ratio of the size of the semiconductor to be mounted on the package is large and stress relaxation in one direction such as the long side direction (longitudinal direction) is required. By forming unevenness on the package 1, it is possible to reduce the stress due to the coefficient of thermal expansion in that direction.

図8は本発明の更に他の実施の形態のパッケージを示す図である。溝形状により形成した突起4を溝方向に複数に分断することにより短辺方向の応力緩和をも可能にしたものである。   FIG. 8 is a view showing a package according to still another embodiment of the present invention. The protrusion 4 formed by the groove shape is divided into a plurality of pieces in the groove direction, thereby enabling stress relaxation in the short side direction.

何れの場合も図1に示す実施の形態と同様に、パッケージの半導体の搭載面側に予め小さい溝による凹凸を形成する工程と、その表面の金の電界メッキ等より応力を吸収する突起として形成する工程とにより実現可能である。   In any case, as in the embodiment shown in FIG. 1, a step of forming irregularities by small grooves in advance on the semiconductor mounting surface side of the package, and a protrusion that absorbs stress by electroplating gold on the surface, etc. It is realizable by the process to perform.

また、以上の実施の形態では突起を金属メッキで形成する例を説明したが、金属メッキによらずに切削やプレス加工等によりパッケージの表面に必要な高さの多数の小さな突起として直接形成することも可能である。この場合の突起はパッケージ材料と同じ剛性率を持つことになるが、その高さ、横幅、形状等の設定により半導体等の熱膨脹係数との差により発生する応力を効果的に緩和することが可能である。   Further, in the above embodiment, the example in which the protrusions are formed by metal plating has been described. However, the protrusions are directly formed as a large number of small protrusions having a necessary height on the surface of the package by cutting or pressing without using metal plating. It is also possible. In this case, the protrusion has the same rigidity as the package material, but it is possible to effectively relieve the stress generated by the difference from the thermal expansion coefficient of the semiconductor etc. by setting its height, width, shape, etc. It is.

本発明の一実施の形態のパッケージの構成を示す図である。It is a figure which shows the structure of the package of one embodiment of this invention. パッケージと半導体との接合面に着目した模式図を示す図である。It is a figure which shows the schematic diagram which paid its attention to the junction surface of a package and a semiconductor. 本発明のパッケージ及びマイクロ波集積回路の製作方法を示す図である。It is a figure which shows the manufacturing method of the package of this invention, and a microwave integrated circuit. 突起を形成したパッケージ1に半導体3を熱圧着により搭載した状態を示す図である。It is a figure which shows the state which mounted the semiconductor 3 in the package 1 in which protrusion was formed by thermocompression bonding. 温度上昇によるパッケージ1の膨脹時の動作を示す図である。It is a figure which shows the operation | movement at the time of expansion of the package 1 by a temperature rise. 温度低下によるパッケージ1の収縮時の動作を示す図である。It is a figure which shows the operation | movement at the time of shrinkage | contraction of the package 1 by a temperature fall. 本発明の他の実施の形態のパッケージを示す図である。It is a figure which shows the package of other embodiment of this invention. 本発明の他の実施の形態のパッケーを示す図である。It is a figure which shows the package of other embodiment of this invention. 従来のRFモジュールの構成を示す図である。It is a figure which shows the structure of the conventional RF module. 従来のパッケージに部品を搭載したRFモジュールのクラックの様子を示す図である。It is a figure which shows the mode of the crack of RF module which mounted components in the conventional package.

符号の説明Explanation of symbols

1、5 パッケージ
2、4 突起
3、6 半導体
7 マイクロ波伝送線路基板
8 ボンディングワイヤ
9 電極
10 リード線
11 クラック
21 凹凸
A、C 応力方向(膨脹)
B 応力方向(圧縮)
1, 5 Package 2, 4 Protrusion 3, 6 Semiconductor 7 Microwave transmission line substrate 8 Bonding wire 9 Electrode 10 Lead wire 11 Crack 21 Concavity and convexity A, C Stress direction (expansion)
B Stress direction (compression)

Claims (9)

部品を搭載するパッケージであって、前記部品の搭載面側に、頂部に部品を搭載、固定することが可能であり、当該部品の固定面より十分小さく、パッケージ材料と前記部品の熱膨脹係数との差により発生する応力を緩和する複数の突起が設けられていることを特徴とするパッケージ。   A package for mounting a component, on which a component can be mounted and fixed on the mounting surface side of the component, and is sufficiently smaller than the fixing surface of the component, and the package material and the thermal expansion coefficient of the component A package comprising a plurality of protrusions that relieve stress generated by the difference. 前記突起は、前記部品の搭載面側に形成した凹凸と、前記凹凸を覆うパッケージ材料より剛性率の低い材料により形成したことを特徴とする請求項1記載のパッケージ。   The package according to claim 1, wherein the protrusion is formed of unevenness formed on the mounting surface side of the component and a material having a lower rigidity than the package material covering the unevenness. 前記凹凸は、前記部品の搭載面側の複数の溝の形成によるものであることを特徴とする請求項2記載のパッケージ。   3. The package according to claim 2, wherein the irregularities are formed by forming a plurality of grooves on the component mounting surface side. パッケージ材料に金属材料を使用し、前記凹凸を覆う前記金属材料より剛性率の低い材料は金属メッキにより形成されていることを特徴とする請求項2又は3記載のパッケージ。   4. The package according to claim 2, wherein a metal material is used as the package material, and the material having a lower rigidity than the metal material covering the irregularities is formed by metal plating. 請求項1ないし5の何れかに記載のパッケージに高周波用の部品を搭載したことを特徴とするマイクロ波集積回路。   6. A microwave integrated circuit comprising a high-frequency component mounted on the package according to claim 1. 部品を搭載するパッケージの製造方法であって、前記パッケージの部品の搭載面側に複数の微小な凹凸を形成する凹凸形成工程と、前記凹凸をパッケージ材料より剛性率の低い金属材料によりメッキするメッキ工程と、を含むことを特徴とするパッケージの製造方法。   A manufacturing method of a package on which a component is mounted, wherein a step of forming a plurality of minute unevenness on the mounting surface side of the component of the package, and plating in which the unevenness is plated with a metal material having a lower rigidity than the package material And a process for manufacturing the package. 前記メッキ工程は、金の電界メッキを行う工程を含むことを特徴とする請求項6記載のパッケージの製造方法。   The package manufacturing method according to claim 6, wherein the plating step includes a step of performing electroplating of gold. パッケージに部品を搭載したマイクロ波集積回路の製造方法であって、前記パッケージの部品の実装面側に複数の微小な凹凸を形成する凹凸形成工程と、前記凹凸をパッケージ材料より剛性率の低い金属材料によりメッキして突起を形成するメッキ工程と、前記突起の頂部に高周波用の部品を搭載し熱圧着により固定する実装工程と、を含むことを特徴とするマイクロ波集積回路の製造方法。   A method for manufacturing a microwave integrated circuit in which a component is mounted on a package, wherein a step of forming a plurality of minute irregularities on a mounting surface side of the component of the package, and a metal whose rigidity is lower than that of a package material. A method of manufacturing a microwave integrated circuit, comprising: a plating step of plating with a material to form a protrusion; and a mounting step of mounting a high-frequency component on the top of the protrusion and fixing by thermocompression bonding. 前記メッキ工程は、金の電界メッキを行う工程を含むことを特徴とする請求項8記載のマイクロ波集積回路の製造方法。   9. The method of manufacturing a microwave integrated circuit according to claim 8, wherein the plating step includes a step of performing electroplating of gold.
JP2004380464A 2004-12-28 2004-12-28 Package, microwave integrated circuit, and its manufacturing method Pending JP2006186232A (en)

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JP2011151321A (en) * 2010-01-25 2011-08-04 Dainippon Printing Co Ltd Assembly of semiconductor element placing member and wiring conductor, semiconductor element placing substrate and method for manufacturing the same, and semiconductor element package and method for manufacturing the same
JP2016139770A (en) * 2015-01-29 2016-08-04 京セラ株式会社 Wiring board, electronic apparatus, and electronic module
WO2017018212A1 (en) * 2015-07-28 2017-02-02 京セラ株式会社 Wiring circuit board and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011151321A (en) * 2010-01-25 2011-08-04 Dainippon Printing Co Ltd Assembly of semiconductor element placing member and wiring conductor, semiconductor element placing substrate and method for manufacturing the same, and semiconductor element package and method for manufacturing the same
JP2016139770A (en) * 2015-01-29 2016-08-04 京セラ株式会社 Wiring board, electronic apparatus, and electronic module
WO2017018212A1 (en) * 2015-07-28 2017-02-02 京セラ株式会社 Wiring circuit board and electronic device
CN107851616A (en) * 2015-07-28 2018-03-27 京瓷株式会社 Circuit board and electronic installation
JPWO2017018212A1 (en) * 2015-07-28 2018-04-12 京セラ株式会社 Wiring board and electronic device
US10672697B2 (en) 2015-07-28 2020-06-02 Kyocera Corporation Wiring board and electronic package
CN107851616B (en) * 2015-07-28 2020-07-31 京瓷株式会社 Wiring substrate and electronic device

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