JP2006186192A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable the reduction in size of an element and to suppress the variation in characteristics associated with a reduction in channel width, in a transistor in which trenches are formed at a region surrounded by a source region, a drain region, and a channel region under a gate electrode which is sandwiched between the source region and the drain region, and an LDD region is formed on the surface of the trench. <P>SOLUTION: The opening 66 of a resist serving as a mask when implanting ion in order to form LDD regions is formed in a rectangular form. The opening 66 has a pair of linear edges extending towards the channel with a space in accordance with the size of the source region 42 and drain region 44 in the channel width direction thereof. The channel region 46 is formed to have a dimension that projects over the edge towards the outside in the channel widthwise direction. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a trench is formed between a source region and a drain region and a channel region under a gate, and an LDD (Lightly Doped Drain) region (low concentration diffusion region) is formed on the surface of the trench. The present invention relates to a semiconductor device including a transistor structure in which is formed and a manufacturing method thereof.

  The breakdown voltage of the transistor formed over the semiconductor substrate can be increased by adjusting the gate length and the concentration of impurities implanted into the source region and the drain region. However, when transistors with different breakdown voltage characteristics are integrated on the same semiconductor substrate, there is a problem that the element size of the medium and high breakdown voltage transistors tends to increase.

  To solve this problem, as shown in Patent Document 1 below, using a STI (Shallow Trench Isolation) technique, a source region and a drain region and a channel region under the gate electrode at a position between them are sandwiched. A configuration in which a groove is formed and an insulator is filled in the groove has been proposed.

  FIG. 6 is a schematic element plan view for explaining the structure of a conventional medium voltage transistor element using the STI structure and a manufacturing method thereof, and FIG. 7 is a corresponding schematic element sectional view. FIG. 7 is a vertical sectional view taken along line A-A ′ in FIG. 6. This transistor is an N-channel MOS transistor, and includes a source region 2 and a drain region 4, a channel region 6 located between them, and a gate electrode 8 for controlling a current flowing through the channel. Grooves 10 and 12 are formed around the source region 2, the drain region 4 and the channel region 6. A trench 10 is formed between the source region 2 and the channel region 6 and between the drain region 4 and the channel region 6, and a trench 12 for element isolation is formed surrounding the entire region. After the grooves 10 and 12 are formed, a resist is applied to the surface of the semiconductor substrate, and the resist is patterned to provide an opening 14 in a portion including the source region 2 and the drain region 4. Using this resist as a mask, impurity ions are implanted. By making the implantation direction oblique, ion implantation is also performed on the wall surface of the groove 10, and the LDD region 16 (first region 16 a) is formed on the surface of the groove 10, that is, on the wall surface and bottom surface of the groove 10. Thereafter, the trenches 10 and 12 are filled with the silicon oxide film 18. A gate electrode 8 is stacked on the channel region 6 with a gate insulating film 20 interposed therebetween. Further, after the LDD region 16 (second region 16b) is formed on the upper surfaces of the source region 2 and the drain region 4 by ion implantation, the source diffusion layer 22 and the drain diffusion layer, which are N-type diffusion layers of higher concentration, are formed. 24 is formed. These N-channel transistor structures are formed on a P-type semiconductor substrate or P well.

In the above-described transistor, the source region 2, the channel region 6, and the drain region 4 are arranged in a line. Here, the arrangement direction is referred to as a channel direction, and the direction orthogonal thereto is referred to as a channel width direction. The dimensions of the source region 2, the channel region 6 and the drain region 4 of the conventional STI structure transistor in the channel width direction are formed so as to coincide with each other, as is the case with conventional transistors that do not form grooves. Has been. On the other hand, the resist serving as a blocking layer (mask) against ion implantation for forming the LDD region 16 on the surface of the groove 10 is provided with an opening 14 whose width is narrowed in the channel region 6 as shown in FIG. That is, a convex portion 26 on the inside of the opening 14 is provided in the resist pattern in the channel region 6. The convex portion 26 is formed so as to overlap the channel region 6. This is because if a gap occurs between the edge of the opening 14 and the side surface of the channel region 6 that does not face the groove 10 due to misalignment of the photomask used for patterning the resist, ion implantation is performed on the side surface. This is because the source region 2 and the drain region 4 may be short-circuited on the side surface. In order to prevent this short circuit, a convex portion 26 is provided in the resist pattern so that no gap is generated between the edge and the channel region 6. On the other hand, the opening 14 is formed so as to include the source region 2 and the drain region 4 so that the LDD region 16 is basically formed in the entire width of the side surface of the source region 2 and the drain region 4 facing the groove 10. Is done. Incidentally, the design distance between the edge of the opening 14 and those regions, and the design overlap amount between the convex portion 26 and the channel region 6, provide a margin for misalignment of the photomask forming the opening 14. Determined in consideration.
Japanese Patent No. 3125752

  The shape of the opening 14 for forming the conventional LDD region 16 is a crank-shaped bend between the source region 2 and the channel region 6 and between the drain region 4 and the channel region 6 due to the presence of the convex portion 26. Have The width of the groove 10 is set to be large so that the bent edge does not overlap any of the source region 2, the drain region 4 and the channel region 6 due to misalignment of the photomask. For this reason, there is a problem that the transistor size is restricted from being reduced in the channel direction. In addition, after the exposure, when the resist 14 is etched to form the opening 14, the corners of the protrusions 26 are rounded, and the dimension in the channel width direction of the LDD region 16 formed on the wall surface of the channel region 6 tends to vary. Therefore, as the channel width becomes finer, there has been a problem that the characteristic variation due to the dimensional variation of the channel width increases.

  The present invention has been made to solve the above-described problem, and a semiconductor device capable of reducing the size of a transistor in the channel direction and suppressing characteristic variations caused by the reduction in the channel width. It aims at providing the manufacturing method.

  A semiconductor device according to the present invention includes a transistor structure including a source region, a drain region, and a channel region disposed under a gate electrode, and each of the regions is disposed in a line on a main surface of a semiconductor substrate, and Are separated from each other by trenches formed around the substrate and filled with an insulator, and have a lower impurity concentration than the source and drain regions along the surface of the trench between the source and drain regions and the channel region. An LDD region is formed, and the LDD region has a size corresponding to the source region and the drain region in the channel width direction, and the channel region is the source region and the drain region in the channel width direction. Sticks out beyond.

  A method of manufacturing a semiconductor device according to the present invention includes a transistor structure including a source region, a drain region, and a channel region disposed under a gate electrode, and each of the regions is aligned in the channel direction on the main surface of the semiconductor substrate. And the source region and the drain region along the surface of the trench between the source region and the drain region and the channel region, separated from each other by a trench formed around each and filled with an insulator. A method of manufacturing a semiconductor device having an LDD region having a lower impurity concentration than the source region, the drain region, and the channel region to form the groove; and Covers the main surface of the semiconductor substrate where the trench is formed, and faces the channel regions of the source region and the drain region, respectively. An injection blocking layer forming step of forming an injection blocking layer provided with an opening in a region including at least a portion; and an LDD region is formed by implanting impurities into the semiconductor substrate from the opening of the injection blocking layer. A side edge along the channel direction among the edges of the opening is formed in a straight line, and the channel region crosses the formation position of the opening in the channel width direction. It extends to the outside.

  According to the present invention, the edge of the LDD region can be formed in a straight line with respect to the direction along the channel direction, thereby reducing the width of the trench between the source region and the drain region and the channel region. The size in the channel direction can be reduced. Further, by reducing the groove width, transistor characteristics such as frequency characteristics can be improved. Further, the channel width can be reduced while suppressing the characteristic variation.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic element plan view for explaining a structure of a medium voltage transistor element according to the present embodiment using an STI structure and a manufacturing method thereof, and FIG. 2 is a corresponding schematic element sectional view. FIG. 2 is a vertical sectional view taken along line A-A ′ in FIG. 1. This transistor is an N-channel MOS transistor, and includes a source region 42, a drain region 44, a channel region 46, and a gate electrode disposed on the channel region 46, which are formed in a P-well formed on the main surface of the semiconductor substrate. 48. The channel region 46 is disposed between the source region 42 and the drain region 44, and grooves 50 and 52 are formed around the source region 42, the drain region 44, and the channel region 46. The trench 50 is formed between the source region 42 and the channel region 46 and between the drain region 44 and the channel region 46. Further, the groove 52 is formed so as to surround the entire region, and performs element isolation from surrounding elements. These grooves 50 and 52 are filled with a silicon oxide film 54 as an insulator.

  In the P well, an LDD region 56 having an impurity concentration lower than that of the source region 42 and the drain region 44 is formed along the groove 50 between the source region 42 and the channel region 46 and between the drain region 44 and the channel region 46. Is done. The LDD region 56 includes a first region 56 a along the groove 50 and a second region 56 b along the upper surfaces of the source region 42 and the drain region 44.

  On the upper surfaces of the source region 42 and the drain region 44, a source diffusion layer 58 and a drain diffusion layer 60, which are N-type diffusion layers of higher concentration, are formed on the LDD region 56 (second region 56b). A gate electrode 48 is stacked on the channel region 46 with a gate insulating film 62 interposed therebetween. Further, spacers 64 are formed on the side walls of the gate insulating film 62 and the gate electrode 48.

  By having the LDD region 56 as described above, the breakdown voltage during operation between the source region 42 and the drain region 44 can be sufficiently maintained. In addition, since the LDD region 56 is connected to the source diffusion layer 58 and the drain diffusion layer 60 having a higher concentration than these, these resistances can be reduced, and the operation speed of the transistor and the like can be suitably maintained. Will be able to.

  In the above-described transistor, the source region 42, the channel region 46, and the drain region 44 are arranged in a line, and here, the arrangement direction is referred to as a channel direction, and the direction orthogonal thereto is referred to as a channel width direction. In this semiconductor device, the dimension of the channel region 46 in the channel width direction is formed larger than the dimension of the source region 42 and the drain region 44 in the channel width direction, and the channel region 46 has the source region 42 and the drain region in the channel width direction. It protrudes outside 44. The source region 42 and the drain region 44 are formed to have the same dimension in the channel width direction.

  In an ion implantation process for forming an LDD region 56 to be described later, the resist serving as a mask is provided with an opening 66 including a source region 42 and a drain region 44 as shown in FIG. The opening 66 is formed in a rectangular shape. That is, both edges along the channel direction of the opening 66 are formed in a straight line. The channel region 46 is formed so as to protrude outward beyond the edge of this straight line.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS. 3 to 5 are schematic vertical cross-sectional views along the channel direction in the main manufacturing process of the semiconductor device.

  For example, a P-type semiconductor substrate 80 is used as the semiconductor substrate, and a thermal oxide film 82 and a silicon nitride film 84 are sequentially stacked thereon (FIG. 3A). Next, openings are provided in regions of the thermal oxide film 82 and the silicon nitride film 84 to be the grooves 50 and 52 by using a lithography technique. Then, using the thermal oxide film 82 and the silicon nitride film 84 as a mask, the semiconductor substrate 80 is etched to form the grooves 50 and 52 (FIG. 3B).

  A resist 86 is applied to the main surface of the substrate on which the grooves 50 and 52 are formed, and the resist is patterned to form the opening 66 shown in FIG. Using this resist as a mask, impurities corresponding to the N-type conductivity are implanted from an oblique direction to form the first region 56a of the LDD region 56 (FIG. 3C). Note that the design gap between the side surface of each of the source region 42 and the drain region 44 that does not face the groove 50 and the edge of the opening 66 is set according to the processing accuracy such as misalignment of patterning that forms the opening 66. Margin. For example, the dimension of the opening 66 in the channel width direction so that the LDD region 56 is formed on the entire side surface of the source region 42 and the drain region 44 facing the groove 50 even if the formation position of the opening 66 is shifted. And the gap between the edge of the opening 66 and the source region 42 and the drain region 44 is set accordingly. For example, the gap is smaller than the width of the groove 50 and can be set so that impurities are not implanted from the gap into the source region 42 and the drain region 44 by oblique incidence of ion implantation.

  Further, in this semiconductor device, the channel region 46 is formed to have a larger dimension in the channel width direction than the source region 42 and the drain region 44 as described above, and both sides along the channel direction of the opening 66 for forming the LDD region 56. Even if the edge of the channel is formed in a straight line as described above, the end of the channel region 46 is covered under the mask for the ion implantation for forming the LDD region 56. As a result, ion implantation for forming the LDD region 56 on the side surface of the end is prevented, and the LDD region 56 on the source region 42 side and the LDD region 56 on the drain region 44 side are connected via the end. This prevents the source region 42 and the drain region 44 from being short-circuited.

  After forming the first region 56a of the LDD region 56, a silicon oxide film 88 is deposited on the semiconductor substrate 80 (FIG. 4A). Here, the deposition amount of the silicon oxide film 88 is desirably set so that the surface of the silicon oxide film 88 in the grooves 50 and 52 is higher than the surface of the silicon nitride film 84. Then, using the silicon nitride film 84 as a stopper, the silicon oxide film 88 is scraped by a chemical mechanical polishing (CMP) method to selectively leave the silicon oxide film 88 in the grooves 50 and 52, which forms the grooves 50 and 52 shown in FIG. The silicon oxide film 54 to be filled is formed. Further, the silicon nitride film 84 and the thermal oxide film 82 are removed by etching (FIG. 4B).

  Further, for example, as shown in FIG. 4B, a deep well 90 and a P well 92 are formed. Next, an insulating film is stacked on the semiconductor substrate 80 and patterned to form a gate insulating film 62 at a position corresponding to the channel region 46. After the gate insulating film 62 is formed, a gate electrode film is stacked and patterned to form a gate electrode 48 disposed on the channel region 46 (FIG. 4C).

  While using the gate electrode 48 as a mask, impurities corresponding to the N-type conductivity are selectively implanted into the upper surfaces of the source region 42 and the drain region 44 to form the second region 56b of the LDD region 56 (see FIG. FIG. 5 (a)). The spacer 64 is formed by depositing a silicon oxide film on the semiconductor substrate 80 by, for example, chemical vapor deposition (CVD) and then anisotropically etching the silicon oxide film (FIG. 5B). ). Further, impurities corresponding to the N-type conductivity are selectively implanted into the upper surfaces of the source region 42 and the drain region 44 to form the source diffusion layer 58 and the drain diffusion layer 60 (FIG. 5C).

  As described above, in this semiconductor device, the channel region 46 protrudes in the channel width direction from the source region 42 and the drain region 44. For example, even if misalignment occurs in the patterning of the opening 66, the protruding amount is a position where a pair of edges along the channel direction of the opening 66 formed in a rectangle cross the channel region 46 in the channel direction. Is set to Thereby, a short circuit between the source region 42 and the drain region 44 via the LDD region 56 can be prevented. At the same time, since the edge is a straight line, it is possible to reduce the transistor size by narrowing the width of the groove 50 in the channel direction. Further, when the source region 42, the channel region 46, and the drain region 44 approach each other in the channel direction, characteristics such as high-speed operation can be improved. Further, the size of the opening 66 on the channel region 46 can be made uniform in the channel direction, and a transistor with a reduced channel width can be formed while suppressing variation in element characteristics.

It is a typical element top view explaining the structure of the medium voltage transistor element concerning this embodiment using an STI structure, and its manufacturing method. It is typical element sectional drawing explaining the structure of the intermediate voltage transistor element based on this embodiment using STI structure, and its manufacturing method. It is a typical vertical sectional view along the channel direction in the main manufacturing process of this semiconductor device. It is a typical vertical sectional view along the channel direction in the main manufacturing process of this semiconductor device. It is a typical vertical sectional view along the channel direction in the main manufacturing process of this semiconductor device. It is the typical element top view explaining the structure of the conventional medium voltage transistor element using an STI structure, and its manufacturing method. It is typical element sectional drawing explaining the structure of the conventional medium voltage transistor element using STI structure, and its manufacturing method.

Explanation of symbols

  42 source region, 44 drain region, 46 channel region, 48 gate electrode, 50, 52 groove, 54 silicon oxide film, 56 LDD region, 58 source diffusion layer, 60 drain diffusion layer, 62 gate insulating film, 64 spacer, 66 opening Part, 80 semiconductor substrate, 82 thermal oxide film, 84 silicon nitride film, 86 resist, 88 silicon oxide film.

Claims (2)

A transistor structure including a source region, a drain region, and a channel region disposed under the gate electrode, wherein each region is disposed in a line on the main surface of the semiconductor substrate, and an insulator is formed around each of the regions. A semiconductor device in which an LDD region having a lower impurity concentration than the source region and the drain region is formed along the surface of the groove between the source region, the drain region, and the channel region, separated from each other by a filled trench Because
The LDD region has a size corresponding to the source region and the drain region in the channel width direction,
The channel region protrudes outside the source region and the drain region in the channel width direction;
A semiconductor device characterized by the above. A transistor structure including a source region, a drain region, and a channel region disposed under the gate electrode, wherein each region is disposed in a line in the channel direction on the main surface of the semiconductor substrate and is formed around each of the regions. An LDD region having a lower impurity concentration than the source region and the drain region is formed along the surface of the groove between the source region, the drain region, and the channel region, separated from each other by a trench filled with an insulator. A method of manufacturing a semiconductor device comprising:
A groove forming step of forming the groove by etching around the source region, the drain region, and the channel region;
An injection blocking layer that covers the main surface of the semiconductor substrate in which the trench is formed and forms an injection blocking layer in which an opening is provided in a region including at least a portion of the source region and the drain region facing the channel region. A layer forming step;
An LDD forming step of forming an LDD region by injecting impurities into the semiconductor substrate from the opening of the injection blocking layer;
Have
Of the edges of the opening, the side edge along the channel direction is formed in a straight line,
The channel region extends across the formation position of the opening in the channel width direction to the outside thereof;
A method of manufacturing a semiconductor device.

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