KR100906051B1 - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR100906051B1
KR100906051B1 KR1020070117563A KR20070117563A KR100906051B1 KR 100906051 B1 KR100906051 B1 KR 100906051B1 KR 1020070117563 A KR1020070117563 A KR 1020070117563A KR 20070117563 A KR20070117563 A KR 20070117563A KR 100906051 B1 KR100906051 B1 KR 100906051B1
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semiconductor device
manufacturing
drain
source
poly gate
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KR20090050895A (en
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조용수
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, MOFET의 소오스/드레인 접합층을 비대칭으로 형성함으로써, DIBL이 감소하게 되어 결국 캐리어 이동을 감소시켜 성능을 개선시킬 수 있다. 또한, DIBL이 감소할 경우, 누설 전류의 증가가 차단되어 고집적 회로에서 발생되는 파워 증가가 억제되어 집적도 개선 및 공정 여유를 확보할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and by forming the source / drain junction layer of the MOFET asymmetrically, DIBL can be reduced, thereby reducing carrier movement and improving performance. In addition, when the DIBL decreases, an increase in leakage current is blocked, thereby suppressing an increase in power generated in a high density circuit, thereby improving integration and securing a process margin.

비대칭, MOSFET, 소오스/드레이 Asymmetric, MOSFET, Source / Dray

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

본 발명은 비대칭 소오스/드레인 구조를 갖는 MOSFET 반도체 소자를 제조하는 방법에 관한 것이다. The present invention relates to a method of manufacturing a MOSFET semiconductor device having an asymmetric source / drain structure.

주지된 바와 같이, MOSFET(Metal Oxide Silicon Field Effect Transistor, 이하, MOSFET라 함)는 게이트(gate) 전극, 소오스/드레인(source/drain) 전극이 절연층(dielectric layer)을 사이에 두고 실리콘 기판에 형성된 대칭적 구조를 갖는다.As is well known, MOSFETs (Metal Oxide Silicon Field Effect Transistors, hereinafter referred to as MOSFETs) include a gate electrode and a source / drain electrode on a silicon substrate with an insulating layer interposed therebetween. Have a formed symmetrical structure.

이러한 대칭적 소오스/드레인 구조는 디자인 룰(design rule)의 감소와 함께 게이트전극의 유효 채널 길이(channel length)를 감소시켜 DIBL(drain induced barrier lowing) 증가를 효과적으로 개선하지 못하게 된다. Such a symmetric source / drain structure may reduce the effective channel length of the gate electrode along with the reduction of the design rule, thereby not effectively improving the increase of the drain induced barrier lowing (DIBL).

도 1은 일반적인 반도체 소자의 MOSFET 구조를 나타낸 단면도로서, 이를 참조하여 종래의 MOSFET 제조 방법을 설명하면 다음과 같다. 1 is a cross-sectional view illustrating a MOSFET structure of a general semiconductor device, and a conventional MOSFET manufacturing method will be described with reference to the following.

즉, 반도체 기판으로서 실리콘 기판(10)에 소자분리 및 웰 공정을 진행한 후 에 기판 전면에 게이트 절연막(12)을 형성한다. 게이트 절연막(12) 위에 도프트 폴리실리콘을 증착하고 이를 패터닝하여 게이트 전극(14)을 형성한다. 그리고 게이트 절연막(12) 및 게이트 전극(14) 전면에 버퍼 절연막(buffer dielectric layer)(16)으로서 실리콘 산화막(SiO2)을 얇게 형성한다. 그 다음 LDD(Lightly Doped Drain) 임플란트 공정을 진행하여 게이트 전극(14) 양쪽 기판내에 저농도의 불순물(n-/p-)이 주입된 얕은 LDD 접합층(18)을 형성한다. 그리고 게이트 전극(14)의 버퍼 절연막(16) 측벽에 절연물질, 예컨대 실리콘 질화막(Si3N4)으로 스페이서(spacer)(20)를 형성한 후에, 소오스/드레인 임플란트 공정을 진행하여 스페이서(20) 양쪽 기판내 에 고농도의 불순물(n+/p+)이 주입된 소오스/드레인 접합층(22)을 형성한다. 이와 같이 제조된 MOSFET는 기판 표면의 채널 사이에 LDD(18) 구조의 소오스/드레인 접합층(22)을 갖으며 LDD 접합층(18) 상부에 게이트 절연막(12)을 사이에 두고 도전성을 갖는 게이트 전극(14)이 형성되어 있으며 게이트 전극(14)의 측벽에 절연물질로 이루어진 스페이서(20)가 형성되어 있다.That is, after the device isolation and the well process are performed on the silicon substrate 10 as a semiconductor substrate, the gate insulating film 12 is formed on the entire surface of the substrate. Doped polysilicon is deposited on the gate insulating layer 12 and patterned to form the gate electrode 14. A thin silicon oxide film (SiO 2 ) is formed as a buffer dielectric layer 16 over the gate insulating film 12 and the gate electrode 14. Next, a lightly doped drain (LDD) implant process is performed to form a shallow LDD junction layer 18 into which low concentrations of impurities (n− / p−) are implanted into both substrates of the gate electrode 14. After the spacer 20 is formed on the sidewall of the buffer insulating layer 16 of the gate electrode 14 by using an insulating material, for example, silicon nitride (Si 3 N 4 ), the source / drain implant process is performed to perform the spacer 20. The source / drain junction layer 22 into which high concentrations of impurities (n + / p +) are implanted is formed in both substrates. The MOSFET manufactured as described above has a source / drain junction layer 22 having an LDD 18 structure between channels on a substrate surface, and a conductive gate having a gate insulating layer 12 interposed therebetween on the LDD junction layer 18. The electrode 14 is formed and a spacer 20 made of an insulating material is formed on the sidewall of the gate electrode 14.

그러나, 상기한 바와 같이 동작되는 배경 기술에서 90㎚ 이하의 고집적화가 진행되면서 종래 MOSFET에서와 같이 제조된 대칭적 소오스/드레인 구조로 인하여 결국 누설 전류(leakage current; Ioff)를 증가시키는 요인으로 작용한다. 이를 개선하기 위한 공정으로 게이트 산화막 두께를 감소시켜 다소 해결할 수는 있었지만 역시 누설 전류의 증가 요인을 완벽하게 차단할 수는 없다. 또한 채널 길이(channel length)가 감소하여 DIBL이 증가하는 요인으로 인하여 캐리어 이동(carrier mobility)이 감소하게 됨으로써, 결국 성능(performance)이 감소하게 되는 문제점이 있다. However, in the background technology operated as described above, the high integration of 90 nm or less proceeds as a factor of increasing leakage current (Ioff) due to the symmetric source / drain structure manufactured as in the conventional MOSFET. . As a process to improve this, the thickness of the gate oxide film can be reduced to some extent, but it cannot completely block the increase factor of leakage current. In addition, carrier mobility decreases due to a decrease in channel length and an increase in DIBL, resulting in a decrease in performance.

이에, 본 발명의 기술적 과제는 상술한 바와 같은 문제점을 해결하기 위해 안출한 것으로, MOFET의 소오스/드레인 접합층을 비대칭으로 형성함으로써, DIBL이 감소하게 되어 결국 캐리어 이동을 감소시켜 성능을 개선시킬 수 있으며, 누설 전류의 증가를 차단시켜 고집적 회로에서 발생되는 파워 증가를 억제할 수 있는 반도체 소자의 제조 방법을 제공한다. Accordingly, the technical problem of the present invention is to solve the problems described above, and by forming the source / drain junction layer of the MOFET asymmetrically, the DIBL is reduced and eventually the carrier movement can be reduced to improve performance The present invention also provides a method of manufacturing a semiconductor device capable of suppressing an increase in leakage current to suppress an increase in power generated in a high integrated circuit.

본 발명의 실시예에 따른 반도체 소자의 제조 방법은, 웰 임플란트 공정이 실시된 기판에 형성된 산화막 패턴 상부에 절연물질을 형성하는 단계와, 절연물질 상부에 형성된 PR 패턴을 마스크로 식각 공정을 실시하여 비대칭의 폴리 게이트 영 역을 형성하는 단계와, 폴리 게이트 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하고, 절연물질을 선택적으로 제거하는 단계와, 산화막 패턴과 폴리 게이트가 형성된 기판에 대하여 LDD(lightly doped drain) 임플란트 공정을 진행하여 폴리 게이트 양쪽 기판내에 비대칭의 얕은 소오스/드레인 LDD 접합층을 형성하는 단계와, 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계를 포함한다. According to an embodiment of the present invention, a method of manufacturing a semiconductor device may include forming an insulating material on an oxide film pattern formed on a substrate on which a well implant process is performed, and performing an etching process using a PR pattern formed on the insulating material as a mask. Forming an asymmetric poly gate region, sequentially forming a gate oxide film and a poly gate in the poly gate region, selectively removing the insulating material, and lightly forming a LDD (lightly) substrate for the substrate having the oxide pattern and the poly gate formed thereon doped drain implantation process to form an asymmetric shallow source / drain LDD junction layer in both polygate substrates, spacers formed on the sidewalls of the polygate, and then source / drain implantation process Forming a source / drain junction layer in the substrate.

상기 절연물질은, 실리콘 질화막(Si3N4)인 것을 특징으로 한다.The insulating material is characterized in that the silicon nitride film (Si 3 N 4 ).

상기 실리콘 질화막(Si3N4)은, 140㎚∼160㎚ 범위의 두께인 것을 특징으로 한다.The silicon nitride film (Si 3 N 4 ) is characterized in that the thickness in the range of 140nm to 160nm.

상기 실리콘 질화막(Si3N4)은, 저압력 화학기상증착법(LPCVD)에 의해 형성되는 것을 특징으로 한다.The silicon nitride film Si 3 N 4 is formed by low pressure chemical vapor deposition (LPCVD).

상기 소오스 LDD 접합층의 깊이는, 상기 드레인 LDD 접합층에 비하여 25%∼35% 범위 이내로 낮게 진행하는 것을 특징으로 한다.The depth of the source LDD junction layer is characterized by advancing lower than the drain LDD junction layer within 25% to 35% range.

상기 산화막 패턴은, 30㎚∼50㎚ 범위의 길이인 것을 특징으로 한다.The oxide film pattern is characterized in that the length in the range of 30nm to 50nm.

상기 폴리 게이트는, 화학기상증착법(CVD)에 의해 형성되는 것을 특징으로 한다.The poly gate is formed by chemical vapor deposition (CVD).

상기 식각 공정은, 건식 방식인 것을 특징으로 한다.The etching step is characterized in that the dry method.

본 발명은 MOFET의 소오스/드레인 접합층을 비대칭으로 형성함으로써, DIBL이 감소하게 되어 결국 캐리어 이동을 감소시켜 성능을 개선시킬 수 있다.The present invention can asymmetrically form the source / drain junction layer of the MOFET, thereby reducing the DIBL, which in turn reduces the carrier movement, thereby improving performance.

또한, DIBL이 감소할 경우, 누설 전류의 증가가 차단되어 고집적 회로에서 발생되는 파워 증가가 억제됨으로써, 집적도 개선 및 공정 여유를 확보할 수 있는 효과가 있다.In addition, when the DIBL decreases, an increase in leakage current is blocked, thereby suppressing an increase in power generated in the integrated circuit, thereby improving integration and securing a process margin.

이하 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

도 2a 내지 도 2i는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 각 공정별 수직 단면도이다.2A to 2I are vertical cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

즉, 도 2a에 도시된 바와 같이, 반도체 기판(P-Substrate)(예컨대, 실리콘 기판)(201)에 서멀 산화막(thermal oxide)(203)을 형성한 다음에, 형성된 서멀 산 화막(203) 상부 전면에 웰 임플란트 공정(205)을 실시한다. 이때, 서멀 산화막(203)은 90㎚∼110㎚ 범위의 두께로 형성하는 것이 바람직하다. That is, as shown in FIG. 2A, a thermal oxide 203 is formed on a semiconductor substrate P-substrate (for example, a silicon substrate) 201, and then an upper portion of the thermal oxide film 203 formed. The well implant step 205 is performed on the entire surface. At this time, the thermal oxide film 203 is preferably formed to a thickness in the range of 90nm to 110nm.

다음으로, 목표로 하는 임의의 패턴으로 설계된 레티클을 이용하는 노광 공정과 현상 공정을 실시하여 전면 도포된 감광막(Photo Resist, PR)의 일부를 선택적으로 제거함으로써, 일 예로서 도 2b에 도시된 바와 같이, 서멀 산화막(203) 상부에 서멀 산화막 패턴 영역을 정의하기 위한 PR 패턴(207)을 형성한다. Next, an exposure process and a development process using a reticle designed in an arbitrary pattern of interest are performed to selectively remove a portion of the photoresist (PR) applied on the entire surface, as shown in FIG. 2B as an example. A PR pattern 207 for defining a thermal oxide film pattern region is formed on the thermal oxide film 203.

이후, 상술한 바와 같이 형성된 PR 패턴(207)을 마스크로 식각 공정(예컨대, 건식 방식)을 실시하여 서멀 산화막(203)을 선택적으로 제거하여 서멀 산화막 패턴을 형성하고, 스트리핑 공정을 실시하여 잔류하는 PR 패턴(207)을 제거한 다음에, 일 예로, 도 2c에 도시된 바와 같이 서멀 산화막(203) 상부에 저압력 화학기상증착법(Low Pressure Chemical Vapor Deposition, 이하, LPCVD라 함)을 이용하여 실리콘 질화막(Si3N4)(209)을 전면 형성한다. 여기서, 서멀 산화막 패턴은 30㎚∼50㎚ 범위의 길이로 형성하고, 실리콘 질화막(Si3N4)(209)은 140㎚∼160㎚ 범위의 두께로 형성하는 것이 바람직하다. Subsequently, the thermal oxide film 203 is selectively removed by an etching process (for example, a dry method) using the PR pattern 207 formed as described above to form a thermal oxide film pattern, and a stripping process is performed. After removing the PR pattern 207, for example, a silicon nitride film using a low pressure chemical vapor deposition method (hereinafter referred to as LPCVD) on the thermal oxide film 203 as shown in FIG. 2C. (Si 3 N 4 ) 209 is formed entirely. Here, the thermal oxide film pattern is preferably formed in a length in the range of 30 nm to 50 nm, and the silicon nitride film (Si 3 N 4 ) 209 is preferably formed in a thickness in the range of 140 nm to 160 nm.

다음에, 목표로 하는 임의의 패턴으로 설계된 레티클을 이용하는 노광 공정과 현상 공정을 실시하여 전면 도포된 PR의 일부를 선택적으로 제거함으로써, 일 예로서 도 2d에 도시된 바와 같이, 실리콘 질화막(Si3N4)(209) 상부에 폴리 게이트 영역을 정의하기 위한 PR 패턴(211)을 형성한다. Next, by selectively removing a part of the entire surface-applied PR by performing an exposure process and a development process using a reticle designed in an arbitrary pattern of interest, as shown in FIG. 2D, for example, a silicon nitride film (Si 3). A PR pattern 211 is formed on the N 4 ) 209 to define the poly gate region.

이어서, 상술한 바와 같이 형성된 PR 패턴(211)을 마스크로 식각 공정(예컨 대, 건식 방식)을 실시하여 일 예로 도 2e에 도시된 바와 같이 실리콘 질화막(Si3N4)(209)을 선택적으로 제거하여 폴리 게이트 영역을 형성하고, 스트리핑 공정을 실시하여 잔류하는 PR 패턴(211)을 제거한다. Subsequently, an etching process (for example, a dry method) is performed using the PR pattern 211 formed as described above to selectively select a silicon nitride film (Si 3 N 4 ) 209 as shown in FIG. 2E, for example. The poly gate region is removed to form a poly gate region, and a stripping process is performed to remove the remaining PR patterns 211.

다음으로, 폴리 게이트 영역이 형성된 실리콘 질화막(Si3N4)(209)에 대하여 게이트 산화막(213)을 성장시킨 후, 화학기상증착법(Chemical Vapor Deposition, 이하, CVD라 함)을 이용하여 폴리 실리콘을 도포한 다음에, 일 예로, 도 2f에 도시된 바와 같이 평탄화 공정인 CMP(Chemical Mechanical Polishing)를 실시하여 폴리 게이트(215)를 형성한다. Next, after the gate oxide film 213 is grown on the silicon nitride film (Si 3 N 4 ) 209 on which the poly gate region is formed, polysilicon is deposited using chemical vapor deposition (hereinafter, referred to as CVD). After the coating, as an example, the poly gate 215 is formed by performing chemical mechanical polishing (CMP), which is a planarization process, as shown in FIG. 2F.

이후, 폴리 게이트(215)가 형성된 실리콘 질화막(Si3N4)(209)에 대하여 식각 공정(예컨대, 습식 방식)을 실시하여 일 예로, 도 2g에 도시된 바와 같이 실리콘 질화막(Si3N4)(209)을 선택적으로 제거한다. Thereafter, an etching process (eg, a wet method) is performed on the silicon nitride film (Si 3 N 4 ) 209 on which the poly gate 215 is formed. For example, as illustrated in FIG. 2G, the silicon nitride film (Si 3 N 4) is formed. 209 is optionally removed.

다음에, 잔류하는 서멀 산화막(203)과 폴리 게이트(215)가 형성된 기판에 대하여 LDD 임플란트 공정(217)을 진행하여 일 예로, 도 2h에 도시된 바와 같이 폴리 게이트(215) 양쪽 기판내에 비대칭이 되도록 저농도의 불순물(n-/p-)이 주입된 얕은 소오스/드레인 LDD 접합층(219a, 219b)을 형성한 다음에, 잔류하는 서멀 산화막(203)을 식각공정(예컨대, 습식 방식)을 이용하여 제거한다. 이때, DIBL을 감소시키기 위하여 소오스 LDD 접합층(219a)의 깊이를 기준으로 드레인 LDD 접합층(219b)에 비하여 25%∼35% 범위 이내로 낮게 진행하는 것이 바람직하다. Next, the LDD implant process 217 is performed on the substrate on which the remaining thermal oxide film 203 and the poly gate 215 are formed. For example, as shown in FIG. 2H, asymmetry is prevented in both substrates of the poly gate 215. After forming shallow source / drain LDD junction layers 219a and 219b into which impurities (n- / p-) of low concentration are injected, the remaining thermal oxide film 203 is subjected to an etching process (for example, a wet method). To remove it. At this time, in order to reduce the DIBL, it is preferable to proceed in the range of 25% to 35% lower than the drain LDD junction layer 219b based on the depth of the source LDD junction layer 219a.

마지막으로, 절연물질, 예컨대 CVD를 이용하는 산화막 및 실리콘 질화 막(Si3N4)을 도포한 다음에, 식각 공정(예컨대, 건식 방식)을 이용하여 폴리 게이트(215)의 측벽에 스페이서(219)를 형성시킨 다음에, 소오스/드레인 임플란트 공정(221)을 진행하여 일 예로, 도 2i에 도시된 바와 같이 스페이서(219) 양쪽 기판내에 고농도의 불순물(n+/p+)이 주입된 소오스/드레인 접합층(223)을 형성한다. Finally, an oxide and silicon nitride film (Si 3 N 4 ) using an insulating material, such as CVD, is applied, and then the spacer 219 is formed on the sidewall of the poly gate 215 using an etching process (eg, a dry method). Next, the source / drain implant process 221 may be performed. For example, as illustrated in FIG. 223 is formed.

이상 설명한 바와 같이, 본 발명은 MOFET의 소오스/드레인 접합층을 비대칭으로 형성함으로써, DIBL이 감소하게 되어 결국 캐리어 이동을 감소시켜 성능을 개선시킬 수 있다. As described above, the present invention can asymmetrically form the source / drain junction layer of the MOFET, so that the DIBL is reduced, thereby reducing the carrier movement, thereby improving performance.

한편 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다. 그러므로 본 발명의 범위는 설명된 실시예에 국한되지 않으며, 후술되는 특허청구의 범위뿐만 아니라 이 특허청구의 범위와 균등한 것들에 의해 정해져야 한다.Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

도 1은 반도체 소자의 MOSFET 구조를 나타낸 단면도,1 is a cross-sectional view showing a MOSFET structure of a semiconductor device,

도 2a 내지 도 2i는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 각 공정별 수직 단면도.2A to 2I are vertical cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

201 : 반도체 기판 203 : 서멀 산화막201: semiconductor substrate 203: thermal oxide film

205 : 웰 임플란트 공정 207, 211 : PR 패턴205: Well implant process 207, 211: PR pattern

209 : 실리콘 질화막 213 : 게이트 산화막209 silicon nitride film 213 gate oxide film

215 : 폴리 게이트 217 : LDD 임플란트 공정215 poly gate 217 LDD implant process

219a : 소오스 LDD 접합층 219b : 드레인 LDD 접합층219a: source LDD junction layer 219b: drain LDD junction layer

221 : 소오스/드레인 임플란트 공정221 source / drain implant process

223 : 소오스/드레인 접합층223: source / drain bonding layer

Claims (8)

웰 임플란트 공정이 실시된 기판에 형성된 산화막 패턴 상부에 절연물질을 형성하는 단계와,Forming an insulating material on the oxide film pattern formed on the substrate subjected to the well implant process; 상기 절연물질 상부에 형성된 PR 패턴을 마스크로 식각 공정을 실시하여 비대칭의 폴리 게이트 영역을 형성하는 단계와, Forming an asymmetric poly gate region by performing an etching process using a PR pattern formed on the insulating material as a mask; 상기 폴리 게이트 영역에 게이트 산화막 및 폴리 게이트를 순차적으로 형성하고, 상기 절연물질을 선택적으로 제거하는 단계와, Sequentially forming a gate oxide film and a poly gate in the poly gate region, and selectively removing the insulating material; 상기 산화막 패턴과 폴리 게이트가 형성된 기판에 대하여 LDD(lightly doped drain) 임플란트 공정을 진행하여 상기 폴리 게이트 양쪽 기판내에 비대칭의 얕은 소오스/드레인 LDD 접합층을 형성하는 단계와,Performing a lightly doped drain (LDD) implant process on the substrate on which the oxide pattern and the poly gate are formed to form an asymmetric shallow source / drain LDD junction layer in both of the poly gate substrates; 상기 폴리 게이트의 측벽에 스페이서를 형성시킨 다음에, 소오스/드레인 임플란트 공정을 진행하여 상기 스페이서 양쪽 기판내에 소오스/드레인 접합층을 형성하는 단계Forming a spacer on the sidewalls of the poly gate, and then performing a source / drain implant process to form a source / drain junction layer in both substrates of the spacer; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 절연물질은, 실리콘 질화막(Si3N4)인 것을 특징으로 하는 반도체 소자 의 제조 방법.The insulating material is a silicon nitride film (Si 3 N 4 ) characterized in that the manufacturing method of the semiconductor device. 제 2 항에 있어서, The method of claim 2, 상기 실리콘 질화막(Si3N4)은, 140㎚∼160㎚ 범위의 두께인 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon nitride film (Si 3 N 4 ) is a thickness of the range of 140nm to 160nm manufacturing method of a semiconductor device. 제 2 항에 있어서, The method of claim 2, 상기 실리콘 질화막(Si3N4)은, 저압력 화학기상증착법(LPCVD)에 의해 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon nitride film (Si 3 N 4 ) is formed by a low pressure chemical vapor deposition (LPCVD) method of manufacturing a semiconductor device. 제 1 항에 있어서, The method of claim 1, 상기 소오스 LDD 접합층의 깊이는, 상기 드레인 LDD 접합층에 비하여 25%∼35% 범위 이내로 낮게 진행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The depth of the source LDD junction layer is lower in the range of 25% to 35% than the drain LDD junction layer, the manufacturing method of a semiconductor device. 제 1 항에 있어서, The method of claim 1, 상기 산화막 패턴은, 30㎚∼50㎚ 범위의 길이인 것을 특징으로 하는 반도체 소자의 제조 방법.The oxide film pattern is a method of manufacturing a semiconductor device, characterized in that the length in the range of 30nm to 50nm. 제 1 항에 있어서, The method of claim 1, 상기 폴리 게이트는, 화학기상증착법(CVD)에 의해 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The poly gate is a method of manufacturing a semiconductor device, characterized in that formed by chemical vapor deposition (CVD). 제 1 항에 있어서, The method of claim 1, 상기 식각 공정은, 건식 방식인 것을 특징으로 하는 반도체 소자의 제조 방법.The etching step is a method of manufacturing a semiconductor device, characterized in that the dry method.
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JPH0758131A (en) * 1993-08-13 1995-03-03 Sumitomo Electric Ind Ltd Method of manufacturing field efect transistor and its integrated circuit
KR970011616B1 (en) * 1993-10-20 1997-07-12 Lg Semicon Co Ltd Fabrication of mosfet
KR970063775A (en) * 1996-02-07 1997-09-12 문정환 Method for manufacturing semiconductor transistor device
KR0154306B1 (en) * 1995-10-31 1998-12-01 김광호 Method of fabricating mosfet

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Publication number Priority date Publication date Assignee Title
JPH0758131A (en) * 1993-08-13 1995-03-03 Sumitomo Electric Ind Ltd Method of manufacturing field efect transistor and its integrated circuit
KR970011616B1 (en) * 1993-10-20 1997-07-12 Lg Semicon Co Ltd Fabrication of mosfet
KR0154306B1 (en) * 1995-10-31 1998-12-01 김광호 Method of fabricating mosfet
KR970063775A (en) * 1996-02-07 1997-09-12 문정환 Method for manufacturing semiconductor transistor device

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