JP2006186039A - Lamination type varistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lamination type varistor of high reliability which has excellent adhesiveness between a ceramic sintered compact made of semiconductor ceramics that is a resistor exhibiting voltage nonlinearity and an internal electrode, and in which surge voltage resistance is raised. <P>SOLUTION: In the ceramic sintered compact 2 of the lamination type varistor 1 made of semiconductor ceramics that is a resistor exhibiting voltage nonlinearity, first internal electrodes 3a, 3c and second internal electrodes 3b, 3d are disposed as alternately overlapping mediating a ceramic sintered compact layer. The first internal electrodes 3a, 3c are derived onto a first end surface 2c, and the second internal electrodes 3b, 3d are derived onto a second end surface 2d. First and second external electrodes 4, 5 are formed on the first and second end surfaces 2c, 2d. The internal electrodes 3a to 3d have a plurality of vacancies 6. An effective area of the internal electrode part excepting the vacancies 6 is assumed to be within a range of 40 to 70% of an area of the internal electrode. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer varistor used for protecting against surge voltage due to electrostatic discharge or the like, and more specifically, a plurality of internal electrodes are provided in a ceramic sintered body whose resistance value is voltage non-linearity. The present invention relates to a laminated varistor.

  In semiconductor devices such as IC and LSI, digital signal processing is performed. Therefore, when a surge voltage due to electrostatic discharge or the like is applied, the semiconductor element may be destroyed or malfunction may occur. In recent years, semiconductor devices such as ICs and LSIs have been highly integrated and driven at a low voltage, and thus have a tendency to be less resistant to surge voltages. In particular, mobile communication devices such as mobile phones are directly carried by people. Therefore, since the semiconductor element is easily exposed to electrostatic discharge from the human body, there is a strong demand for reliably protecting the semiconductor element against such electrostatic discharge.

  In view of the above requirements, the following Patent Document 1 discloses a multilayer varistor shown in a front sectional view in FIG.

  In the multilayer varistor 101, a ceramic sintered body 102 whose resistance value, whose main component is ZnO, has voltage nonlinearity is used. In the ceramic sintered body 102, a plurality of internal electrodes 103a to 103d made of Pt are arranged so as to overlap with each other via a ceramic sintered body layer. The internal electrodes 103a and 103c are drawn out to one end face 102a of the ceramic sintered body 102, and the internal electrodes 103b and 103d are drawn out to the other end face 102b. External electrodes 104 and 105 are formed so as to cover the first and second end faces 102a and 102b.

  On the other hand, as an electronic component used for an application different from the multilayer varistor, the following Patent Document 2 discloses a multilayer ceramic capacitor shown in FIG. The multilayer ceramic capacitor 111 has a ceramic sintered body 112 made of dielectric ceramics. In order to take out the capacitance in the ceramic sintered body 112, the internal electrodes 113a to 113d are arranged so as to overlap with each other via the ceramic sintered body layer. The internal electrodes 113a and 113c are drawn out to the end face 112a, and the internal electrodes 113b and 113d are drawn out to the end face 112b. External electrodes 114 and 115 are formed on the end faces 112a and 112b, respectively.

In the multilayer ceramic capacitor 111, in order to improve the adhesion between the internal electrodes 113a to 113d and the ceramic sintered body layer made of dielectric ceramics, the hollow portion 116 of the internal electrodes 113a to 113d is 10 to 10 times the area of the entire internal electrode. It is formed to occupy 30%. That is, the upper and lower ceramic sintered body layers are in close contact with each other through the hollowed portion 116, and the adhesion between the internal electrodes 113a to 113d and the ceramic sintered body layer is enhanced. Here, if the ratio of the hollowed portion exceeds 30% of the total area of the internal electrode, that is, the internal electrode area surrounded by the outer edge of the internal electrode, sufficient capacitance cannot be obtained. It is described that the ratio must be 30% or less as described above.
Japanese Patent Laid-Open No. 5-283208 JP-A-5-90064

  In the multilayer varistor 101 described in Patent Document 1, surge resistance can be improved by using the ceramic sintered body 102 made of semiconductor ceramics mainly composed of ZnO and the internal electrodes 103a to 103d made of Pt. It was. However, since the ceramic sintered body made of semiconductor ceramics containing ZnO as a main component and Pt constituting the internal electrode are different materials, the adhesion between the ceramic sintered body 102 and the internal electrodes 103a to 103d is sufficient. It was not.

  Therefore, when the end face 102a, 102b of the ceramic sintered body 102 has moisture or the like invading from the interface between the internal electrodes 103a-103d and the ceramic layer, or when the external electrodes 104, 105 are formed, a wet plating method is used. The plating solution sometimes invaded. Therefore, there is a problem that the reliability of the multilayer varistor 101 is not sufficient.

  On the other hand, in the multilayer ceramic capacitor 111 described in Patent Document 2, the ceramic sintered body layer made of upper and lower dielectric ceramics is formed by setting the area of the hollowed portion in the internal electrodes 113a to 113d to a ratio of 10 to 30%. It was supposed that they could be bonded together to suppress delamination between the internal electrode and the ceramic sintered body.

  However, Patent Document 2 only describes a structure that suppresses delamination in the multilayer ceramic capacitor 111. Further, it has only been stated that sufficient electrostatic capacity cannot be obtained unless the ratio of the hollowed portion is 30% or less. That is, Patent Document 2 does not mention any other multilayer ceramic electronic component such as a multilayer varistor.

  In view of the current state of the prior art described above, the present invention has excellent adhesion between a ceramic sintered body made of semiconductor ceramics, which is a resistor exhibiting voltage nonlinearity, and an internal electrode, and has improved surge voltage resistance. In addition to this, it is to provide a laminated varistor having excellent reliability.

  According to the present invention, a ceramic sintered body having first and second end faces facing each other, the resistance value of which is voltage non-linearity, and the ceramic sintered body alternately overlap with each other via a ceramic sintered body layer. The first internal electrode is disposed on the first end surface of the ceramic sintered body, and the second internal electrode is disposed on the first end surface of the ceramic sintered body. It is drawn out to the second end surface on the opposite side, formed on the first and second end surfaces of the ceramic sintered body, and electrically connected to the first and second internal electrodes, respectively. In the multilayer varistor further including the first and second external electrodes, the internal electrode has a plurality of holes, and the area of the internal electrode portion excluding the holes is 40 to 40% of the area of the internal electrode. It is characterized by being in the range of 70%.

  In the present invention, the internal electrode is preferably formed using a material containing Pt as a main component.

  In the present invention, the material constituting the ceramic sintered body is not particularly limited, but a material mainly composed of ZnO is preferably used.

  The form of the first and second external electrodes is not particularly limited, but in a specific aspect of the present invention, the external electrode has a structure in which a plurality of conductive layers are stacked. In this case, the outermost conductive layer may be formed of an electrolytic plating film or a conductive film formed by sputtering.

  In the present invention, the first and second external electrodes may be composed of conductive films directly formed by sputtering on the first and second end faces of the ceramic sintered body.

  In the multilayer varistor according to the present invention, in the first and second internal electrodes, the ratio of the area of the internal electrode portion excluding the plurality of holes is in the range of 40 to 70% of the internal electrode. The first and second internal electrodes overlap with a sufficient area through the ceramic sintered body layer. Therefore, sufficient surge resistance is ensured. Moreover, since the plurality of holes are provided, the ceramic sintered body layer above the internal electrode and the ceramic sintered body layer below are integrated at the hole portion, and the internal electrode and the ceramic sintered body layer Can be effectively improved and delamination can be effectively prevented.

  Therefore, according to the present invention, the adhesion between the internal electrode and the ceramic sintered body made of the voltage nonlinear resistor is sufficiently enhanced, and therefore, the reliability is excellent and the surge resistance is sufficiently high. A large stacked varistor can be provided.

  In addition, when the ratio of the area of the internal electrode part excluding the voids is less than 40%, sufficient surge resistance cannot be obtained, and when it exceeds 70%, the internal electrode, the ceramic sintered body layer, It becomes impossible to sufficiently improve the adhesion.

  When the internal electrode is formed using Pt, a sufficiently large surge proof multilayer varistor can be easily provided according to the present invention.

  When a ceramic sintered body made of semiconductor ceramics is composed of a material mainly composed of ZnO, it has excellent voltage non-linearity, and therefore a multilayer varistor having a sufficiently large surge resistance can be easily obtained. Can be offered.

  In the case where the first and second external electrodes have a structure in which a plurality of conductive layers are laminated and the outermost layer is formed of an electrolytic plating film, the conductive layer is formed by electrolytic plating. However, since the adhesion between the internal electrode and the ceramic sintered body layer is excellent, penetration of the plating solution hardly occurs. Therefore, it is difficult for the reliability of the multilayer varistor to decrease.

  Even if the outermost layer of the first and second external electrodes is a conductive layer formed by sputtering, the adhesion between the internal electrode and the ceramic sintered body is improved. Moisture resistance can be secured.

  In the present invention, when an external electrode is formed by directly forming a conductive layer on the first and second end faces of the ceramic sintered body by sputtering, a thick film electrode is formed by applying and baking a silver paste. Instead, only a sputtered film may be formed. Even in this case, according to the present invention, the adhesiveness between the ceramic sintered body and the internal electrode is excellent, so that sufficient moisture resistance is ensured. Therefore, the external electrode can be efficiently formed using the sputtering method.

  Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.

  FIGS. 1A and 1B are a front sectional view and a plan sectional view of a multilayer varistor according to an embodiment of the present invention.

  The multilayer varistor 1 has a rectangular parallelepiped ceramic sintered body 2 mainly composed of ZnO. The ceramic sintered body 2 has an upper surface 2a, a lower surface 2b, a first end surface 2c, a second end surface 2d, and a pair of side surfaces 2e and 2f.

  In the ceramic sintered body 2, the first internal electrodes 3a and 3c and the second internal electrodes 3b and 3d are alternately arranged so as to overlap with each other via the ceramic sintered body layer. In the present embodiment, the internal electrodes 3a to 3d are formed using Pt. The first inner electrodes 3a and 3c are drawn out to the first end face 2c, and the second inner electrodes 3b and 3d are drawn out to the second end face 2d opposite to the first end face 2c. Yes.

  In the region where the first internal electrodes 3a, 3c and the second internal electrodes 3b, 3d overlap, the resistance due to the ceramic sintered body layer positioned between them is taken out.

  The ceramic sintered body 2 can be obtained according to a well-known method for manufacturing a multilayer ceramic electronic component. That is, first, a ceramic green sheet containing ZnO as a main component is prepared. A Pt paste is printed on the ceramic green sheet by screen printing or the like. Thereafter, a plurality of ceramic green sheets printed with Pt are laminated, and an appropriate number of plain ceramic green sheets are laminated on the upper and lower sides to obtain a laminate. The ceramic sintered body 2 is obtained by firing the laminate.

  In actual production, after obtaining a mother laminate, the mother laminate is cut in the thickness direction to prepare a laminate of two individual ceramic sintered bodies. And the ceramic sintered compact 2 is obtained by baking each laminated body.

  As shown in FIG. 1A, first and second external electrodes 4 and 5 are formed on the first end surface 2c and the second end surface 2d of the ceramic sintered body 2, respectively. The first external electrode 4 is electrically connected to the first internal electrodes 3a and 3c, and the second external electrode 5 is electrically connected to the second internal electrodes 3b and 3d.

  In the present embodiment, each of the external electrodes 4 and 5 has a structure in which a plurality of conductive layers 4a to 4c and 5a to 5c are stacked. The innermost conductive layers 4a and 5a directly formed on the end faces 2c and 2d of the ceramic sintered body 2 are sintered electrode layers formed by applying and baking Ag paste. Conductive layers 4b and 5b made of Ni plating film and conductive layers 4c and 5c made of Sn plating film as outermost layers are sequentially formed on the conductive layers 4a and 5a made of the sintered electrode layer. These Ni plating film and Si plating film are formed by electrolytic plating which is a wet plating method.

  As shown in FIG. 1B, a large number of holes 6 are formed in the internal electrode 3a. In the portion where the holes 6 are provided, after firing, the ceramic sintered body layer above the internal electrode 3a and the ceramic sintered body layer below are united and integrated. Adhesion with the ceramic sintered body layer is effectively enhanced. Other internal electrodes 3b to 3d also have the plurality of holes 6 similarly to the internal electrode 3a.

  The feature of the multilayer varistor 1 of the present embodiment is that, in the fired internal electrodes 3a to 3d, the ratio of the area of the internal electrode portion excluding the holes to the internal electrode area surrounded by the outer edge of the internal electrode is The hole 6 is formed so as to be in the range of 40 to 70%.

  When this ratio is less than 40%, a sufficiently large resistance value cannot be taken out between the first internal electrodes 3a and 3c and the second internal electrodes 3b and 3d, and sufficient. It becomes impossible to obtain a large surge resistance. If it exceeds 70%, the adhesion between the internal electrodes 3a to 3d and the ceramic sintered body layer is lowered, and the reliability is lowered.

  Furthermore, the ratio of the real area of the internal electrodes 3a to 3d may be up to 70% in order to prevent delamination, but considering that a large voltage such as a surge voltage is applied to the multilayer varistor, The ratio of the actual area of the internal electrodes 3a to 3d is preferably up to 60%.

  As described above, the feature of the present embodiment is that the ratio of the real area of the internal electrodes 3a to 3d in the portion excluding the holes 6 is in the range of 40 to 70%. In the above, good surge resistance, which is a characteristic characteristic of the varistor, and improvement in adhesion between the internal electrodes 3a to 3d and the ceramic sintered body layer are intended.

  In Patent Document 2 described above, there is no mention of such a multilayer varistor. In Patent Document 2, only a multilayer ceramic capacitor is disclosed. In Patent Document 2, a hollow portion is provided in the internal electrode. However, in Patent Document 2, the ratio of the hollow portion is the entire internal electrode. It was described that the area of the internal electrode portion where the area is not 30% or less, in other words, where the hollow portion is not provided, must be larger than 70%.

  On the other hand, in this embodiment, the area ratio of the internal electrode part is 70% or less except for the part where the holes 6 are provided, that is, the ratio denied in Patent Document 2. Thus, the actual areas of the internal electrodes 3a to 3d in the portion excluding the holes 6 are defined. In other words, in the present embodiment, the holes 6 are provided in the internal electrodes 3a to 3d so as to have a ratio denied in Patent Document 2, thereby improving the surge resistance of the multilayer varistor 1 and reducing the internal electrode and ceramic firing. It is intended to improve the adhesion of the bonded body. This will be described based on a specific experimental example.

  A slurry containing ZnO-based semiconductor ceramic powder and an organic resin binder was formed to obtain a ceramic green sheet. On this ceramic green sheet, a Pt-containing paste was screen-printed to form an internal electrode pattern. Also, a plurality of ceramic green sheets on which internal electrode patterns were printed with the Pt paste were laminated, pressed in the thickness direction, and then cut in the thickness direction to obtain a laminate of individual ceramic sintered body units. The laminate was heated, degreased, and then maintained in air at a temperature of 1160 to 1200 ° C. for 8 hours for firing. In this way, a ceramic sintered body 2 was obtained.

  Next, after corner polishing and surface portion of the obtained ceramic sintered body 2 are barrel-polished, an Ag paste containing 3.5% by weight of Zn-based frit is applied, and the temperature is in the range of 750 to 850 ° C. Baking was performed to form conductive layers 4a and 5a. Thereafter, a Ni plating film and a Sn plating film were sequentially formed by electrolytic plating to form conductive layers 4b, 5b, 4c, and 5c, and a multilayer varistor 1 was obtained.

  In the production of the multilayer varistor 1, the Pt content in the Pt paste as the internal electrode paste is 75, 70, 65, 60, 55, 50, 45, 40, and 35% by weight in terms of solid content. A plurality of types of laminated varistors 1 were obtained. The content ratio of Pt is varied, and pores 6 are formed in the firing step according to the content ratio of Pt, and the ratio of the portion where the upper and lower ceramic sintered body layers are bonded is changed in the pore portions. This is because a plurality of types of laminated varistors 1 are obtained.

  FIG. 2 shows the relationship between the Pt content ratio in the Pt paste and the internal electrode coverage in the plural types of laminated varistors obtained as described above.

  In Table 1 below, the internal electrode coverage according to the Pt content in the Pt paste is also shown. The internal electrode coverage is the ratio of the internal electrode part excluding the voids calculated by cutting the ceramic sintered body obtained by firing and using an image analyzer. As can be seen from Table 1, the internal electrode coverage decreases as the Pt content in the Pt paste decreases. This internal electrode coverage is inversely related to the above-described ratio of holes.

  The multilayer varistor 1 obtained as described above is mounted on a printed circuit board using a solder paste, put into a constant temperature and humidity chamber, and left in an environment of 85 ° C. and relative humidity 85% RH for 1000 hours. did. When the insulation resistance logIR after being left at 85 ° C. and 85% relative humidity for 1000 hours exceeded 6, the product was accepted, and when it was 6 or less, the product was rejected. The results are shown in Table 1 below by means of ◯ and X. Moreover, the result of the test in this constant temperature and humidity chamber is shown in FIG.

  In addition, a surge resistance test was performed as follows. That is, it was a square wave of 8/20 μsec, a surge current of Ip = 20 A was applied twice, and the insulation resistance logIR after energization was measured. The results are shown in FIG. Moreover, when logIR after electricity supply was larger than 6, it was set as normal and marked with ○ in Table 1 below. Moreover, x mark shows that the insulation resistance logIR after surge current application is less than 6, and it is a rejected product.

  As apparent from Table 1, when the Pt content in the Pt paste is 60, 55, 50 and 45% by weight, the internal electrode coverage is 73, 61, 50 and 39%, in other words, the porosity is 27, 39, 50 and 61%. In these cases, the insulation resistance logIR after the constant temperature and humidity test was not deteriorated and was larger than 6. Furthermore, no deterioration of the insulation resistance logIR after the surge resistance test was observed, and good results were obtained.

  This is because, when the internal electrode coverage is 39 to 73%, in other words, when the porosity is in the range of 27 to 61%, the internal electrode contracts during firing, and the internal electrode portion formed into a mesh shape, This is considered to be due to the fact that the upper and lower ceramic sintered bodies are bonded to each other in the hole portion that does not contribute to the coating with the internal electrode constituent metal, and the adhesion between the internal electrode and the ceramic sintered body layer is enhanced. That is, the penetration of moisture and plating solution from the portion where the internal electrodes 3a to 3d are drawn out to the end faces 2c and 2d of the ceramic sintered body 2 or the penetration of flux components in the solder paste is suppressed, and the flux and It is considered that the decrease in insulation resistance is reduced because the diffusion of moisture and the like into the interior is reliably suppressed. Further, as described above, since the ratio of the holes is not so high, the multilayer varistor having the electrode coverage of 73, 61, 50, and 39% has a sufficient surge resistance.

  On the other hand, in the multilayer varistor using the internal electrode with Pt content of 75, 70 and 65% by weight, the insulation resistance logIR after the constant temperature and humidity test was less than 6, which was poor. This is because, since the porosity is 15% or less, the portion where the upper and lower ceramic sintered body layers are bonded to each other is reduced, and the adhesion between the internal electrode and the ceramic sintered body layer is reduced. Conceivable. That is, it is considered that moisture, plating solution, and flux component penetration / diffusion between the internal electrode-ceramic sintered body layers were difficult to be suppressed.

  On the contrary, when Pt paste with Pt content of 40 and 35% by weight was used, the insulation resistance logIR after the surge resistance test was less than 6, which was poor. Since the porosity is as high as 68 and 75%, the area of the internal electrode excluding the void is too small to absorb the surge current effectively, and the insulation resistance between the internal electrodes This is thought to be due to the fact that the deterioration of the material became remarkable.

  From the above experimental example, it can be seen that if the coverage of the internal electrode is 39 to 73%, in other words, the porosity is 61 to 37%, both moisture resistance and surge resistance can be achieved. According to the experiment by the present inventor, it has been confirmed that the same result as in the above experimental example can be obtained when the porosity is in the range of 40 to 70%.

  5 to 7 are front sectional views of partially cutouts for explaining another embodiment of the multilayer varistor of the present invention.

  In the multilayer varistor 21 of the second embodiment shown in FIG. 5, the external electrodes 24, 25 have a structure in which conductive layers 24a, 25a and outer conductive layers 24b, 25b are stacked. About another point, it is comprised similarly to the multilayer varistor 1 of 1st Embodiment.

  In the present embodiment, the conductive layers 24a and 25a are formed by applying and baking an Ag-containing paste, and NiCr-NiCu-Ag films formed by sputtering are stacked as the outer conductive layers 24b and 25b. . As described above, even when the outermost conductive layers 24b and 25b are conductive layers provided by sputtering, flux components and moisture in the solder paste are not present when mounted on the substrate using the solder paste. Intrusion can be suppressed and moisture resistance can be secured. In forming the NiCr—NiCu—Ag film, NiCr, NiCu, and Ag may be prepared as targets and sputtered. The outer conductive layer may be formed by sputtering such an alloy film or a quasi-metal other than the alloy. In the first embodiment, the plating film is formed outside the Ag electrode, but in the second embodiment, a sputtered film is used instead. In the case of this embodiment, moisture resistance can be ensured even with a sputtered film that is thinner than the plated film. Further, when the dielectric layer is formed by sputtering, no plating solution is used, so that the problem of moisture resistance does not occur in the process of forming the dielectric layer. Therefore, there is a merit in the manufacturing process.

  In the multilayer varistor 21 of the second embodiment, the Pt paste content in the conductive paste constituting the internal electrode is set to 75, 70, 65, 60, 55, as in the experimental example of the first embodiment. A plurality of types of laminated varistors 21 were prepared and evaluated by changing the amounts to 50 and 45% by weight. The results are shown in Table 2 below.

  In Table 2, when the content rate of the said Pt paste is changed, it turns out that the internal electrode coverage after baking changes with it similarly to the case of Table 1. It can also be seen that the insulation resistance logIR after the high temperature and high humidity test is good when the internal electrode coverage is 73% or less.

  FIG. 6 is a front sectional view showing a multilayer varistor according to the third embodiment. In the multilayer varistor 31 of the third embodiment, the external electrodes 34 and 35 are formed of a conductive film formed by single-layer sputtering. Therefore, the structure of the multilayer varistor 31 is the same as that of the multilayer varistor 1.

  In the present invention, like the third stacked varistor 31, the first and second external electrodes 34 and 35 may be formed of a single-layer conductive film. In the third embodiment, the external electrodes 34 and 35 made of a single conductive layer are formed by sputtering a NiCr—NiCu—Ag film, but may be formed from other metals or alloys. Good.

  In the second embodiment, the sputtered film is formed outside the Ag electrode. However, in the third embodiment, the Ag electrode is not formed and only the sputtered film is formed. Moisture resistance is ensured. That is, since the adhesiveness between the ceramic sintered body and the internal electrode is sufficiently ensured, it is possible to prevent the flux component and moisture from entering during mounting regardless of the presence or absence of the Ag electrode, and to secure moisture resistance.

  FIG. 7 is a front cross-sectional view showing a multilayer varistor according to a modification of the multilayer varistor 1 of the first embodiment. In the multilayer varistor 41 shown in FIG. 7, the external electrodes 4 and 5 are configured in the same manner as the external electrodes 4 and 5 of the first embodiment. The difference is that the internal electrodes 43a to 43d in the ceramic sintered body 2 are configured to have a relatively thick portion and a relatively thin portion. For example, when the internal electrode 43a is taken as an example, the internal electrode 43a is relatively thick in the characteristic portion indicated by the arrow A, and also in the lead portion B near the edge connected to the external electrode 4, The thickness is relatively increased. And in the connection part C which connects the characteristic part A and the drawer | drawing-out part B, thickness is made relatively thin. The other internal electrodes 43b to 43d have the same structure.

  In this modification, a sufficient surge resistance can be ensured by relatively increasing the thickness of the internal electrode in the characteristic portion A, and the portion electrically connected to the external electrodes 4 and 5 The reliability of the electrical connection is enhanced by making the lead-out portion B which is a sufficient thickness.

  On the other hand, with regard to the connection portion C, the adhesion between the internal electrode and the ceramic sintered body layer can be enhanced by making it thin. That is, in the relatively thin connection portion C, a plurality of holes are formed as described above, but the upper and lower ceramic sintered bodies are joined together by the ceramics that have entered the hole portions, and are integrated. However, in the portion where the thickness of the internal electrode is thin, the upper and lower ceramic sintered bodies are easily attached, and the adhesion between the internal electrode and the ceramic sintered body layer is effectively enhanced.

  Accordingly, by relatively reducing the thickness of the internal electrode in portions other than the characteristic portion A and the lead-out portion B as in the present embodiment, the surge resistance is sufficiently large, and the reliability of the electrical connection is improved. According to the present invention, the adhesion between the internal electrode and the ceramic sintered body layer can be effectively enhanced.

(A) And (b) is a front sectional view and a plan sectional view of the multilayer varistor according to the first embodiment of the present invention. The figure which shows the relationship between Pt content in Pt paste in an internal electrode, and the internal electrode coverage after baking. The figure which shows the relationship between the internal electrode coverage after baking, and the insulation resistance after leaving to stand at 85 degreeC and relative humidity 85% for 1000 hours. The figure which shows the relationship between the internal electrode coverage after baking, and the insulation resistance after surge tolerance. Front sectional drawing of the laminated varistor which concerns on the 2nd Embodiment of this invention. Front sectional drawing of the laminated varistor which concerns on the 3rd Embodiment of this invention. Front sectional drawing which shows the modification of the laminated varistor of 1st Embodiment. Front sectional view showing an example of a conventional laminated varistor. Front sectional drawing which shows the conventional multilayer ceramic capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multilayer varistor 2 ... Ceramic sintered body 2a ... Upper surface 2b ... Lower surface 2c, 2d ... End surface 3a, 3c ... 1st internal electrode 3b, 3d ... 2nd internal electrode 4 ... 1st external electrode 4a-4c ... Conductive layer 5 ... Second external electrodes 5a to 5c ... Conductive layer 6 ... Hole 21 ... Laminated varistor 24,25 ... External electrodes 24a, 24b, 25a, 25b ... Conductive layer 31 ... Laminated varistor 34,35 ... External electrode 41 ... Multilayer varistors 43a to 43d ... Internal electrode A ... Characteristic part B ... Lead-out part C ... Connection part

Claims (6)

A ceramic sintered body having first and second end faces facing each other, the resistance value of which has voltage non-linearity;
A first internal electrode and a second internal electrode arranged to alternately overlap with each other through a ceramic sintered body layer in the ceramic sintered body,
The first internal electrode is drawn out to the first end face of the ceramic sintered body, and the second internal electrode is drawn out to the second end face opposite to the first end face of the ceramic sintered body,
A laminate further comprising first and second external electrodes respectively formed on the first and second end faces of the ceramic sintered body and electrically connected to the first and second internal electrodes, respectively. In type varistors,
The multilayer varistor, wherein the internal electrode has a plurality of holes, and the area of the internal electrode portion excluding the holes is in the range of 40 to 70% of the area of the internal electrode.   2. The multilayer varistor according to claim 1, wherein the first and second internal electrodes are made of a material containing Pt as a main component.   The multilayer varistor according to claim 1 or 2, wherein the ceramic sintered body is configured using a material mainly composed of ZnO.   The first and second external electrodes have a structure in which a plurality of conductive layers are laminated, and the outermost conductive layer is formed of an electrolytic plating film. Laminated varistor.   The first and second external electrodes have a structure in which a plurality of conductive layers are stacked, and the outermost conductive layer is formed of a conductive film formed by sputtering. 2. A laminated varistor according to item 1. The laminated type according to any one of claims 1 to 3, wherein the first and second external electrodes are conductive films formed by sputtering on the first and second end faces of the ceramic sintered body. Barista.

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