JP2006185998A - Thin film transistor forming method and plasma cvd device used for forming thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor forming method and a plasma CVD device used for forming a thin film transistor, wherein an excellent gate insulating film can be efficiently formed through a process of preventing dangling bonds from occurring without depending on a past-treatment. <P>SOLUTION: The thin film transistor forming method comprises processes of forming a silicon film on a substrate, and providing the gate insulating film on the silicon film by gradually varying a power applied to generate plasma in a plasma CVD method. The plasma CVD method and the plasma CVD device used for forming the thin film transistor are provided so as to improve the thin film transistors in element characteristics without carrying out an after treatment. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a thin film transistor on a substrate and a plasma CVD apparatus for forming the thin film transistor.

  What is important in forming a thin film transistor having good device characteristics is that the density of the trap level at the interface between the semiconductor layer and the gate insulating film (interface state density) and the operating voltage (threshold voltage) of the thin film transistor. It is to reduce.

  Conventionally, the gate insulating film is formed by a thermal oxidation method and a plasma CVD method. The thermal oxidation method is limited to a glass substrate (for example, a quartz glass substrate) that can be used for heat resistance because heat treatment at about 1000 ° C. or more must be performed for 1 hour or more after the gate insulating film is formed. Since such a glass substrate is expensive, there is a problem in cost. In the case of a large flat panel or the like, there is an inconvenience that the profitability is poor. In addition, since the processing time is long, there is a problem of throughput reduction.

  Therefore, at present, the plasma CVD method, which can be processed at a low temperature and does not require a processing time as much as the thermal oxidation method, is mainly used. For example, in the case of using a large glass substrate such as for manufacturing a liquid crystal panel, there is a method of depositing a silicon oxide film on the glass substrate using tetraethoxysilane (TEOS) gas (for example, see Patent Document 1).

  However, according to this method, there are many defects in the film, trap levels are generated at the interface between the semiconductor layer and the gate insulating film, and the induced carriers are trapped in the trap levels, which cannot contribute to conduction. In order to solve this, since a high gate voltage is required, the field effect mobility is lowered and the threshold voltage is increased.

By the way, the generation of the trap level is caused by the formation of a dunk ring bond. Therefore, conventionally, after dangling bonds and inert gas atoms, ions, and radicals are combined to be electrically inactivated and the substrate is kept at 100 ° C., the gate insulating film is deposited, and then the gate insulating film Was heat-treated from 400 to 600 ° C. (for example, see Patent Document 2).
JP 63-246829 A JP 2003-124231 A

  When a dangling bond is frequently generated, for example, when a P-type silicon wafer is used, the flat band voltage (Vfb) is −2.5 V at a film thickness of 100 nm as shown in FIG. A voltage larger than −0.7 V in the case of the formed thin film transistor is required, which causes a problem that the field effect mobility is lowered and the threshold voltage is increased. Since the flat band voltage greatly affects the threshold voltage in the thin film transistor, suppressing the generation of the dangling bond and improving the quality of the gate insulating film leads to improvement in device characteristics of the thin film transistor.

  In addition, if heat treatment is performed as a post-treatment after the formation of the gate insulating film as in the above prior art, the quality of the gate insulating film is improved, but there is a disadvantage that the processing time is increased and the working efficiency is lowered.

  Accordingly, in view of the above problems, the present invention provides a method for forming a thin film transistor that efficiently forms a good gate insulating film by suppressing the occurrence of dangling bonds without relying on the post-treatment, and a plasma for forming the thin film transistor. It is an object to provide a CVD apparatus.

  In order to solve the above-described problems, a thin film transistor forming method according to the present invention is a method of forming a thin film transistor on a substrate, and a step of forming a silicon film on the substrate and generating plasma by a plasma CVD method. Forming a gate insulating film on the silicon film by changing the applied power stepwise.

  According to this configuration, the gate insulating film on the silicon film is gradually formed in accordance with the power applied by changing in stages as compared with the conventional forming method. For example, the power may be high-frequency power that is applied in two stages.

  Of the high-frequency power applied in the two stages, the power applied in the second stage is preferably larger than the power applied in the first stage. For example, the power density of the power applied in the first stage is 0.02 W / cm 2 or more and 0.30 W / cm 2 or less, and the power density of the power applied in the second stage is 0.50 W / cm 2 or more and 0.80 W / cm 2. The following is sufficient. Furthermore, it is preferable that the discharge time of the power applied in the first stage is 1 second or more and 10 seconds or less.

  The source gas introduced to form the gate insulating film is preferably a silicon atom-containing gas containing at least one of a silane compound such as tetraethoxysilane, hexamethyldisilazane, and triethoxysilane. The silicon film is preferably a thin film made of amorphous silicon or polysilicon.

  In order to solve the above problems, a plasma CVD apparatus according to the present invention is a plasma CVD apparatus in which a silicon film is formed on a substrate and a gate insulating film is formed on the silicon film to form a thin film transistor. A gas introduction system that introduces a silicon atom-containing gas and an oxygen atom-containing gas into the vacuum chamber, a substrate holder on which the substrate on which the thin film transistor is formed is placed, a substrate electrode that heats the substrate holder, A high-frequency electrode installed at a position facing the substrate holder, a high-frequency power source for supplying high-frequency power to the high-frequency electrode, and a control for changing the high-frequency power from the high-frequency power source to the high-frequency electrode in steps. And a control unit.

  According to this configuration, it is possible to automatically perform stepwise application of high-frequency power applied to generate plasma by the control unit. The control unit can set the number of stages, the magnitude of applied power at each stage, the setting range of the applied power density, the application time, and the like as control parameters.

  Therefore, in the above control unit, the number of stages is divided into two stages, the power applied in the second stage is made larger than the power applied in the first stage, and the power of the high-frequency power applied in the first stage The density is set to 0.02 W / cm 2 or more and 0.30 W / cm 2 or less, the power density of the high-frequency power applied in the second stage is set to 0.50 W / cm 2 or more and 0.80 W / cm 2 or less, the first stage The discharge time of the high frequency power applied at 1 can be set to 1 second or more and 10 seconds or less.

  As is apparent from the above description, the present invention can suppress the generation of dangling bonds and reduce the flat band voltage and interface state density without performing post-processing after the gate insulating film is deposited. A good gate insulating film can be efficiently formed, and the element characteristics of the thin film transistor can be improved.

  Referring to FIG. 1, reference numeral 1 denotes a vacuum chamber of a plasma CVD apparatus according to the present invention. A raw material gas introduction system 2 is provided above the vacuum chamber 1. In the present embodiment, a gas introduction port (not shown) is opened on the upper surface of the vacuum chamber 1, and the source gas supplied from the source gas introduction system 2 is introduced into the vacuum chamber 1 from this gas introduction port. . The source gas is a silicon atom-containing gas containing at least one of silane compounds such as tetraethoxysilane, hexamethyldisilazane, and triethoxysilane, and oxygen, oxygen, nitrous oxide, ozone, carbon dioxide, or water. It is an atom-containing gas. In addition, as for the ratio of the said silicon atom containing gas and oxygen atom containing gas, 1: 20-100 are preferable.

  In order to turn this source gas into plasma in the vacuum chamber 1, high-frequency power is applied from the high-frequency power source 3 through the modulator 4 to the electrode 5 in the vacuum chamber 1. A substrate holder 8 on which a substrate 7 is placed via a shower plate 6 is provided at a position facing the electrode 5. An electrode (not shown) for heating the substrate is embedded in the substrate holder 8. A vacuum exhaust system 9 is provided below the vacuum chamber 1.

  The raw material gas is introduced into the vacuum chamber 1 from the gas introduction system 2, and a predetermined high frequency power is applied from the high frequency power source 3 through the modulator 4 to the electrode 5. Plasma is generated in a high electric field by the applied high frequency power. The source gas is excited by the plasma to promote a chemical reaction, thereby forming a desired gate insulating film. This gate insulating film is formed on a silicon film (portions serving as a source, a channel portion, and a drain of a thin film transistor) already formed on the substrate 7. The oscillation frequency of the high frequency power supply 3 may be 10 to 100 MHz. The film forming temperature is preferably 300 to 450 ° C., and the film forming pressure is preferably 80 to 400 Pa.

  Conventionally, the gate insulating film was formed by applying the predetermined high frequency power from the beginning, but in this method, dangling bonds are likely to occur, and the flat band voltage and interface state density increase. There is a risk that the quality of the gate insulating film deteriorates and the reliability of the element characteristics of the thin film transistor is impaired. In addition, in order to suppress the occurrence of dangling bonds, heat treatment was performed as a post-treatment after forming the gate insulating film to improve the quality of the gate insulating film. However, there is a disadvantage that the processing time is increased and the throughput is lowered. there were.

  Therefore, in the present invention, in order to form a high-quality gate insulating film without the above-described inconveniences, the control unit 10 that can be set to apply high-frequency power in a stepwise manner is provided. In order to form a desired gate insulating film, the control unit 10 can input control parameters necessary for applying the high-frequency power that is changed stepwise. Here, the necessary control parameters are, for example, the number of stages, the applied power at each stage, the application time, and the like.

  Hereinafter, the conventional thin film transistor forming method and the thin film transistor forming method according to the present invention will be compared with reference to FIGS.

  FIG. 2 is a graph showing the relationship between applied power density (W / cm 2) and elapsed time (seconds) according to the conventional method. According to the conventional method, the target power of 0.65 W / cm 2 is applied in about 1 second after 5 seconds from the start of the film forming process, and the application of this power is maintained thereafter. FIG. 3 is a diagram showing the relationship between the applied power density (W / cm 2) and the elapsed time (seconds) by the power application method (stepwise application method) according to the present invention. According to this stepwise application method, as the first step, when 5 seconds have elapsed from the start of the film forming process, a power of 0.05 W / cm 2 is applied for about 1 second, and thereafter this power is applied for up to 10 seconds. In the second stage, about 0.60 W / cm 2 of power is applied after 10 seconds, and the application of this power is maintained thereafter.

  FIG. 4 is a graph showing the relationship between the film thickness and the flat band voltage (Vfb) by the conventional method and the stepwise application method. For example, Vfb at a film thickness of 100 nm is −2.4 V according to the conventional method, whereas it is −1.4 V according to the stepwise application method. Therefore, at a film thickness of 100 nm, the stepwise application method can reduce the voltage applied by about −1 V compared to the conventional method. FIG. 5 is a graph showing the relationship between the film thickness and the interface state density (Dit: cm−2 · eV−1) by the conventional method and the stepwise application method. As is apparent from this figure, according to the stepwise application method, Dit is also reduced from the conventional method. FIG. 6 is a graph showing the relationship between the applied power density and the deposition rate (nm / min) by the conventional method and the stepwise application method. Comparing the film forming speeds of the input power density between 0.50 and 0.70 W / cm 2, the difference between the stepwise application method and the conventional method is in the range of about 5 nm / min. Even when power is applied to the film, the film formation rate is almost the same as that of the conventional method. Therefore, it is considered that productivity is hardly impaired even if the stepwise application method is adopted.

  The thin film transistor forming method and the plasma CVD apparatus for forming the thin film transistor according to the present invention are thin film transistors formed on a glass substrate, and the film forming temperature is 600 ° C. or lower due to the heat resistance temperature of the glass substrate. Is preferred. In addition, the film formation is preferably a process in which a semiconductor layer is first formed on the glass substrate, and then a gate insulating film and a gate are formed in that order. Furthermore, a parallel plate type plasma CVD apparatus is preferable as the apparatus. However, the present invention is not limited to these without departing from the scope of the invention described in the claims.

According to the above embodiment, the present invention was implemented under the following basic conditions.
Deposition temperature 350 ° C
First stage applied power density 0.06 W / cm 2
Second stage applied power density 0.66 W / cm 2
Deposition pressure 175Pa
First stage discharge time 5 seconds Evaluation film thickness 100 nm
TEOS gas flow rate 200sccm
Gas flow rate of oxygen atom-containing compound 50 times that of TEOS gas

  Based on the above basic conditions, the flat band voltage (Vfb) and interface state when the three parameters of the first stage applied power density, the second stage applied power density, and the first stage discharge time are changed, respectively. The transition of unit density (Dit) was measured.

  FIG. 7 is a diagram showing the relationship between Vfb and Dit when the applied power density in the first stage is changed. When the applied power density is 0.30 W / cm 2 or less, both Vfb and Dit hardly change and show a constant value. However, when the applied power density is 0.50 W / cm 2 or more, both Vfb and Dit deteriorate due to plasma damage. It should be noted that from the start of application of the applied power density to 0.02 W / cm2, a steep change is shown until the values of Vfb and Dit reach the constant values. This is because it is difficult to control the power density value at 0.02 W / cm 2 or less.

  FIG. 8 is a diagram showing the relationship between Vfb and Dit when the applied power density in the second stage is changed. When the applied power density is in the range of 0.40 W / cm 2 to 0.50 W / cm 2, both Vfb and Dit are gradually reduced from the values in the first stage. When the applied power density is 0.50 W / cm 2 or more, both Vfb and Dit hardly change, and are stable at substantially the same value as the constant value shown in the first stage of FIG. The upper limit of the applied power density is approximately 0.80 W / cm 2, but this is due to the occurrence of film formation defects due to the generation of arcs and an increase in film stress when a power density of 0.80 W / cm 2 or more is applied. This is because there is a possibility of thin film peeling.

  FIG. 9 is a diagram showing the relationship between Vfb and Dit when the first stage discharge time is changed. After 1 second, Dit shows a substantially constant value regardless of the passage of time, but for Vfb, the voltage decreases most after 1 second, and then gradually increases, and after about 10 seconds, It turns out that it became about -1.8V. In the range of 1 second or less from the start of discharge, a steep change is observed from about −2.5V to −1.3V. This is because the reproducibility is poor and control is difficult immediately after discharge.

  From the above results, it is necessary to suppress the plasma damage in the initial stage of power density application, that is, in the initial stage of film formation, but from the time when the stage in which the power density to be applied is gradually increased has passed, It can be seen that a better thin film can be obtained if the film is formed with a high plasma density that can sufficiently decompose the gas. In the initial stage of film formation, it can be seen that the shorter the discharge time, the better Vfb. Therefore, in consideration of the controllable range of the applied power density, as specific values, the applied power density in the first stage is 0.02 W / cm 2 or more and 0.30 W / cm 2 or less, and the discharge time is 1 second. It is considered that the applied power density in the second stage is desirably 0.50 W / cm 2 or more and 0.80 W / cm 2 or less.

  Since the present invention is a thin film transistor forming method for improving element characteristics of a thin film transistor or a plasma CVD apparatus for forming this thin film transistor, the present invention has industrial applicability in the field of thin film transistor manufacturing.

Schematic of plasma CVD apparatus according to the present invention Diagram showing the relationship between applied power density and time by the conventional method Figure showing the relationship between applied power density and time by stepwise application method Diagram showing the relationship between film thickness and flat band voltage by conventional method and stepwise application method Diagram showing the relationship between film thickness and interface state density by conventional method and stepwise application method Diagram showing the relationship between the applied power density and the deposition rate by the conventional method and the stepwise application method The figure which showed the relationship between the interface state density with respect to the applied electric power density of a 1st step, and a flat band voltage The figure which showed the relationship between the interface state density with respect to the applied electric power density of a 2nd step, and a flat band voltage The figure which showed the relationship between the interface state density with respect to the discharge time of a 1st step, and a flat band voltage The figure which showed the relation between the film thickness of the insulating film by the conventional method and the flat band voltage

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vacuum chamber 2 Gas introduction system 3 High frequency power supply 4 Modulator 5 Electrode 6 Shower plate 7 Substrate 8 Substrate holder 9 Vacuum exhaust system 10 Control part

Claims (14)

  A method of forming a thin film transistor on a substrate, comprising: a step of forming a silicon film on the substrate; and a step of changing power applied to generate plasma by a plasma CVD method to form a gate on the silicon film. Forming a thin film transistor.   2. The method of forming a thin film transistor according to claim 1, wherein the power is high-frequency power applied in two stages.   3. The high-frequency power applied by changing in the two stages, wherein the power applied in the second stage is higher than the power applied in the first stage. The thin-film transistor formation method in any one.   4. The method of forming a thin film transistor according to claim 1, wherein the power density of the power applied in the first step is 0.02 W / cm 2 or more and 0.30 W / cm 2 or less.   5. The method of forming a thin film transistor according to claim 1, wherein the power density of the electric power applied in the second stage is 0.50 W / cm 2 or more and 0.80 W / cm 2 or less.   6. The method of forming a thin film transistor according to claim 1, wherein a discharge time of the electric power applied in the first stage is not less than 1 second and not more than 10 seconds.   The source gas introduced to form the gate insulating film is a silicon atom-containing gas containing at least one of tetraethoxysilane, hexamethyldisilazane, and triethoxysilane. Item 7. The method for forming a thin film transistor according to any one of Items 6 to 6.   8. The method of forming a thin film transistor according to claim 1, wherein the silicon film is a thin film made of amorphous silicon or polysilicon.   A plasma CVD apparatus for forming a thin film transistor by forming a silicon film on a substrate and forming a gate insulating film on the silicon film, the vacuum chamber, and a silicon atom-containing gas and an oxygen atom-containing gas in the vacuum chamber A gas introduction system for introducing the substrate, a substrate holder for mounting the substrate on which the thin film transistor is formed, a substrate electrode for heating the substrate holder, a high-frequency electrode installed at a position facing the substrate holder, and the high-frequency A plasma CVD apparatus comprising: a high-frequency power source that supplies high-frequency power to an electrode; and a control unit that controls the high-frequency power from the high-frequency power source to be applied in a stepwise manner to the high-frequency electrode.   10. The plasma CVD apparatus according to claim 9, wherein the control unit controls the high frequency power based on a setting to change and apply the high frequency power in two stages.   The control unit performs control based on a setting in which the power applied in the second stage is higher than the power applied in the first stage among the high-frequency power applied in the two stages. The plasma CVD apparatus according to claim 9 or 10, wherein the apparatus is a plasma CVD apparatus.   The control unit is configured to control by setting a power density of the high-frequency power applied in the first step in a range of 0.02 W / cm 2 or more and 0.30 W / cm 2 or less. The plasma CVD apparatus according to claim 11.   10. The control unit according to claim 9, wherein the control unit sets and controls the power density of the high-frequency power supplied in the second stage in a range of 0.50 W / cm 2 to 0.80 W / cm 2. The plasma CVD apparatus according to claim 12.   14. The control unit according to claim 9, wherein the control unit sets and controls a discharge time of the high frequency power applied in the first stage in a range of 1 second to 10 seconds. The plasma CVD apparatus according to any one of the above.

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