JP2006184140A - Phase sequence display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase sequence display device whose measuring place is not restricted, dispensing with a battery exchange work or a charging work. <P>SOLUTION: This device includes sensors 2-4 for detecting voltages V1-V3; diodes 11-13 for generating a digital signal S32 having a positive voltage when the voltage V3 is a positive voltage relative to the voltage V2; diodes 21-23 for generating a digital signal S12 having a positive voltage when the voltage V1 is a positive voltage relative to the voltage V2; a flip-flop circuit 14 operating with the digital signal S32 as a power source and outputting a digital signal Sn; a flip-flop circuit 24 operating with the digital signal S12 as a power source and outputting a digital signal Sr; and a display part 6 for displaying a positive-phase display image 41 by being driven by the digital signal Sn and displaying an opposite-phase display image 42 by being driven by the digital signal Sr. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase sequence display device that detects and displays the phase sequence of a three-phase alternating current.

As this type of phase sequence display device, a phase tachometer disclosed in JP-A-8-15356 is known. In this phase tachometer, a voltage is generated in each electrode plate by electrostatic induction when the three electrode plates are brought close to each of the three wires covered with the insulating coating of the three-phase AC circuit in the applied state. The phase determination circuit determines the voltage phase order (phase order) of the three-phase alternating current based on the generated voltage, and the display unit displays the determination result. Therefore, according to this phase tachometer, the voltage is detected from the portion of the wire covered with the insulation film without directly contacting the phase discrimination circuit with the portion of the wire not covered with the insulation film (conducting wire). Since it is possible to determine the phase order of the three-phase alternating current, it is possible to avoid the risk of electric shock. In this case, the phase tachometer that determines the phase sequence of three-phase AC without contacting the conductive wire generally operates using the power output from the commercial AC power source via the AC adapter or the power of the built-in battery. It is configured to.
JP-A-8-15356 (page 2)

  However, the conventional phase tachometer (phase sequence display device) has the following problems. In other words, the conventional phase sequence display device is operated by the power output from the commercial AC power supply via the AC adapter or the power of the built-in battery. Therefore, the conventional phase-sequence display device of the type using a commercial AC power supply cannot be used in a place without a commercial AC power supply, and thus has a problem that the measurement place is restricted. On the other hand, in the phase sequence display device using the power of the built-in battery, although the measurement location is not limited, the remaining capacity of the built-in battery decreases according to the operation time of the phase sequence display device, and unintended operation due to power shortage There is a risk of stopping. For this reason, when using a primary battery as a built-in battery, early battery replacement work is required, and when using a rechargeable battery, early charge work is required. Therefore, the conventional phase sequence display device also has a problem that the replacement work and the charging work are complicated. In addition, the structure which uses the three-phase alternating current imposed on the conduction | electrical_connection wire as a power supply is considered by making a phase-sequence display apparatus contact the conduction | electrical_connection wire directly. However, when this configuration is adopted, the risk of electric shock becomes a problem.

  The present invention has been made in view of such a problem, and provides a phase sequence display device that can avoid the risk of electric shock and can eliminate the need for battery replacement work and charging work without limiting the measurement location. The main purpose.

  In order to achieve the above object, the phase sequence display device according to claim 1 is configured to detect first, second and third detection voltages by electrostatic induction from each of three phases in three-phase alternating current. The third detection voltage is one of a positive voltage and a negative voltage with respect to the first detection voltage detected from the two and third detectors and the grounded one of the three phases. A first pulse signal generation unit for generating a first pulse signal having the polarity when the polarity is positive, and when the second detection voltage is any one of the polarities with respect to the first detection voltage A second pulse signal generation unit that generates a second pulse signal having a polarity; and the first pulse signal in a period in which the first detection voltage is a reference potential and the voltage has any one of the polarities. Operating as a power source and during operation said second pulse A first flip-flop circuit that outputs a first drive signal that shifts to one of the polarities with respect to the reference potential in synchronization with the shift to one of the polarities of the signal, and the first detection voltage As a reference potential and the second pulse signal during the period of any one of the polarities is used as a power source and is synchronized with the transition of the first pulse signal to any one of the polarities during operation. A second flip-flop circuit that outputs a second drive signal that shifts to any one of the polarities with respect to the reference potential, and is driven by the first drive signal to display a normal phase display image and And a display unit that is driven by the second drive signal to display a reverse phase display image.

  According to the phase sequential display device of the first aspect, the first flip-flop circuit uses the first detection voltage as the reference potential and the voltage of any polarity (for example, a positive voltage) during the first period. The first pulse signal operates as a power source, and outputs a first drive signal that shifts to the positive voltage with respect to the reference potential in synchronization with the shift of the second pulse signal to the positive voltage during the operation. The flip-flop circuit operates with the first detection voltage as a reference potential and the second pulse signal during a period of positive voltage as a power source, and is synchronized with the transition of the first pulse signal to the positive voltage during operation. Then, the second drive signal that shifts to the positive voltage with respect to the reference potential is output, and the display unit is driven by the first drive signal to display the positive phase display image and the second drive signal. Driven and reversed phase display By displaying the image, it is possible to use the power of each phase as the operating power from the top of the insulating coating of the three-phase AC circuit, so avoiding the risk of electric shock, without limiting the measurement location, In addition, it is possible to realize a phase sequence display device that can eliminate battery replacement work and charging work.

  The best mode of a phase sequence display device according to the present invention will be described below with reference to the accompanying drawings.

  First, the configuration of the phase sequence inspection apparatus 1 will be described with reference to the drawings.

  The phase sequence inspection device 1 is an example of a phase sequence display device according to the present invention, and includes three detectors 2, 3, 4, a phase detection unit 5 and a display unit 6, as shown in FIG. Then, the phase order of the three-phase AC output from the three-phase AC power supply 50 in a state where the S phase is grounded is inspected.

  The detector 2 corresponds to the second detector in the present invention, and includes an electrode plate 31 and, as an example, is formed in a clip shape (not shown) capable of sandwiching a wire. The detector 3 corresponds to the first detector in the present invention, and includes an electrode plate 32 and is formed in a clip shape (not shown) like the detector 2. The detector 4 corresponds to the third detector in the present invention, and includes an electrode plate 33 and is formed in a clip shape (not shown) like the detector 2. The detectors 2 to 4 are color-coded, for example, so as to be distinguishable from each other. In addition, each of the detectors 2 to 4 sandwiches three electric wires of a three-phase AC circuit, so that the voltages V1, V2, and V2 correspond to the voltages supplied to the electric wires on the electrode plates 31, 32, and 33, respectively. V3 (second, first, and third detection voltages in the present invention) is detected by electrostatic induction and output to the phase detector 5. In this case, each of the detectors 2, 3, and 4 detects the voltages V1, V2, and V3 by electrostatic induction. Therefore, each phase of the three-phase alternating current can be obtained simply by bringing each electrode plate 31, 32, 33 close to the conductive wire from the insulating coating covering the conductive wire without directly contacting the conductive wire of each electric wire (pinching the electric wire). Voltages V1, V2, and V3 corresponding to the voltages are detected. In this case, the detector 3 detects the voltage of the S phase that is grounded among the three phases. The phase sequence inspection apparatus 1 operates using the voltage V2 detected by the detector 3 as a reference potential.

  The phase detection unit 5 includes six diodes 11 to 13 and 21 to 23 and two flip-flop circuits 14 and 24. The diodes 11 to 13 correspond to a first pulse signal generation unit in the present invention. In this case, the diodes 11 and 12 are connected in series by connecting the cathode of the diode 11 and the anode of the diode 12. Further, the detector 3, the anode of the diode 13, and the cathode of the diode 12 are connected, and the detector 4, the cathode of the diode 13, and the anode of the diode 11 are connected. The diodes 11 to 13 have a voltage V32 between the voltage V2 output from the detector 3 and the voltage V3 output from the detector 4 (the voltage V3 when the voltage V2 is the reference potential (0 V)). ) Is equal to or higher than a predetermined positive voltage (an example of the polarity of either a positive voltage or a negative voltage in the present invention, for example, +1.2 V), the diodes 11 and 12 connected in series become conductive and the positive predetermined voltage. When the voltage is limited to a negative predetermined voltage (for example, −0.6 V) or less, the diode 13 is turned on to limit the voltage to the negative predetermined voltage. Accordingly, when the AC voltage V32 is input, the diodes 11 to 13 are at a high level in synchronization with the positive half-cycle period of the voltage V32 (an example of the polarity at any polarity in the present invention). For example, the digital signal S32 (first pulse signal in the present invention) is generated that maintains +1.2 V) and maintains the low level (−0.6 V) in synchronization with the negative half-cycle period of the voltage V32.

  In this case, the positive predetermined voltage that the diodes 11 and 12 limit the voltage includes between the Vcc terminal / GND terminal of the flip-flop circuit 14 and between the input terminals (D terminal and CK terminal) / GND terminal of the flip-flop circuits 14 and 24. When the voltage is applied to the flip-flop circuit 14, the flip-flop circuit 14 has a voltage value at which the flip-flop circuit 14 can operate as a power supply voltage without being destroyed, and is applied between the NOR terminal / COM terminal of the display unit 6. When the display unit 6 is activated, the normal phase display image 41 is regulated to a displayable voltage value. Therefore, the number of diodes connected in series is not limited to two as in the diodes 11 and 12, but can be appropriately changed to one or more. Further, as the negative predetermined voltage that the diode 13 limits the voltage, when this negative predetermined voltage is applied between the Vcc terminal / GND terminal of the flip-flop circuit 14 and between the input terminals / GND terminals of the flip-flop circuits 14, 24. Further, the voltage value is set so as not to destroy the flip-flop circuits 14 and 24. Therefore, it is desirable that the negative predetermined voltage is close to 0V.

  The diodes 21 to 23 correspond to a second pulse signal generation unit in the present invention. In this case, the diodes 21 and 22 are connected in series by connecting the cathode of the diode 21 and the anode of the diode 22. Further, the detector 3, the anode of the diode 23, and the cathode of the diode 22 are connected, and the detector 2, the cathode of the diode 23, and the anode of the diode 21 are connected. The diodes 21 to 23 have a voltage V12 between the voltage V2 output from the detector 3 and the voltage V1 output from the detector 2 (the voltage V1 when the voltage V2 is the reference potential (0 V)). ) Is equal to or higher than a predetermined positive voltage (an example of the polarity of either a positive voltage or a negative voltage in the present invention, for example, +1.2 V), the diodes 21 and 22 connected in series become conductive and the predetermined positive voltage. When the voltage is limited to a negative predetermined voltage (for example, −0.6 V) or less, the diode 23 is turned on to limit the voltage to the negative predetermined voltage. Therefore, when the AC voltage V12 is input, the diodes 21 to 23 are at a high level (an example of the polarity at any polarity in the present invention) in synchronization with the positive half-cycle period of the voltage V12. For example, the digital signal S12 (second pulse signal in the present invention) is generated that maintains the low level (−0.6 V) in synchronization with the negative half cycle period of the voltage V12.

  In this case, the positive predetermined voltage that the diodes 21 and 22 limit the voltage includes between the Vcc terminal / GND terminal of the flip-flop circuit 24 and between the input terminals (D terminal and CK terminal) / GND terminal of the flip-flop circuits 14 and 24. Is applied to the REV terminal / COM terminal of the display unit 6 so that the flip-flop circuit 24 can operate as a power supply voltage without destroying the flip-flop circuits 14 and 24. Sometimes, the display unit 6 is activated and the reverse phase display image 42 is regulated to a displayable voltage value. Therefore, the number of diodes connected in series is not limited to two as in the diodes 21 and 22, but can be appropriately changed to one or more. The negative predetermined voltage that the diode 23 limits the voltage is when the negative predetermined voltage is applied between the Vcc terminal / GND terminal of the flip-flop circuit 24 and between the input terminal / GND terminals of the flip-flop circuits 14, 24. Further, the voltage value is set so as not to destroy the flip-flop circuits 14 and 24. Therefore, it is desirable that the negative predetermined voltage is close to 0V.

  The flip-flop circuit 14 corresponds to the first flip-flop circuit in the present invention, and as an example, is a low power consumption type D-flip-flop circuit that operates with a power supply voltage of 1.2 V, and has a ground terminal. (GND terminal) is connected to the detector 3 and operates with the voltage V2 as the ground voltage. In the flip-flop circuit 14, the digital signal S32 is input to the power supply terminal (Vcc terminal) and the signal input terminal (D terminal), and the digital signal S12 is input to the clock input terminal (CK terminal). With this configuration, the flip-flop circuit 14 operates using power based on the three-phase AC voltage as operating power. Specifically, the flip-flop circuit 14 operates using the digital signal S32 during a period of high voltage as a power source. Further, since the flip-flop circuit 14 receives the high level digital signal S32 at the D terminal during operation, the flip-flop circuit 14 inputs the digital signal S12 that shifts (rises) from the low level to the high level at the CK terminal during operation. In this case, the digital signal Sn (in the present invention) that shifts to the high level with respect to the low level (reference potential) in synchronization with the rising edge of the digital signal S12 (in synchronization with the transition to any polarity in the present invention). The first drive signal is output from the output terminal (Q terminal).

  The flip-flop circuit 24 corresponds to the second flip-flop circuit in the present invention, and is constituted by a D-flip-flop circuit of the same type as the flip-flop circuit 14 as an example, and the ground terminal (GND terminal) is the detector 3. To operate with the voltage V2 as the ground voltage. In the flip-flop circuit 24, the digital signal S12 is input to the power supply terminal (Vcc terminal) and the signal input terminal (D terminal), and the digital signal S32 is input to the clock input terminal (CK terminal). With this configuration, the flip-flop circuit 24 operates using power based on the three-phase AC voltage as operating power. Specifically, the flip-flop circuit 24 operates using the digital signal S12 during a period of high voltage as a power source. Further, since the flip-flop circuit 24 is in operation, the high-level digital signal S12 is input to the D terminal. Therefore, the digital signal S32 that shifts (rises) from the low level to the high level is input to the CK terminal during operation. In this case, the digital signal Sr (in the present invention) shifts to the high level with respect to the low level (reference potential) in synchronism with the rising edge of the digital signal S32 (in synchronization with the transition to any polarity in the present invention). The second drive signal) is output from the output terminal (Q terminal).

  The display unit 6 is a liquid crystal display unit configured by a liquid crystal panel as an example, and the voltage V2 output from the detector 3 is input to a reference potential terminal (COM terminal) to operate using the voltage V2 as a reference potential. The digital signal Sn is input to the positive phase display terminal (NOR terminal), and the digital signal Sr is input to the negative phase display terminal (REV terminal). Further, when a digital signal Sn is repeatedly input between the COM terminal and the NOR terminal, for example, 1.2 V and 0 V in a predetermined cycle, the display unit 6 uses the digital signal Sn as an operation power source to operate the liquid crystal panel. Is driven, and a normal phase display image 41 indicating that the three-phase alternating current is the positive phase is displayed on the liquid crystal panel. On the other hand, when a digital signal Sr that alternately repeats 1.2 V and 0 V, for example, at a predetermined cycle is input between the COM terminal and the REV terminal, the display unit 6 uses the digital signal Sr as an operation power source to operate the liquid crystal panel. Is driven to display the reverse phase display image 42 on the liquid crystal panel. That is, the display unit 6 operates by using power based on the three-phase AC voltage as operating power. Since the liquid crystal panel is a voltage driving element, generally, little power is consumed. Therefore, the display unit 6 is driven by the digital signals Sn and Sr output from the Q terminals of the flip-flop circuits 14 and 24, and can display the normal phase display image 41 and the reverse phase display image 42.

  Next, operation | movement of the phase sequence inspection apparatus 1 is demonstrated with reference to each figure.

  When inspecting the phase sequence of the three-phase AC using the phase sequence inspection device 1, first, as shown in FIG. 1, the detector is placed on the insulating film of the three-phase AC grounded S-phase wire 52. Set 3 (pinch). In this case, for example, the color of the electric wire 52 and the color of the electric wires 51, 53 are different from each other such that the color of the insulating film of the electric wire 52 is white and the color of the insulating film of the other electric wires 51, 53 is black. The S phase that is being used can be easily identified. Next, the detectors 2 and 4 are set on the electric wires 51 and 53. In this case, the detectors 2 and 4 can be set in any of the electric wires 51 and 53, and the phase sequence inspection apparatus 1 inspects whether the connection state is the normal phase or the reverse phase. First, as shown in FIG. 1, the following description will be made assuming that the detector 2 is set on the R-phase electric wire 51 and the detector 4 is set on the T-phase electric wire 53.

  First, the detectors 2 to 4 detect and output voltages V1 to V3 corresponding to the three-phase AC voltages of the electric wires 51 to 53, respectively. In this case, as shown in FIG. 2, the voltage V32 (the voltage Vts that is a relative voltage of the T phase with respect to the S phase voltage) input to the phase detector 5 is the voltage V12 (the S phase voltage). The phase is delayed by 300 ° (in other words, the phase is advanced by 60 °) relative to the R-phase relative voltage Vrs). Next, the digital signals S32 (see FIG. 2) in which the diodes 11 to 13 of the phase detector 5 maintain the high level during the positive half cycle period and the low level during the negative half cycle period in the AC voltage V32. ) Is generated. Further, the digital signals S12 in which the diodes 21 to 23 of the phase detector 5 maintain the high level during the positive half cycle period and the low level during the negative half cycle period in the AC voltage V12 (see FIG. 5). ) Is generated. In this case, as shown in the figure, the digital signal S32 shifts from the low level to the high level with a delay of 300 ° after the digital signal S12 shifts from the low level to the high level. Further, the digital signal S12 shifts from the low level to the high level 60 degrees after the digital signal S32 shifts from the low level to the high level. Further, the digital signal S32 shifts from the high level to the low level 120 ° after the digital signal S12 shifts from the low level to the high level. Further, the digital signal S12 shifts from the high level to the low level 60 degrees after the digital signal S32 shifts from the high level to the low level.

  Subsequently, the flip-flop circuit 14 inputs the digital signal S32 generated by the diodes 11 to 13 to the Vcc terminal and the D terminal. In FIG. 2, the signal waveform of the digital signal S32 input to the Vcc terminal is indicated as DFF14-Vcc, and the signal waveform of the digital signal S32 input to the D terminal is indicated as DFF14-D. In this case, the flip-flop circuit 14 operates only during the high level period using the digital signal S32 during the high level period as an operation power source. Subsequently, the flip-flop circuit 14 inputs, to the CK terminal, the digital signal S12 that shifts from the low level to the high level with a delay of 60 ° from the transition of the digital signal S32 from the low level to the high level (DFF14-CK in the figure). reference). At this time, since the flip-flop circuit 14 inputs the high-level digital signal S32 to the D terminal, the flip-flop circuit 14 synchronizes with the transition from the low level to the high level to the digital signal S32 input to the CK terminal. The digital signal Sn transitioning from the level to the high level is output from the Q terminal, and the digital signal Sn is maintained at the high level (see DFF14-Q in the figure). Subsequently, the flip-flop circuit 14 stops operating due to a voltage drop of the operating power supply in synchronization with the transition of the digital signal S32 from the high level to the low level. Therefore, in synchronization with the operation stop of the flip-flop circuit 14, the digital signal Sn output from the Q terminal shifts to a low level (see DFF14-Q in the figure).

  In this case, as shown in FIG. 2, since the digital signals S12 and S32 are periodically input to the flip-flop circuit 14, the flip-flop circuit 14 is synchronized with the transition of the digital signal S12 from the low level to the high level. A periodic digital signal Sn that shifts from the low level to the high level and that shifts from the high level to the low level in synchronization with the transition of the digital signal S32 from the high level to the low level is output from the Q terminal.

  On the other hand, the display unit 6 inputs a digital signal Sn output from the flip-flop circuit 14 that alternately repeats a high level and a low level to the NOR terminal, and is driven by the digital signal Sn to display a normal phase display image. 41 is displayed on the liquid crystal panel. Therefore, by displaying this normal phase display image 41, the electric wires 51, 52, 53 in which the detectors 2, 3, 4 are set are in this order R phase, S phase, and T phase, that is, the positive phase. Is inspected.

  The flip-flop circuit 24 inputs the digital signal S12 generated by the diodes 21 to 23 to the Vcc terminal and the D terminal. In FIG. 2, the signal waveform of the digital signal S12 input to the Vcc terminal is indicated as DFF24-Vcc, and the signal waveform of the digital signal S12 input to the D terminal is indicated as DFF24-D. In this case, the flip-flop circuit 24 operates only during the high level period using the digital signal S12 during the high level period as an operating power source. At this time, the digital signal S12 shifts from the low level to the high level with a delay of 60 ° after the digital signal S32 shifts from the low level to the high level. For this reason, the digital signal S32 (see DFF24-CK in the figure) input to the CK terminal does not shift from the low level to the high level during the operation period of the flip-flop circuit 24. Therefore, the flip-flop circuit 24 outputs the digital signal Sr maintained at the low level from the Q terminal. For this reason, since the display unit 6 inputs the digital signal Sr maintained at the low level to the REV terminal, the display unit 6 does not display the reverse phase display image 42. As a result, at this time, the display unit 6 displays only the normal phase display image 41.

  Next, contrary to the setting of the detectors 2 and 4 to the electric wires 51 and 53, the detector 4 is set on the R-phase electric wire 51, and the detector 2 is attached to the three-phase AC T-phase electric wire 53. The operation of the phase sequence inspection apparatus 1 will be described as set.

  In this example, the voltage V12 (Vrs) described above corresponds to the voltage V32 (voltage Vrs that is a relative voltage of the R phase with respect to the voltage of the S phase), and the voltage V32 (Vts) described above is the voltage V12 (Vts). The digital signal S12 (Vrs) is equivalent to the digital signal S32 (Vrs), and the digital signal S32 (Vts) is equivalent to the T-phase relative voltage with respect to the S-phase voltage. ) Corresponds to the digital signal S12 (Vts). Further, since the connection of the diodes 11 to 13 and the flip-flop circuit 14 of the phase detection unit 5 and the connection of the diodes 21 to 23 and the flip-flop circuit 24 are symmetrically connected, the diodes 21 to 23 and the flip-flop circuit 24 are The diodes 11 to 13 and the flip-flop circuit 14 operate in the same manner, and the diodes 11 to 13 and the flip-flop circuit 14 operate in the same manner as the diodes 21 to 23 and the flip-flop circuit 24 described above. Therefore, since the operation in which the operations of the flip-flop circuits 14 and 24 are reversed as compared with the operation when the wires 51 to 53 are in the normal phase, the redundant description is omitted. In this example, as shown in FIG. 3, the flip-flop circuit 14 outputs a digital signal Sn maintained at a low level. As shown in the figure, the flip-flop circuit 24 shifts from the low level to the high level in synchronization with the shift of the digital signal S32 from the low level to the high level, and the digital signal S12 shifts from the high level to the low level. A periodic digital signal Sr that shifts from a high level to a low level in synchronization with the transition to is output from the Q terminal.

  Next, the display unit 6 inputs a digital signal Sr output from the flip-flop circuit 24, which periodically alternates between a high level and a low level, to the REV terminal, and is driven by this digital signal Sr to display a reverse phase display image. 42 is displayed on the liquid crystal panel. The display unit 6 inputs the digital signal Sn output from the flip-flop circuit 14 to the NOR terminal. In this case, since the digital signal Sn is maintained at a low level, the display unit 6 displays only the reverse phase display image 42 without displaying the normal phase display image 41. Therefore, by displaying this reverse phase display image 42, the electric wires 51, 52, 53 in which the detectors 2, 3, 4 are set respectively are in this order T phase, S phase, and R phase, that is, reverse phase. Is inspected.

  As described above, according to the phase sequence inspection apparatus 1, the flip-flop circuit 14 operates with the voltage V2 as the reference potential and the digital signal S32 during the period when the voltage V2 is a positive voltage as an operation power supply, and the digital signal during the operation. A digital signal Sn that shifts to a high level with respect to the reference potential in synchronism with the transition of S12 to the high level is output, and the flip-flop circuit 24 uses the voltage V2 as the reference potential and is a digital signal during a period of positive voltage. The digital signal Sr that operates as a power source for operation S12 and shifts to a high level with respect to the reference potential in synchronization with the transition of the digital signal S32 to a high level during operation is output. Driven to display normal phase display image 41 and driven by digital signal Sr to reverse phase By displaying the display image 42, the electric power of each phase can be used as the operating power from above the insulating coating of the three-phase AC circuit, so that the measurement location is not restricted while avoiding the risk of electric shock. Moreover, the phase sequence inspection apparatus 1 that can eliminate the need for battery replacement work and charging work can be realized.

  In addition, this invention is not limited to said structure. For example, in the above configuration, the configuration in which the voltage is limited to the positive predetermined voltage (1.2 V) by the two diodes 11 and 12 and the two diodes 21 and 22 has been described. Instead of 22, it is also possible to employ a configuration in which two constant voltage circuits are provided and the voltage is limited to a predetermined positive voltage. In this example, each of the flip-flop circuits 14 and 24 is constituted by a D-flip flop circuit, but may be constituted by various types of flip-flop circuits such as a JK-flip flop circuit and an RS-flip flop circuit. it can. Further, the configuration using a positive voltage as the operating power supply for the flip-flop circuits 14 and 24 has been described. However, the power supply voltage of the operating power input to the Vcc terminal, D terminal and CK terminal of the flip-flop circuits 14 and 24 is set to 0V ( It is also possible to adopt a configuration in which a negative voltage is input to the GND terminal, that is, a so-called negative power source. In this configuration, for example, the voltage V2 is input to the Vcc terminal and D terminal of each flip-flop circuit 14, 24, the diodes 11-13, 21-24 are connected in the opposite direction to the above configuration, and the flip-flop The GND terminal of the flip-flop circuit 14 is connected to the detector 4, and the GND terminal of the flip-flop circuit 24 is connected to the detector 2. Moreover, although the example which comprises the display part 6 using a liquid crystal panel was mentioned above, the display part 6 is displayed using the other low current consumption type display (LED etc.) which can be driven with the electric current obtained by electrostatic induction. It can also be configured.

1 is a circuit diagram showing a configuration of a phase sequence inspection device 1. FIG. It is a timing chart for demonstrating operation | movement of the phase sequence inspection apparatus 1 in the normal phase state about a three-phase alternating current line. It is a timing chart for demonstrating operation | movement of the phase sequence inspection apparatus 1 in the reverse phase state about a three-phase alternating current line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase sequence inspection apparatus 2-4 Detector 5 Phase detection part 6 Display part 11-13, 21-23 Diode 14, 24 Flip-flop circuit 41 Normal phase display image 42 Reversed phase display image 51-53 Electric wire V1-V3, V12 , V32 Voltage S12, S32, Sn, Sr Digital signal

Claims (1)

First, second, and third detectors for detecting first, second, and third detection voltages from the three phases of the three-phase alternating current by electrostatic induction;
When the third detection voltage is a positive voltage or a negative voltage with respect to the first detection voltage detected from one of the three phases that is grounded, the polarity becomes the first. A first pulse signal generator that generates one pulse signal;
A second pulse signal generation unit configured to generate a second pulse signal having the polarity when the second detection voltage is any one of the polarities with respect to the first detection voltage;
The first detection voltage is used as a reference potential, and the first pulse signal in a period in which the voltage is any one of the polarities operates as a power source, and the one of the polarities of the second pulse signal during operation A first flip-flop circuit that outputs a first drive signal that shifts to one of the polarities with respect to the reference potential in synchronization with the shift to
The first detection voltage is used as a reference potential, and the second pulse signal in a period in which the voltage is any one of the polarities operates as a power source, and the one polarity of the first pulse signal during operation A second flip-flop circuit that outputs a second drive signal that shifts to any one of the polarities with respect to the reference potential in synchronization with the shift to
A phase sequence display device comprising: a display unit that is driven by the first drive signal to display a normal phase display image and that is driven by the second drive signal to display a reverse phase display image.

Images